stm32f1_staging/stm32f103/i2c1/
oar1.rs

1///Register `OAR1` reader
2pub type R = crate::R<OAR1rs>;
3///Register `OAR1` writer
4pub type W = crate::W<OAR1rs>;
5///Field `ADD` reader - Interface address
6pub type ADD_R = crate::FieldReader<u16>;
7///Field `ADD` writer - Interface address
8pub type ADD_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16, crate::Safe>;
9/**Addressing mode (slave mode)
10
11Value on reset: 0*/
12#[cfg_attr(feature = "defmt", derive(defmt::Format))]
13#[derive(Clone, Copy, Debug, PartialEq, Eq)]
14pub enum ADDMODE {
15    ///0: 7-bit slave address
16    Add7 = 0,
17    ///1: 10-bit slave address
18    Add10 = 1,
19}
20impl From<ADDMODE> for bool {
21    #[inline(always)]
22    fn from(variant: ADDMODE) -> Self {
23        variant as u8 != 0
24    }
25}
26///Field `ADDMODE` reader - Addressing mode (slave mode)
27pub type ADDMODE_R = crate::BitReader<ADDMODE>;
28impl ADDMODE_R {
29    ///Get enumerated values variant
30    #[inline(always)]
31    pub const fn variant(&self) -> ADDMODE {
32        match self.bits {
33            false => ADDMODE::Add7,
34            true => ADDMODE::Add10,
35        }
36    }
37    ///7-bit slave address
38    #[inline(always)]
39    pub fn is_add7(&self) -> bool {
40        *self == ADDMODE::Add7
41    }
42    ///10-bit slave address
43    #[inline(always)]
44    pub fn is_add10(&self) -> bool {
45        *self == ADDMODE::Add10
46    }
47}
48///Field `ADDMODE` writer - Addressing mode (slave mode)
49pub type ADDMODE_W<'a, REG> = crate::BitWriter<'a, REG, ADDMODE>;
50impl<'a, REG> ADDMODE_W<'a, REG>
51where
52    REG: crate::Writable + crate::RegisterSpec,
53{
54    ///7-bit slave address
55    #[inline(always)]
56    pub fn add7(self) -> &'a mut crate::W<REG> {
57        self.variant(ADDMODE::Add7)
58    }
59    ///10-bit slave address
60    #[inline(always)]
61    pub fn add10(self) -> &'a mut crate::W<REG> {
62        self.variant(ADDMODE::Add10)
63    }
64}
65impl R {
66    ///Bits 0:9 - Interface address
67    #[inline(always)]
68    pub fn add(&self) -> ADD_R {
69        ADD_R::new(self.bits & 0x03ff)
70    }
71    ///Bit 15 - Addressing mode (slave mode)
72    #[inline(always)]
73    pub fn addmode(&self) -> ADDMODE_R {
74        ADDMODE_R::new(((self.bits >> 15) & 1) != 0)
75    }
76}
77impl core::fmt::Debug for R {
78    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
79        f.debug_struct("OAR1")
80            .field("addmode", &self.addmode())
81            .field("add", &self.add())
82            .finish()
83    }
84}
85impl W {
86    ///Bits 0:9 - Interface address
87    #[inline(always)]
88    pub fn add(&mut self) -> ADD_W<OAR1rs> {
89        ADD_W::new(self, 0)
90    }
91    ///Bit 15 - Addressing mode (slave mode)
92    #[inline(always)]
93    pub fn addmode(&mut self) -> ADDMODE_W<OAR1rs> {
94        ADDMODE_W::new(self, 15)
95    }
96}
97/**Own address register 1
98
99You can [`read`](crate::Reg::read) this register and get [`oar1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`oar1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
100
101See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#I2C1:OAR1)*/
102pub struct OAR1rs;
103impl crate::RegisterSpec for OAR1rs {
104    type Ux = u16;
105}
106///`read()` method returns [`oar1::R`](R) reader structure
107impl crate::Readable for OAR1rs {}
108///`write(|w| ..)` method takes [`oar1::W`](W) writer structure
109impl crate::Writable for OAR1rs {
110    type Safety = crate::Unsafe;
111}
112///`reset()` method sets OAR1 to value 0
113impl crate::Resettable for OAR1rs {}
stm32f1_staging/stm32f103/i2c1/oar1.rs

stm32f1_staging/stm32f103/i2c1/
oar1.rs
