stm32f1_staging/stm32f102/
mod.rs

1/*!Peripheral access API for STM32F102 microcontrollers (generated using svd2rust v0.36.1 (a85deda 2025-04-04))
2
3You can find an overview of the generated API [here].
4
5API features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.
6
7[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api
8[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased
9[repository]: https://github.com/rust-embedded/svd2rust*/
10///Number available in the NVIC for configuring priority
11pub const NVIC_PRIO_BITS: u8 = 4;
12#[cfg(feature = "rt")]
13pub use self::Interrupt as interrupt;
14pub use cortex_m::peripheral::Peripherals as CorePeripherals;
15pub use cortex_m::peripheral::{
16    CBP, CPUID, DCB, DWT, FPB, ITM, MPU, NVIC, SCB, SYST, TPIU,
17};
18#[cfg(feature = "rt")]
19pub use cortex_m_rt::interrupt;
20#[cfg(feature = "rt")]
21extern "C" {
22    fn WWDG();
23    fn PVD();
24    fn TAMPER();
25    fn RTC();
26    fn FLASH();
27    fn RCC();
28    fn EXTI0();
29    fn EXTI1();
30    fn EXTI2();
31    fn EXTI3();
32    fn EXTI4();
33    fn DMA1_CHANNEL1();
34    fn DMA1_CHANNEL2();
35    fn DMA1_CHANNEL3();
36    fn DMA1_CHANNEL4();
37    fn DMA1_CHANNEL5();
38    fn DMA1_CHANNEL6();
39    fn DMA1_CHANNEL7();
40    fn ADC1_2();
41    fn USB_HP_CAN_TX();
42    fn USB_LP_CAN_RX0();
43    fn EXTI9_5();
44    fn TIM1_BRK();
45    fn TIM1_UP();
46    fn TIM1_TRG_COM();
47    fn TIM1_CC();
48    fn TIM2();
49    fn TIM3();
50    fn TIM4();
51    fn I2C1_EV();
52    fn I2C1_ER();
53    fn I2C2_EV();
54    fn I2C2_ER();
55    fn SPI1();
56    fn SPI2();
57    fn USART1();
58    fn USART2();
59    fn USART3();
60    fn EXTI15_10();
61    fn RTCALARM();
62    fn USBWAKEUP();
63    fn TIM8_BRK();
64    fn TIM8_UP();
65    fn TIM8_TRG_COM();
66    fn TIM8_CC();
67    fn ADC3();
68    fn FSMC();
69    fn SDIO();
70    fn TIM5();
71    fn SPI3();
72    fn UART4();
73    fn UART5();
74    fn TIM6();
75    fn TIM7();
76    fn DMA2_CHANNEL1();
77    fn DMA2_CHANNEL2();
78    fn DMA2_CHANNEL3();
79    fn DMA2_CHANNEL4_5();
80}
81#[doc(hidden)]
82#[repr(C)]
83pub union Vector {
84    _handler: unsafe extern "C" fn(),
85    _reserved: u32,
86}
87#[cfg(feature = "rt")]
88#[doc(hidden)]
89#[link_section = ".vector_table.interrupts"]
90#[no_mangle]
91pub static __INTERRUPTS: [Vector; 60] = [
92    Vector { _handler: WWDG },
93    Vector { _handler: PVD },
94    Vector { _handler: TAMPER },
95    Vector { _handler: RTC },
96    Vector { _handler: FLASH },
97    Vector { _handler: RCC },
98    Vector { _handler: EXTI0 },
99    Vector { _handler: EXTI1 },
100    Vector { _handler: EXTI2 },
101    Vector { _handler: EXTI3 },
102    Vector { _handler: EXTI4 },
103    Vector { _handler: DMA1_CHANNEL1 },
104    Vector { _handler: DMA1_CHANNEL2 },
105    Vector { _handler: DMA1_CHANNEL3 },
106    Vector { _handler: DMA1_CHANNEL4 },
107    Vector { _handler: DMA1_CHANNEL5 },
108    Vector { _handler: DMA1_CHANNEL6 },
109    Vector { _handler: DMA1_CHANNEL7 },
110    Vector { _handler: ADC1_2 },
111    Vector { _handler: USB_HP_CAN_TX },
112    Vector { _handler: USB_LP_CAN_RX0 },
113    Vector { _reserved: 0 },
114    Vector { _reserved: 0 },
115    Vector { _handler: EXTI9_5 },
116    Vector { _handler: TIM1_BRK },
117    Vector { _handler: TIM1_UP },
118    Vector { _handler: TIM1_TRG_COM },
119    Vector { _handler: TIM1_CC },
120    Vector { _handler: TIM2 },
121    Vector { _handler: TIM3 },
122    Vector { _handler: TIM4 },
123    Vector { _handler: I2C1_EV },
124    Vector { _handler: I2C1_ER },
125    Vector { _handler: I2C2_EV },
126    Vector { _handler: I2C2_ER },
127    Vector { _handler: SPI1 },
128    Vector { _handler: SPI2 },
129    Vector { _handler: USART1 },
130    Vector { _handler: USART2 },
131    Vector { _handler: USART3 },
132    Vector { _handler: EXTI15_10 },
133    Vector { _handler: RTCALARM },
134    Vector { _handler: USBWAKEUP },
135    Vector { _handler: TIM8_BRK },
136    Vector { _handler: TIM8_UP },
137    Vector { _handler: TIM8_TRG_COM },
138    Vector { _handler: TIM8_CC },
139    Vector { _handler: ADC3 },
140    Vector { _handler: FSMC },
141    Vector { _handler: SDIO },
142    Vector { _handler: TIM5 },
143    Vector { _handler: SPI3 },
144    Vector { _handler: UART4 },
145    Vector { _handler: UART5 },
146    Vector { _handler: TIM6 },
147    Vector { _handler: TIM7 },
148    Vector { _handler: DMA2_CHANNEL1 },
149    Vector { _handler: DMA2_CHANNEL2 },
150    Vector { _handler: DMA2_CHANNEL3 },
151    Vector {
152        _handler: DMA2_CHANNEL4_5,
153    },
154];
155///Enumeration of all the interrupts.
156#[cfg_attr(feature = "defmt", derive(defmt::Format))]
157#[derive(Copy, Clone, Debug, PartialEq, Eq)]
158#[repr(u16)]
159pub enum Interrupt {
160    ///0 - Window Watchdog interrupt
161    WWDG = 0,
162    ///1 - PVD through EXTI line detection interrupt
163    PVD = 1,
164    ///2 - Tamper interrupt
165    TAMPER = 2,
166    ///3 - RTC global interrupt
167    RTC = 3,
168    ///4 - Flash global interrupt
169    FLASH = 4,
170    ///5 - RCC global interrupt
171    RCC = 5,
172    ///6 - EXTI Line0 interrupt
173    EXTI0 = 6,
174    ///7 - EXTI Line1 interrupt
175    EXTI1 = 7,
176    ///8 - EXTI Line2 interrupt
177    EXTI2 = 8,
178    ///9 - EXTI Line3 interrupt
179    EXTI3 = 9,
180    ///10 - EXTI Line4 interrupt
181    EXTI4 = 10,
182    ///11 - DMA1 Channel1 global interrupt
183    DMA1_CHANNEL1 = 11,
184    ///12 - DMA1 Channel2 global interrupt
185    DMA1_CHANNEL2 = 12,
186    ///13 - DMA1 Channel3 global interrupt
187    DMA1_CHANNEL3 = 13,
188    ///14 - DMA1 Channel4 global interrupt
189    DMA1_CHANNEL4 = 14,
190    ///15 - DMA1 Channel5 global interrupt
191    DMA1_CHANNEL5 = 15,
192    ///16 - DMA1 Channel6 global interrupt
193    DMA1_CHANNEL6 = 16,
194    ///17 - DMA1 Channel7 global interrupt
195    DMA1_CHANNEL7 = 17,
196    ///18 - ADC1 and ADC2 global interrupt
197    ADC1_2 = 18,
198    ///19 - USB High Priority or CAN TX interrupts
199    USB_HP_CAN_TX = 19,
200    ///20 - USB Low Priority or CAN RX0 interrupts
201    USB_LP_CAN_RX0 = 20,
202    ///23 - EXTI Line\[9:5\] interrupts
203    EXTI9_5 = 23,
204    ///24 - TIM1 Break interrupt
205    TIM1_BRK = 24,
206    ///25 - TIM1 Update interrupt
207    TIM1_UP = 25,
208    ///26 - TIM1 Trigger and Commutation interrupts
209    TIM1_TRG_COM = 26,
210    ///27 - TIM1 Capture Compare interrupt
211    TIM1_CC = 27,
212    ///28 - TIM2 global interrupt
213    TIM2 = 28,
214    ///29 - TIM3 global interrupt
215    TIM3 = 29,
216    ///30 - TIM4 global interrupt
217    TIM4 = 30,
218    ///31 - I2C event interrupt
219    I2C1_EV = 31,
220    ///32 - I2C errot interrupt
221    I2C1_ER = 32,
222    ///33 - I2C event interrupt
223    I2C2_EV = 33,
224    ///34 - I2C errot interrupt
225    I2C2_ER = 34,
226    ///35 - SPI1 global interrupt
227    SPI1 = 35,
228    ///36 - SPI2 global interrupt
229    SPI2 = 36,
230    ///37 - USART1 global interrupt
231    USART1 = 37,
232    ///38 - USART2 global interrupt
233    USART2 = 38,
234    ///39 - USART3 global interrupt
235    USART3 = 39,
236    ///40 - EXTI Line\[15:10\] interrupts
237    EXTI15_10 = 40,
238    ///41 - RTC Alarms through EXTI line interrupt
239    RTCALARM = 41,
240    ///42 - USB wakeup from suspend through EXTI line interrupt
241    USBWAKEUP = 42,
242    ///43 - TIM8 Break interrupt
243    TIM8_BRK = 43,
244    ///44 - TIM8 Update interrupt
245    TIM8_UP = 44,
246    ///45 - TIM8 Trigger and Commutation interrupts
247    TIM8_TRG_COM = 45,
248    ///46 - TIM8 Capture Compare interrupt
249    TIM8_CC = 46,
250    ///47 - ADC3 global interrupt
251    ADC3 = 47,
252    ///48 - FSMC global interrupt
253    FSMC = 48,
254    ///49 - SDIO global interrupt
255    SDIO = 49,
256    ///50 - TIM5 global interrupt
257    TIM5 = 50,
258    ///51 - SPI3 global interrupt
259    SPI3 = 51,
260    ///52 - UART4 global interrupt
261    UART4 = 52,
262    ///53 - UART5 global interrupt
263    UART5 = 53,
264    ///54 - TIM6 global interrupt
265    TIM6 = 54,
266    ///55 - TIM7 global interrupt
267    TIM7 = 55,
268    ///56 - DMA2 Channel1 global interrupt
269    DMA2_CHANNEL1 = 56,
270    ///57 - DMA2 Channel2 global interrupt
271    DMA2_CHANNEL2 = 57,
272    ///58 - DMA2 Channel3 global interrupt
273    DMA2_CHANNEL3 = 58,
274    ///59 - DMA2 Channel4 and DMA2 Channel5 global interrupt
275    DMA2_CHANNEL4_5 = 59,
276}
277unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
278    #[inline(always)]
279    fn number(self) -> u16 {
280        self as u16
281    }
282}
283///Power control
284///
285///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#PWR)
286pub type PWR = crate::Periph<pwr::RegisterBlock, 0x4000_7000>;
287impl core::fmt::Debug for PWR {
288    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
289        f.debug_struct("PWR").finish()
290    }
291}
292///Power control
293pub mod pwr;
294///Reset and clock control
295///
296///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#RCC)
297pub type RCC = crate::Periph<rcc::RegisterBlock, 0x4002_1000>;
298impl core::fmt::Debug for RCC {
299    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
300        f.debug_struct("RCC").finish()
301    }
302}
303///Reset and clock control
304pub mod rcc;
305///General purpose I/O
306///
307///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#GPIOA)
308pub type GPIOA = crate::Periph<gpioa::RegisterBlock, 0x4001_0800>;
309impl core::fmt::Debug for GPIOA {
310    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
311        f.debug_struct("GPIOA").finish()
312    }
313}
314///General purpose I/O
315pub mod gpioa;
316///General purpose I/O
317///
318///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#GPIOA)
319pub type GPIOB = crate::Periph<gpioa::RegisterBlock, 0x4001_0c00>;
320impl core::fmt::Debug for GPIOB {
321    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
322        f.debug_struct("GPIOB").finish()
323    }
324}
325///General purpose I/O
326pub use self::gpioa as gpiob;
327///General purpose I/O
328///
329///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#GPIOA)
330pub type GPIOC = crate::Periph<gpioa::RegisterBlock, 0x4001_1000>;
331impl core::fmt::Debug for GPIOC {
332    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
333        f.debug_struct("GPIOC").finish()
334    }
335}
336///General purpose I/O
337pub use self::gpioa as gpioc;
338///General purpose I/O
339///
340///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#GPIOA)
341pub type GPIOD = crate::Periph<gpioa::RegisterBlock, 0x4001_1400>;
342impl core::fmt::Debug for GPIOD {
343    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
344        f.debug_struct("GPIOD").finish()
345    }
346}
347///General purpose I/O
348pub use self::gpioa as gpiod;
349///General purpose I/O
350///
351///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#GPIOA)
352pub type GPIOE = crate::Periph<gpioa::RegisterBlock, 0x4001_1800>;
353impl core::fmt::Debug for GPIOE {
354    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
355        f.debug_struct("GPIOE").finish()
356    }
357}
358///General purpose I/O
359pub use self::gpioa as gpioe;
360///General purpose I/O
361///
362///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#GPIOA)
363pub type GPIOF = crate::Periph<gpioa::RegisterBlock, 0x4001_1c00>;
364impl core::fmt::Debug for GPIOF {
365    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
366        f.debug_struct("GPIOF").finish()
367    }
368}
369///General purpose I/O
370pub use self::gpioa as gpiof;
371///General purpose I/O
372///
373///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#GPIOA)
374pub type GPIOG = crate::Periph<gpioa::RegisterBlock, 0x4001_2000>;
375impl core::fmt::Debug for GPIOG {
376    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
377        f.debug_struct("GPIOG").finish()
378    }
379}
380///General purpose I/O
381pub use self::gpioa as gpiog;
382///Alternate function I/O
383///
384///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#AFIO)
385pub type AFIO = crate::Periph<afio::RegisterBlock, 0x4001_0000>;
386impl core::fmt::Debug for AFIO {
387    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
388        f.debug_struct("AFIO").finish()
389    }
390}
391///Alternate function I/O
392pub mod afio;
393///EXTI
394///
395///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#EXTI)
396pub type EXTI = crate::Periph<exti::RegisterBlock, 0x4001_0400>;
397impl core::fmt::Debug for EXTI {
398    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
399        f.debug_struct("EXTI").finish()
400    }
401}
402///EXTI
403pub mod exti;
404///DMA controller
405///
406///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#DMA1)
407pub type DMA1 = crate::Periph<dma1::RegisterBlock, 0x4002_0000>;
408impl core::fmt::Debug for DMA1 {
409    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
410        f.debug_struct("DMA1").finish()
411    }
412}
413///DMA controller
414pub mod dma1;
415///DMA controller
416///
417///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#DMA1)
418pub type DMA2 = crate::Periph<dma1::RegisterBlock, 0x4002_0400>;
419impl core::fmt::Debug for DMA2 {
420    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
421        f.debug_struct("DMA2").finish()
422    }
423}
424///DMA controller
425pub use self::dma1 as dma2;
426///Real time clock
427///
428///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#RTC)
429pub type RTC = crate::Periph<rtc::RegisterBlock, 0x4000_2800>;
430impl core::fmt::Debug for RTC {
431    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
432        f.debug_struct("RTC").finish()
433    }
434}
435///Real time clock
436pub mod rtc;
437///Independent watchdog
438///
439///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#IWDG)
440pub type IWDG = crate::Periph<iwdg::RegisterBlock, 0x4000_3000>;
441impl core::fmt::Debug for IWDG {
442    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
443        f.debug_struct("IWDG").finish()
444    }
445}
446///Independent watchdog
447pub mod iwdg;
448///Window watchdog
449///
450///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#WWDG)
451pub type WWDG = crate::Periph<wwdg::RegisterBlock, 0x4000_2c00>;
452impl core::fmt::Debug for WWDG {
453    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
454        f.debug_struct("WWDG").finish()
455    }
456}
457///Window watchdog
458pub mod wwdg;
459///General purpose timer
460///
461///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#TIM2)
462pub type TIM2 = crate::Periph<tim2::RegisterBlock, 0x4000_0000>;
463impl core::fmt::Debug for TIM2 {
464    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
465        f.debug_struct("TIM2").finish()
466    }
467}
468///General purpose timer
469pub mod tim2;
470///General purpose timer
471///
472///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#TIM2)
473pub type TIM3 = crate::Periph<tim2::RegisterBlock, 0x4000_0400>;
474impl core::fmt::Debug for TIM3 {
475    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
476        f.debug_struct("TIM3").finish()
477    }
478}
479///General purpose timer
480pub use self::tim2 as tim3;
481///Inter integrated circuit
482///
483///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#I2C1)
484pub type I2C1 = crate::Periph<i2c1::RegisterBlock, 0x4000_5400>;
485impl core::fmt::Debug for I2C1 {
486    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
487        f.debug_struct("I2C1").finish()
488    }
489}
490///Inter integrated circuit
491pub mod i2c1;
492///Inter integrated circuit
493///
494///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#I2C1)
495pub type I2C2 = crate::Periph<i2c1::RegisterBlock, 0x4000_5800>;
496impl core::fmt::Debug for I2C2 {
497    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
498        f.debug_struct("I2C2").finish()
499    }
500}
501///Inter integrated circuit
502pub use self::i2c1 as i2c2;
503///Serial peripheral interface
504///
505///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#SPI1)
506pub type SPI1 = crate::Periph<spi1::RegisterBlock, 0x4001_3000>;
507impl core::fmt::Debug for SPI1 {
508    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
509        f.debug_struct("SPI1").finish()
510    }
511}
512///Serial peripheral interface
513pub mod spi1;
514///Universal synchronous asynchronous receiver transmitter
515///
516///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#USART1)
517pub type USART1 = crate::Periph<usart1::RegisterBlock, 0x4001_3800>;
518impl core::fmt::Debug for USART1 {
519    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
520        f.debug_struct("USART1").finish()
521    }
522}
523///Universal synchronous asynchronous receiver transmitter
524pub mod usart1;
525///Universal synchronous asynchronous receiver transmitter
526///
527///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#USART1)
528pub type USART2 = crate::Periph<usart1::RegisterBlock, 0x4000_4400>;
529impl core::fmt::Debug for USART2 {
530    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
531        f.debug_struct("USART2").finish()
532    }
533}
534///Universal synchronous asynchronous receiver transmitter
535pub use self::usart1 as usart2;
536///Universal synchronous asynchronous receiver transmitter
537///
538///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#USART1)
539pub type USART3 = crate::Periph<usart1::RegisterBlock, 0x4000_4800>;
540impl core::fmt::Debug for USART3 {
541    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
542        f.debug_struct("USART3").finish()
543    }
544}
545///Universal synchronous asynchronous receiver transmitter
546pub use self::usart1 as usart3;
547///Analog to digital converter
548///
549///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#ADC1)
550pub type ADC1 = crate::Periph<adc1::RegisterBlock, 0x4001_2400>;
551impl core::fmt::Debug for ADC1 {
552    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
553        f.debug_struct("ADC1").finish()
554    }
555}
556///Analog to digital converter
557pub mod adc1;
558///Analog to digital converter
559///
560///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#ADC3)
561pub type ADC3 = crate::Periph<adc3::RegisterBlock, 0x4001_3c00>;
562impl core::fmt::Debug for ADC3 {
563    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
564        f.debug_struct("ADC3").finish()
565    }
566}
567///Analog to digital converter
568pub mod adc3;
569///CRC calculation unit
570///
571///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#CRC)
572pub type CRC = crate::Periph<crc::RegisterBlock, 0x4002_3000>;
573impl core::fmt::Debug for CRC {
574    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
575        f.debug_struct("CRC").finish()
576    }
577}
578///CRC calculation unit
579pub mod crc;
580///FLASH
581///
582///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#FLASH)
583pub type FLASH = crate::Periph<flash::RegisterBlock, 0x4002_2000>;
584impl core::fmt::Debug for FLASH {
585    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
586        f.debug_struct("FLASH").finish()
587    }
588}
589///FLASH
590pub mod flash;
591///Debug support
592///
593///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#DBGMCU)
594pub type DBGMCU = crate::Periph<dbgmcu::RegisterBlock, 0xe004_2000>;
595impl core::fmt::Debug for DBGMCU {
596    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
597        f.debug_struct("DBGMCU").finish()
598    }
599}
600///Debug support
601pub mod dbgmcu;
602///Backup registers
603///
604///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#BKP)
605pub type BKP = crate::Periph<bkp::RegisterBlock, 0x4000_6c04>;
606impl core::fmt::Debug for BKP {
607    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
608        f.debug_struct("BKP").finish()
609    }
610}
611///Backup registers
612pub mod bkp;
613///Flexible static memory controller
614///
615///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#FSMC)
616pub type FSMC = crate::Periph<fsmc::RegisterBlock, 0xa000_0000>;
617impl core::fmt::Debug for FSMC {
618    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
619        f.debug_struct("FSMC").finish()
620    }
621}
622///Flexible static memory controller
623pub mod fsmc;
624///USB on the go full speed
625///
626///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#OTG_FS_DEVICE)
627pub type OTG_FS_DEVICE = crate::Periph<otg_fs_device::RegisterBlock, 0x5000_0800>;
628impl core::fmt::Debug for OTG_FS_DEVICE {
629    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
630        f.debug_struct("OTG_FS_DEVICE").finish()
631    }
632}
633///USB on the go full speed
634pub mod otg_fs_device;
635///USB on the go full speed
636///
637///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#OTG_FS_GLOBAL)
638pub type OTG_FS_GLOBAL = crate::Periph<otg_fs_global::RegisterBlock, 0x5000_0000>;
639impl core::fmt::Debug for OTG_FS_GLOBAL {
640    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
641        f.debug_struct("OTG_FS_GLOBAL").finish()
642    }
643}
644///USB on the go full speed
645pub mod otg_fs_global;
646///USB on the go full speed
647///
648///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#OTG_FS_HOST)
649pub type OTG_FS_HOST = crate::Periph<otg_fs_host::RegisterBlock, 0x5000_0400>;
650impl core::fmt::Debug for OTG_FS_HOST {
651    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
652        f.debug_struct("OTG_FS_HOST").finish()
653    }
654}
655///USB on the go full speed
656pub mod otg_fs_host;
657///USB on the go full speed
658///
659///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#OTG_FS_PWRCLK)
660pub type OTG_FS_PWRCLK = crate::Periph<otg_fs_pwrclk::RegisterBlock, 0x5000_0e00>;
661impl core::fmt::Debug for OTG_FS_PWRCLK {
662    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
663        f.debug_struct("OTG_FS_PWRCLK").finish()
664    }
665}
666///USB on the go full speed
667pub mod otg_fs_pwrclk;
668///Secure digital input/output interface
669///
670///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#SDIO)
671pub type SDIO = crate::Periph<sdio::RegisterBlock, 0x4001_8000>;
672impl core::fmt::Debug for SDIO {
673    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
674        f.debug_struct("SDIO").finish()
675    }
676}
677///Secure digital input/output interface
678pub mod sdio;
679///General purpose timer
680///
681///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#TIM13)
682pub type TIM13 = crate::Periph<tim13::RegisterBlock, 0x4000_1c00>;
683impl core::fmt::Debug for TIM13 {
684    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
685        f.debug_struct("TIM13").finish()
686    }
687}
688///General purpose timer
689pub mod tim13;
690///General purpose timer
691///
692///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#TIM13)
693pub type TIM10 = crate::Periph<tim13::RegisterBlock, 0x4001_5000>;
694impl core::fmt::Debug for TIM10 {
695    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
696        f.debug_struct("TIM10").finish()
697    }
698}
699///General purpose timer
700pub use self::tim13 as tim10;
701///General purpose timer
702///
703///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#TIM13)
704pub type TIM11 = crate::Periph<tim13::RegisterBlock, 0x4001_5400>;
705impl core::fmt::Debug for TIM11 {
706    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
707        f.debug_struct("TIM11").finish()
708    }
709}
710///General purpose timer
711pub use self::tim13 as tim11;
712///General purpose timer
713///
714///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#TIM9)
715pub type TIM9 = crate::Periph<tim9::RegisterBlock, 0x4001_4c00>;
716impl core::fmt::Debug for TIM9 {
717    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
718        f.debug_struct("TIM9").finish()
719    }
720}
721///General purpose timer
722pub mod tim9;
723///General purpose timer
724///
725///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#TIM9)
726pub type TIM12 = crate::Periph<tim9::RegisterBlock, 0x4000_1800>;
727impl core::fmt::Debug for TIM12 {
728    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
729        f.debug_struct("TIM12").finish()
730    }
731}
732///General purpose timer
733pub use self::tim9 as tim12;
734///Advanced timer
735///
736///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#TIM8)
737pub type TIM8 = crate::Periph<tim8::RegisterBlock, 0x4001_3400>;
738impl core::fmt::Debug for TIM8 {
739    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
740        f.debug_struct("TIM8").finish()
741    }
742}
743///Advanced timer
744pub mod tim8;
745///Advanced timer
746///
747///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#TIM8)
748pub type TIM1 = crate::Periph<tim8::RegisterBlock, 0x4001_2c00>;
749impl core::fmt::Debug for TIM1 {
750    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
751        f.debug_struct("TIM1").finish()
752    }
753}
754///Advanced timer
755pub use self::tim8 as tim1;
756///Analog to digital converter
757///
758///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#ADC2)
759pub type ADC2 = crate::Periph<adc2::RegisterBlock, 0x4001_2800>;
760impl core::fmt::Debug for ADC2 {
761    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
762        f.debug_struct("ADC2").finish()
763    }
764}
765///Analog to digital converter
766pub mod adc2;
767///Digital to analog converter
768///
769///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#DAC)
770pub type DAC = crate::Periph<dac::RegisterBlock, 0x4000_7400>;
771impl core::fmt::Debug for DAC {
772    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
773        f.debug_struct("DAC").finish()
774    }
775}
776///Digital to analog converter
777pub mod dac;
778///Universal serial bus full-speed device interface
779///
780///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#USB)
781pub type USB = crate::Periph<usb::RegisterBlock, 0x4000_5c00>;
782impl core::fmt::Debug for USB {
783    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
784        f.debug_struct("USB").finish()
785    }
786}
787///Universal serial bus full-speed device interface
788pub mod usb;
789///Universal asynchronous receiver transmitter
790///
791///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#UART4)
792pub type UART4 = crate::Periph<uart4::RegisterBlock, 0x4000_4c00>;
793impl core::fmt::Debug for UART4 {
794    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
795        f.debug_struct("UART4").finish()
796    }
797}
798///Universal asynchronous receiver transmitter
799pub mod uart4;
800///Universal asynchronous receiver transmitter
801///
802///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#UART4)
803pub type UART5 = crate::Periph<uart4::RegisterBlock, 0x4000_5000>;
804impl core::fmt::Debug for UART5 {
805    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
806        f.debug_struct("UART5").finish()
807    }
808}
809///Universal asynchronous receiver transmitter
810pub use self::uart4 as uart5;
811///Serial peripheral interface
812///
813///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#SPI2)
814pub type SPI2 = crate::Periph<spi2::RegisterBlock, 0x4000_3800>;
815impl core::fmt::Debug for SPI2 {
816    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
817        f.debug_struct("SPI2").finish()
818    }
819}
820///Serial peripheral interface
821pub mod spi2;
822///Serial peripheral interface
823///
824///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#SPI2)
825pub type SPI3 = crate::Periph<spi2::RegisterBlock, 0x4000_3c00>;
826impl core::fmt::Debug for SPI3 {
827    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
828        f.debug_struct("SPI3").finish()
829    }
830}
831///Serial peripheral interface
832pub use self::spi2 as spi3;
833///General purpose timer
834///
835///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#TIM2)
836pub type TIM4 = crate::Periph<tim2::RegisterBlock, 0x4000_0800>;
837impl core::fmt::Debug for TIM4 {
838    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
839        f.debug_struct("TIM4").finish()
840    }
841}
842///General purpose timer
843pub use self::tim2 as tim4;
844///General purpose timer
845///
846///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#TIM2)
847pub type TIM5 = crate::Periph<tim2::RegisterBlock, 0x4000_0c00>;
848impl core::fmt::Debug for TIM5 {
849    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
850        f.debug_struct("TIM5").finish()
851    }
852}
853///General purpose timer
854pub use self::tim2 as tim5;
855///Basic timer
856///
857///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#TIM6)
858pub type TIM6 = crate::Periph<tim6::RegisterBlock, 0x4000_1000>;
859impl core::fmt::Debug for TIM6 {
860    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
861        f.debug_struct("TIM6").finish()
862    }
863}
864///Basic timer
865pub mod tim6;
866///Basic timer
867///
868///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#TIM6)
869pub type TIM7 = crate::Periph<tim6::RegisterBlock, 0x4000_1400>;
870impl core::fmt::Debug for TIM7 {
871    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
872        f.debug_struct("TIM7").finish()
873    }
874}
875///Basic timer
876pub use self::tim6 as tim7;
877///General purpose timer
878///
879///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#TIM13)
880pub type TIM14 = crate::Periph<tim13::RegisterBlock, 0x4000_2000>;
881impl core::fmt::Debug for TIM14 {
882    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
883        f.debug_struct("TIM14").finish()
884    }
885}
886///General purpose timer
887pub use self::tim13 as tim14;
888///System control block ACTLR
889///
890///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#SCB_ACTRL)
891pub type SCB_ACTRL = crate::Periph<scb_actrl::RegisterBlock, 0xe000_e008>;
892impl core::fmt::Debug for SCB_ACTRL {
893    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
894        f.debug_struct("SCB_ACTRL").finish()
895    }
896}
897///System control block ACTLR
898pub mod scb_actrl;
899///Nested vectored interrupt controller
900///
901///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#NVIC_STIR)
902pub type NVIC_STIR = crate::Periph<nvic_stir::RegisterBlock, 0xe000_ef00>;
903impl core::fmt::Debug for NVIC_STIR {
904    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
905        f.debug_struct("NVIC_STIR").finish()
906    }
907}
908///Nested vectored interrupt controller
909pub mod nvic_stir;
910///SysTick timer
911///
912///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#STK)
913pub type STK = crate::Periph<stk::RegisterBlock, 0xe000_e010>;
914impl core::fmt::Debug for STK {
915    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
916        f.debug_struct("STK").finish()
917    }
918}
919///SysTick timer
920pub mod stk;
921#[no_mangle]
922static mut DEVICE_PERIPHERALS: bool = false;
923/// All the peripherals.
924#[allow(non_snake_case)]
925pub struct Peripherals {
926    ///PWR
927    pub PWR: PWR,
928    ///RCC
929    pub RCC: RCC,
930    ///GPIOA
931    pub GPIOA: GPIOA,
932    ///GPIOB
933    pub GPIOB: GPIOB,
934    ///GPIOC
935    pub GPIOC: GPIOC,
936    ///GPIOD
937    pub GPIOD: GPIOD,
938    ///GPIOE
939    pub GPIOE: GPIOE,
940    ///GPIOF
941    pub GPIOF: GPIOF,
942    ///GPIOG
943    pub GPIOG: GPIOG,
944    ///AFIO
945    pub AFIO: AFIO,
946    ///EXTI
947    pub EXTI: EXTI,
948    ///DMA1
949    pub DMA1: DMA1,
950    ///DMA2
951    pub DMA2: DMA2,
952    ///RTC
953    pub RTC: RTC,
954    ///IWDG
955    pub IWDG: IWDG,
956    ///WWDG
957    pub WWDG: WWDG,
958    ///TIM2
959    pub TIM2: TIM2,
960    ///TIM3
961    pub TIM3: TIM3,
962    ///I2C1
963    pub I2C1: I2C1,
964    ///I2C2
965    pub I2C2: I2C2,
966    ///SPI1
967    pub SPI1: SPI1,
968    ///USART1
969    pub USART1: USART1,
970    ///USART2
971    pub USART2: USART2,
972    ///USART3
973    pub USART3: USART3,
974    ///ADC1
975    pub ADC1: ADC1,
976    ///ADC3
977    pub ADC3: ADC3,
978    ///CRC
979    pub CRC: CRC,
980    ///FLASH
981    pub FLASH: FLASH,
982    ///DBGMCU
983    pub DBGMCU: DBGMCU,
984    ///BKP
985    pub BKP: BKP,
986    ///FSMC
987    pub FSMC: FSMC,
988    ///OTG_FS_DEVICE
989    pub OTG_FS_DEVICE: OTG_FS_DEVICE,
990    ///OTG_FS_GLOBAL
991    pub OTG_FS_GLOBAL: OTG_FS_GLOBAL,
992    ///OTG_FS_HOST
993    pub OTG_FS_HOST: OTG_FS_HOST,
994    ///OTG_FS_PWRCLK
995    pub OTG_FS_PWRCLK: OTG_FS_PWRCLK,
996    ///SDIO
997    pub SDIO: SDIO,
998    ///TIM13
999    pub TIM13: TIM13,
1000    ///TIM10
1001    pub TIM10: TIM10,
1002    ///TIM11
1003    pub TIM11: TIM11,
1004    ///TIM9
1005    pub TIM9: TIM9,
1006    ///TIM12
1007    pub TIM12: TIM12,
1008    ///TIM8
1009    pub TIM8: TIM8,
1010    ///TIM1
1011    pub TIM1: TIM1,
1012    ///ADC2
1013    pub ADC2: ADC2,
1014    ///DAC
1015    pub DAC: DAC,
1016    ///USB
1017    pub USB: USB,
1018    ///UART4
1019    pub UART4: UART4,
1020    ///UART5
1021    pub UART5: UART5,
1022    ///SPI2
1023    pub SPI2: SPI2,
1024    ///SPI3
1025    pub SPI3: SPI3,
1026    ///TIM4
1027    pub TIM4: TIM4,
1028    ///TIM5
1029    pub TIM5: TIM5,
1030    ///TIM6
1031    pub TIM6: TIM6,
1032    ///TIM7
1033    pub TIM7: TIM7,
1034    ///TIM14
1035    pub TIM14: TIM14,
1036    ///SCB_ACTRL
1037    pub SCB_ACTRL: SCB_ACTRL,
1038    ///NVIC_STIR
1039    pub NVIC_STIR: NVIC_STIR,
1040    ///STK
1041    pub STK: STK,
1042}
1043impl Peripherals {
1044    /// Returns all the peripherals *once*.
1045    #[cfg(feature = "critical-section")]
1046    #[inline]
1047    pub fn take() -> Option<Self> {
1048        critical_section::with(|_| {
1049            if unsafe { DEVICE_PERIPHERALS } {
1050                return None;
1051            }
1052            Some(unsafe { Peripherals::steal() })
1053        })
1054    }
1055    /// Unchecked version of `Peripherals::take`.
1056    ///
1057    /// # Safety
1058    ///
1059    /// Each of the returned peripherals must be used at most once.
1060    #[inline]
1061    pub unsafe fn steal() -> Self {
1062        DEVICE_PERIPHERALS = true;
1063        Peripherals {
1064            PWR: PWR::steal(),
1065            RCC: RCC::steal(),
1066            GPIOA: GPIOA::steal(),
1067            GPIOB: GPIOB::steal(),
1068            GPIOC: GPIOC::steal(),
1069            GPIOD: GPIOD::steal(),
1070            GPIOE: GPIOE::steal(),
1071            GPIOF: GPIOF::steal(),
1072            GPIOG: GPIOG::steal(),
1073            AFIO: AFIO::steal(),
1074            EXTI: EXTI::steal(),
1075            DMA1: DMA1::steal(),
1076            DMA2: DMA2::steal(),
1077            RTC: RTC::steal(),
1078            IWDG: IWDG::steal(),
1079            WWDG: WWDG::steal(),
1080            TIM2: TIM2::steal(),
1081            TIM3: TIM3::steal(),
1082            I2C1: I2C1::steal(),
1083            I2C2: I2C2::steal(),
1084            SPI1: SPI1::steal(),
1085            USART1: USART1::steal(),
1086            USART2: USART2::steal(),
1087            USART3: USART3::steal(),
1088            ADC1: ADC1::steal(),
1089            ADC3: ADC3::steal(),
1090            CRC: CRC::steal(),
1091            FLASH: FLASH::steal(),
1092            DBGMCU: DBGMCU::steal(),
1093            BKP: BKP::steal(),
1094            FSMC: FSMC::steal(),
1095            OTG_FS_DEVICE: OTG_FS_DEVICE::steal(),
1096            OTG_FS_GLOBAL: OTG_FS_GLOBAL::steal(),
1097            OTG_FS_HOST: OTG_FS_HOST::steal(),
1098            OTG_FS_PWRCLK: OTG_FS_PWRCLK::steal(),
1099            SDIO: SDIO::steal(),
1100            TIM13: TIM13::steal(),
1101            TIM10: TIM10::steal(),
1102            TIM11: TIM11::steal(),
1103            TIM9: TIM9::steal(),
1104            TIM12: TIM12::steal(),
1105            TIM8: TIM8::steal(),
1106            TIM1: TIM1::steal(),
1107            ADC2: ADC2::steal(),
1108            DAC: DAC::steal(),
1109            USB: USB::steal(),
1110            UART4: UART4::steal(),
1111            UART5: UART5::steal(),
1112            SPI2: SPI2::steal(),
1113            SPI3: SPI3::steal(),
1114            TIM4: TIM4::steal(),
1115            TIM5: TIM5::steal(),
1116            TIM6: TIM6::steal(),
1117            TIM7: TIM7::steal(),
1118            TIM14: TIM14::steal(),
1119            SCB_ACTRL: SCB_ACTRL::steal(),
1120            NVIC_STIR: NVIC_STIR::steal(),
1121            STK: STK::steal(),
1122        }
1123    }
1124}
stm32f1_staging/stm32f102/mod.rs

stm32f1_staging/stm32f102/
mod.rs
