stm32f1_staging/stm32f102/
gpioa.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    crl: CRL,
6    crh: CRH,
7    idr: IDR,
8    odr: ODR,
9    bsrr: BSRR,
10    brr: BRR,
11    lckr: LCKR,
12}
13impl RegisterBlock {
14    ///0x00 - Port configuration register low (GPIOn_CRL)
15    #[inline(always)]
16    pub const fn crl(&self) -> &CRL {
17        &self.crl
18    }
19    ///0x04 - Port configuration register high (GPIOn_CRL)
20    #[inline(always)]
21    pub const fn crh(&self) -> &CRH {
22        &self.crh
23    }
24    ///0x08 - Port input data register (GPIOn_IDR)
25    #[inline(always)]
26    pub const fn idr(&self) -> &IDR {
27        &self.idr
28    }
29    ///0x0c - Port output data register (GPIOn_ODR)
30    #[inline(always)]
31    pub const fn odr(&self) -> &ODR {
32        &self.odr
33    }
34    ///0x10 - Port bit set/reset register (GPIOn_BSRR)
35    #[inline(always)]
36    pub const fn bsrr(&self) -> &BSRR {
37        &self.bsrr
38    }
39    ///0x14 - Port bit reset register (GPIOn_BRR)
40    #[inline(always)]
41    pub const fn brr(&self) -> &BRR {
42        &self.brr
43    }
44    ///0x18 - Port configuration lock register
45    #[inline(always)]
46    pub const fn lckr(&self) -> &LCKR {
47        &self.lckr
48    }
49}
50/**CRL (rw) register accessor: Port configuration register low (GPIOn_CRL)
51
52You can [`read`](crate::Reg::read) this register and get [`crl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
53
54See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#GPIOA:CRL)
55
56For information about available fields see [`mod@crl`] module*/
57pub type CRL = crate::Reg<crl::CRLrs>;
58///Port configuration register low (GPIOn_CRL)
59pub mod crl;
60/**CRH (rw) register accessor: Port configuration register high (GPIOn_CRL)
61
62You can [`read`](crate::Reg::read) this register and get [`crh::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`crh::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
63
64See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#GPIOA:CRH)
65
66For information about available fields see [`mod@crh`] module*/
67pub type CRH = crate::Reg<crh::CRHrs>;
68///Port configuration register high (GPIOn_CRL)
69pub mod crh;
70/**IDR (r) register accessor: Port input data register (GPIOn_IDR)
71
72You can [`read`](crate::Reg::read) this register and get [`idr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
73
74See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#GPIOA:IDR)
75
76For information about available fields see [`mod@idr`] module*/
77pub type IDR = crate::Reg<idr::IDRrs>;
78///Port input data register (GPIOn_IDR)
79pub mod idr;
80/**ODR (rw) register accessor: Port output data register (GPIOn_ODR)
81
82You can [`read`](crate::Reg::read) this register and get [`odr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`odr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
83
84See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#GPIOA:ODR)
85
86For information about available fields see [`mod@odr`] module*/
87pub type ODR = crate::Reg<odr::ODRrs>;
88///Port output data register (GPIOn_ODR)
89pub mod odr;
90/**BSRR (w) register accessor: Port bit set/reset register (GPIOn_BSRR)
91
92You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bsrr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
93
94See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#GPIOA:BSRR)
95
96For information about available fields see [`mod@bsrr`] module*/
97pub type BSRR = crate::Reg<bsrr::BSRRrs>;
98///Port bit set/reset register (GPIOn_BSRR)
99pub mod bsrr;
100/**BRR (w) register accessor: Port bit reset register (GPIOn_BRR)
101
102You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`brr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
103
104See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#GPIOA:BRR)
105
106For information about available fields see [`mod@brr`] module*/
107pub type BRR = crate::Reg<brr::BRRrs>;
108///Port bit reset register (GPIOn_BRR)
109pub mod brr;
110/**LCKR (rw) register accessor: Port configuration lock register
111
112You can [`read`](crate::Reg::read) this register and get [`lckr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lckr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
113
114See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F102.html#GPIOA:LCKR)
115
116For information about available fields see [`mod@lckr`] module*/
117pub type LCKR = crate::Reg<lckr::LCKRrs>;
118///Port configuration lock register
119pub mod lckr;
stm32f1_staging/stm32f102/gpioa.rs

stm32f1_staging/stm32f102/
gpioa.rs
