stm32f1_staging/stm32f101/usart1/
cr3.rs

1///Register `CR3` reader
2pub type R = crate::R<CR3rs>;
3///Register `CR3` writer
4pub type W = crate::W<CR3rs>;
5/**Error interrupt enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum EIE {
11    ///0: Error interrupt disabled
12    Disabled = 0,
13    ///1: Error interrupt enabled
14    Enabled = 1,
15}
16impl From<EIE> for bool {
17    #[inline(always)]
18    fn from(variant: EIE) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `EIE` reader - Error interrupt enable
23pub type EIE_R = crate::BitReader<EIE>;
24impl EIE_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> EIE {
28        match self.bits {
29            false => EIE::Disabled,
30            true => EIE::Enabled,
31        }
32    }
33    ///Error interrupt disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == EIE::Disabled
37    }
38    ///Error interrupt enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == EIE::Enabled
42    }
43}
44///Field `EIE` writer - Error interrupt enable
45pub type EIE_W<'a, REG> = crate::BitWriter<'a, REG, EIE>;
46impl<'a, REG> EIE_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Error interrupt disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(EIE::Disabled)
54    }
55    ///Error interrupt enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(EIE::Enabled)
59    }
60}
61/**IrDA mode enable
62
63Value on reset: 0*/
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum IREN {
67    ///0: IrDA disabled
68    Disabled = 0,
69    ///1: IrDA enabled
70    Enabled = 1,
71}
72impl From<IREN> for bool {
73    #[inline(always)]
74    fn from(variant: IREN) -> Self {
75        variant as u8 != 0
76    }
77}
78///Field `IREN` reader - IrDA mode enable
79pub type IREN_R = crate::BitReader<IREN>;
80impl IREN_R {
81    ///Get enumerated values variant
82    #[inline(always)]
83    pub const fn variant(&self) -> IREN {
84        match self.bits {
85            false => IREN::Disabled,
86            true => IREN::Enabled,
87        }
88    }
89    ///IrDA disabled
90    #[inline(always)]
91    pub fn is_disabled(&self) -> bool {
92        *self == IREN::Disabled
93    }
94    ///IrDA enabled
95    #[inline(always)]
96    pub fn is_enabled(&self) -> bool {
97        *self == IREN::Enabled
98    }
99}
100///Field `IREN` writer - IrDA mode enable
101pub type IREN_W<'a, REG> = crate::BitWriter<'a, REG, IREN>;
102impl<'a, REG> IREN_W<'a, REG>
103where
104    REG: crate::Writable + crate::RegisterSpec,
105{
106    ///IrDA disabled
107    #[inline(always)]
108    pub fn disabled(self) -> &'a mut crate::W<REG> {
109        self.variant(IREN::Disabled)
110    }
111    ///IrDA enabled
112    #[inline(always)]
113    pub fn enabled(self) -> &'a mut crate::W<REG> {
114        self.variant(IREN::Enabled)
115    }
116}
117/**IrDA low-power
118
119Value on reset: 0*/
120#[cfg_attr(feature = "defmt", derive(defmt::Format))]
121#[derive(Clone, Copy, Debug, PartialEq, Eq)]
122pub enum IRLP {
123    ///0: Normal mode
124    Normal = 0,
125    ///1: Low-power mode
126    LowPower = 1,
127}
128impl From<IRLP> for bool {
129    #[inline(always)]
130    fn from(variant: IRLP) -> Self {
131        variant as u8 != 0
132    }
133}
134///Field `IRLP` reader - IrDA low-power
135pub type IRLP_R = crate::BitReader<IRLP>;
136impl IRLP_R {
137    ///Get enumerated values variant
138    #[inline(always)]
139    pub const fn variant(&self) -> IRLP {
140        match self.bits {
141            false => IRLP::Normal,
142            true => IRLP::LowPower,
143        }
144    }
145    ///Normal mode
146    #[inline(always)]
147    pub fn is_normal(&self) -> bool {
148        *self == IRLP::Normal
149    }
150    ///Low-power mode
151    #[inline(always)]
152    pub fn is_low_power(&self) -> bool {
153        *self == IRLP::LowPower
154    }
155}
156///Field `IRLP` writer - IrDA low-power
157pub type IRLP_W<'a, REG> = crate::BitWriter<'a, REG, IRLP>;
158impl<'a, REG> IRLP_W<'a, REG>
159where
160    REG: crate::Writable + crate::RegisterSpec,
161{
162    ///Normal mode
163    #[inline(always)]
164    pub fn normal(self) -> &'a mut crate::W<REG> {
165        self.variant(IRLP::Normal)
166    }
167    ///Low-power mode
168    #[inline(always)]
169    pub fn low_power(self) -> &'a mut crate::W<REG> {
170        self.variant(IRLP::LowPower)
171    }
172}
173/**Half-duplex selection
174
175Value on reset: 0*/
176#[cfg_attr(feature = "defmt", derive(defmt::Format))]
177#[derive(Clone, Copy, Debug, PartialEq, Eq)]
178pub enum HDSEL {
179    ///0: Half duplex mode is not selected
180    FullDuplex = 0,
181    ///1: Half duplex mode is selected
182    HalfDuplex = 1,
183}
184impl From<HDSEL> for bool {
185    #[inline(always)]
186    fn from(variant: HDSEL) -> Self {
187        variant as u8 != 0
188    }
189}
190///Field `HDSEL` reader - Half-duplex selection
191pub type HDSEL_R = crate::BitReader<HDSEL>;
192impl HDSEL_R {
193    ///Get enumerated values variant
194    #[inline(always)]
195    pub const fn variant(&self) -> HDSEL {
196        match self.bits {
197            false => HDSEL::FullDuplex,
198            true => HDSEL::HalfDuplex,
199        }
200    }
201    ///Half duplex mode is not selected
202    #[inline(always)]
203    pub fn is_full_duplex(&self) -> bool {
204        *self == HDSEL::FullDuplex
205    }
206    ///Half duplex mode is selected
207    #[inline(always)]
208    pub fn is_half_duplex(&self) -> bool {
209        *self == HDSEL::HalfDuplex
210    }
211}
212///Field `HDSEL` writer - Half-duplex selection
213pub type HDSEL_W<'a, REG> = crate::BitWriter<'a, REG, HDSEL>;
214impl<'a, REG> HDSEL_W<'a, REG>
215where
216    REG: crate::Writable + crate::RegisterSpec,
217{
218    ///Half duplex mode is not selected
219    #[inline(always)]
220    pub fn full_duplex(self) -> &'a mut crate::W<REG> {
221        self.variant(HDSEL::FullDuplex)
222    }
223    ///Half duplex mode is selected
224    #[inline(always)]
225    pub fn half_duplex(self) -> &'a mut crate::W<REG> {
226        self.variant(HDSEL::HalfDuplex)
227    }
228}
229/**Smartcard NACK enable
230
231Value on reset: 0*/
232#[cfg_attr(feature = "defmt", derive(defmt::Format))]
233#[derive(Clone, Copy, Debug, PartialEq, Eq)]
234pub enum NACK {
235    ///0: NACK transmission in case of parity error is disabled
236    Disabled = 0,
237    ///1: NACK transmission during parity error is enabled
238    Enabled = 1,
239}
240impl From<NACK> for bool {
241    #[inline(always)]
242    fn from(variant: NACK) -> Self {
243        variant as u8 != 0
244    }
245}
246///Field `NACK` reader - Smartcard NACK enable
247pub type NACK_R = crate::BitReader<NACK>;
248impl NACK_R {
249    ///Get enumerated values variant
250    #[inline(always)]
251    pub const fn variant(&self) -> NACK {
252        match self.bits {
253            false => NACK::Disabled,
254            true => NACK::Enabled,
255        }
256    }
257    ///NACK transmission in case of parity error is disabled
258    #[inline(always)]
259    pub fn is_disabled(&self) -> bool {
260        *self == NACK::Disabled
261    }
262    ///NACK transmission during parity error is enabled
263    #[inline(always)]
264    pub fn is_enabled(&self) -> bool {
265        *self == NACK::Enabled
266    }
267}
268///Field `NACK` writer - Smartcard NACK enable
269pub type NACK_W<'a, REG> = crate::BitWriter<'a, REG, NACK>;
270impl<'a, REG> NACK_W<'a, REG>
271where
272    REG: crate::Writable + crate::RegisterSpec,
273{
274    ///NACK transmission in case of parity error is disabled
275    #[inline(always)]
276    pub fn disabled(self) -> &'a mut crate::W<REG> {
277        self.variant(NACK::Disabled)
278    }
279    ///NACK transmission during parity error is enabled
280    #[inline(always)]
281    pub fn enabled(self) -> &'a mut crate::W<REG> {
282        self.variant(NACK::Enabled)
283    }
284}
285/**Smartcard mode enable
286
287Value on reset: 0*/
288#[cfg_attr(feature = "defmt", derive(defmt::Format))]
289#[derive(Clone, Copy, Debug, PartialEq, Eq)]
290pub enum SCEN {
291    ///0: Smartcard mode disabled
292    Disabled = 0,
293    ///1: Smartcard mode enabled
294    Enabled = 1,
295}
296impl From<SCEN> for bool {
297    #[inline(always)]
298    fn from(variant: SCEN) -> Self {
299        variant as u8 != 0
300    }
301}
302///Field `SCEN` reader - Smartcard mode enable
303pub type SCEN_R = crate::BitReader<SCEN>;
304impl SCEN_R {
305    ///Get enumerated values variant
306    #[inline(always)]
307    pub const fn variant(&self) -> SCEN {
308        match self.bits {
309            false => SCEN::Disabled,
310            true => SCEN::Enabled,
311        }
312    }
313    ///Smartcard mode disabled
314    #[inline(always)]
315    pub fn is_disabled(&self) -> bool {
316        *self == SCEN::Disabled
317    }
318    ///Smartcard mode enabled
319    #[inline(always)]
320    pub fn is_enabled(&self) -> bool {
321        *self == SCEN::Enabled
322    }
323}
324///Field `SCEN` writer - Smartcard mode enable
325pub type SCEN_W<'a, REG> = crate::BitWriter<'a, REG, SCEN>;
326impl<'a, REG> SCEN_W<'a, REG>
327where
328    REG: crate::Writable + crate::RegisterSpec,
329{
330    ///Smartcard mode disabled
331    #[inline(always)]
332    pub fn disabled(self) -> &'a mut crate::W<REG> {
333        self.variant(SCEN::Disabled)
334    }
335    ///Smartcard mode enabled
336    #[inline(always)]
337    pub fn enabled(self) -> &'a mut crate::W<REG> {
338        self.variant(SCEN::Enabled)
339    }
340}
341/**DMA enable receiver
342
343Value on reset: 0*/
344#[cfg_attr(feature = "defmt", derive(defmt::Format))]
345#[derive(Clone, Copy, Debug, PartialEq, Eq)]
346pub enum DMAR {
347    ///0: DMA mode is disabled for reception
348    Disabled = 0,
349    ///1: DMA mode is enabled for reception
350    Enabled = 1,
351}
352impl From<DMAR> for bool {
353    #[inline(always)]
354    fn from(variant: DMAR) -> Self {
355        variant as u8 != 0
356    }
357}
358///Field `DMAR` reader - DMA enable receiver
359pub type DMAR_R = crate::BitReader<DMAR>;
360impl DMAR_R {
361    ///Get enumerated values variant
362    #[inline(always)]
363    pub const fn variant(&self) -> DMAR {
364        match self.bits {
365            false => DMAR::Disabled,
366            true => DMAR::Enabled,
367        }
368    }
369    ///DMA mode is disabled for reception
370    #[inline(always)]
371    pub fn is_disabled(&self) -> bool {
372        *self == DMAR::Disabled
373    }
374    ///DMA mode is enabled for reception
375    #[inline(always)]
376    pub fn is_enabled(&self) -> bool {
377        *self == DMAR::Enabled
378    }
379}
380///Field `DMAR` writer - DMA enable receiver
381pub type DMAR_W<'a, REG> = crate::BitWriter<'a, REG, DMAR>;
382impl<'a, REG> DMAR_W<'a, REG>
383where
384    REG: crate::Writable + crate::RegisterSpec,
385{
386    ///DMA mode is disabled for reception
387    #[inline(always)]
388    pub fn disabled(self) -> &'a mut crate::W<REG> {
389        self.variant(DMAR::Disabled)
390    }
391    ///DMA mode is enabled for reception
392    #[inline(always)]
393    pub fn enabled(self) -> &'a mut crate::W<REG> {
394        self.variant(DMAR::Enabled)
395    }
396}
397/**DMA enable transmitter
398
399Value on reset: 0*/
400#[cfg_attr(feature = "defmt", derive(defmt::Format))]
401#[derive(Clone, Copy, Debug, PartialEq, Eq)]
402pub enum DMAT {
403    ///0: DMA mode is disabled for transmission
404    Disabled = 0,
405    ///1: DMA mode is enabled for transmission
406    Enabled = 1,
407}
408impl From<DMAT> for bool {
409    #[inline(always)]
410    fn from(variant: DMAT) -> Self {
411        variant as u8 != 0
412    }
413}
414///Field `DMAT` reader - DMA enable transmitter
415pub type DMAT_R = crate::BitReader<DMAT>;
416impl DMAT_R {
417    ///Get enumerated values variant
418    #[inline(always)]
419    pub const fn variant(&self) -> DMAT {
420        match self.bits {
421            false => DMAT::Disabled,
422            true => DMAT::Enabled,
423        }
424    }
425    ///DMA mode is disabled for transmission
426    #[inline(always)]
427    pub fn is_disabled(&self) -> bool {
428        *self == DMAT::Disabled
429    }
430    ///DMA mode is enabled for transmission
431    #[inline(always)]
432    pub fn is_enabled(&self) -> bool {
433        *self == DMAT::Enabled
434    }
435}
436///Field `DMAT` writer - DMA enable transmitter
437pub type DMAT_W<'a, REG> = crate::BitWriter<'a, REG, DMAT>;
438impl<'a, REG> DMAT_W<'a, REG>
439where
440    REG: crate::Writable + crate::RegisterSpec,
441{
442    ///DMA mode is disabled for transmission
443    #[inline(always)]
444    pub fn disabled(self) -> &'a mut crate::W<REG> {
445        self.variant(DMAT::Disabled)
446    }
447    ///DMA mode is enabled for transmission
448    #[inline(always)]
449    pub fn enabled(self) -> &'a mut crate::W<REG> {
450        self.variant(DMAT::Enabled)
451    }
452}
453/**RTS enable
454
455Value on reset: 0*/
456#[cfg_attr(feature = "defmt", derive(defmt::Format))]
457#[derive(Clone, Copy, Debug, PartialEq, Eq)]
458pub enum RTSE {
459    ///0: RTS hardware flow control disabled
460    Disabled = 0,
461    ///1: RTS hardware flow control enabled
462    Enabled = 1,
463}
464impl From<RTSE> for bool {
465    #[inline(always)]
466    fn from(variant: RTSE) -> Self {
467        variant as u8 != 0
468    }
469}
470///Field `RTSE` reader - RTS enable
471pub type RTSE_R = crate::BitReader<RTSE>;
472impl RTSE_R {
473    ///Get enumerated values variant
474    #[inline(always)]
475    pub const fn variant(&self) -> RTSE {
476        match self.bits {
477            false => RTSE::Disabled,
478            true => RTSE::Enabled,
479        }
480    }
481    ///RTS hardware flow control disabled
482    #[inline(always)]
483    pub fn is_disabled(&self) -> bool {
484        *self == RTSE::Disabled
485    }
486    ///RTS hardware flow control enabled
487    #[inline(always)]
488    pub fn is_enabled(&self) -> bool {
489        *self == RTSE::Enabled
490    }
491}
492///Field `RTSE` writer - RTS enable
493pub type RTSE_W<'a, REG> = crate::BitWriter<'a, REG, RTSE>;
494impl<'a, REG> RTSE_W<'a, REG>
495where
496    REG: crate::Writable + crate::RegisterSpec,
497{
498    ///RTS hardware flow control disabled
499    #[inline(always)]
500    pub fn disabled(self) -> &'a mut crate::W<REG> {
501        self.variant(RTSE::Disabled)
502    }
503    ///RTS hardware flow control enabled
504    #[inline(always)]
505    pub fn enabled(self) -> &'a mut crate::W<REG> {
506        self.variant(RTSE::Enabled)
507    }
508}
509/**CTS enable
510
511Value on reset: 0*/
512#[cfg_attr(feature = "defmt", derive(defmt::Format))]
513#[derive(Clone, Copy, Debug, PartialEq, Eq)]
514pub enum CTSE {
515    ///0: CTS hardware flow control disabled
516    Disabled = 0,
517    ///1: CTS hardware flow control enabled
518    Enabled = 1,
519}
520impl From<CTSE> for bool {
521    #[inline(always)]
522    fn from(variant: CTSE) -> Self {
523        variant as u8 != 0
524    }
525}
526///Field `CTSE` reader - CTS enable
527pub type CTSE_R = crate::BitReader<CTSE>;
528impl CTSE_R {
529    ///Get enumerated values variant
530    #[inline(always)]
531    pub const fn variant(&self) -> CTSE {
532        match self.bits {
533            false => CTSE::Disabled,
534            true => CTSE::Enabled,
535        }
536    }
537    ///CTS hardware flow control disabled
538    #[inline(always)]
539    pub fn is_disabled(&self) -> bool {
540        *self == CTSE::Disabled
541    }
542    ///CTS hardware flow control enabled
543    #[inline(always)]
544    pub fn is_enabled(&self) -> bool {
545        *self == CTSE::Enabled
546    }
547}
548///Field `CTSE` writer - CTS enable
549pub type CTSE_W<'a, REG> = crate::BitWriter<'a, REG, CTSE>;
550impl<'a, REG> CTSE_W<'a, REG>
551where
552    REG: crate::Writable + crate::RegisterSpec,
553{
554    ///CTS hardware flow control disabled
555    #[inline(always)]
556    pub fn disabled(self) -> &'a mut crate::W<REG> {
557        self.variant(CTSE::Disabled)
558    }
559    ///CTS hardware flow control enabled
560    #[inline(always)]
561    pub fn enabled(self) -> &'a mut crate::W<REG> {
562        self.variant(CTSE::Enabled)
563    }
564}
565/**CTS interrupt enable
566
567Value on reset: 0*/
568#[cfg_attr(feature = "defmt", derive(defmt::Format))]
569#[derive(Clone, Copy, Debug, PartialEq, Eq)]
570pub enum CTSIE {
571    ///0: CTS interrupt disabled
572    Disabled = 0,
573    ///1: CTS interrupt enabled
574    Enabled = 1,
575}
576impl From<CTSIE> for bool {
577    #[inline(always)]
578    fn from(variant: CTSIE) -> Self {
579        variant as u8 != 0
580    }
581}
582///Field `CTSIE` reader - CTS interrupt enable
583pub type CTSIE_R = crate::BitReader<CTSIE>;
584impl CTSIE_R {
585    ///Get enumerated values variant
586    #[inline(always)]
587    pub const fn variant(&self) -> CTSIE {
588        match self.bits {
589            false => CTSIE::Disabled,
590            true => CTSIE::Enabled,
591        }
592    }
593    ///CTS interrupt disabled
594    #[inline(always)]
595    pub fn is_disabled(&self) -> bool {
596        *self == CTSIE::Disabled
597    }
598    ///CTS interrupt enabled
599    #[inline(always)]
600    pub fn is_enabled(&self) -> bool {
601        *self == CTSIE::Enabled
602    }
603}
604///Field `CTSIE` writer - CTS interrupt enable
605pub type CTSIE_W<'a, REG> = crate::BitWriter<'a, REG, CTSIE>;
606impl<'a, REG> CTSIE_W<'a, REG>
607where
608    REG: crate::Writable + crate::RegisterSpec,
609{
610    ///CTS interrupt disabled
611    #[inline(always)]
612    pub fn disabled(self) -> &'a mut crate::W<REG> {
613        self.variant(CTSIE::Disabled)
614    }
615    ///CTS interrupt enabled
616    #[inline(always)]
617    pub fn enabled(self) -> &'a mut crate::W<REG> {
618        self.variant(CTSIE::Enabled)
619    }
620}
621impl R {
622    ///Bit 0 - Error interrupt enable
623    #[inline(always)]
624    pub fn eie(&self) -> EIE_R {
625        EIE_R::new((self.bits & 1) != 0)
626    }
627    ///Bit 1 - IrDA mode enable
628    #[inline(always)]
629    pub fn iren(&self) -> IREN_R {
630        IREN_R::new(((self.bits >> 1) & 1) != 0)
631    }
632    ///Bit 2 - IrDA low-power
633    #[inline(always)]
634    pub fn irlp(&self) -> IRLP_R {
635        IRLP_R::new(((self.bits >> 2) & 1) != 0)
636    }
637    ///Bit 3 - Half-duplex selection
638    #[inline(always)]
639    pub fn hdsel(&self) -> HDSEL_R {
640        HDSEL_R::new(((self.bits >> 3) & 1) != 0)
641    }
642    ///Bit 4 - Smartcard NACK enable
643    #[inline(always)]
644    pub fn nack(&self) -> NACK_R {
645        NACK_R::new(((self.bits >> 4) & 1) != 0)
646    }
647    ///Bit 5 - Smartcard mode enable
648    #[inline(always)]
649    pub fn scen(&self) -> SCEN_R {
650        SCEN_R::new(((self.bits >> 5) & 1) != 0)
651    }
652    ///Bit 6 - DMA enable receiver
653    #[inline(always)]
654    pub fn dmar(&self) -> DMAR_R {
655        DMAR_R::new(((self.bits >> 6) & 1) != 0)
656    }
657    ///Bit 7 - DMA enable transmitter
658    #[inline(always)]
659    pub fn dmat(&self) -> DMAT_R {
660        DMAT_R::new(((self.bits >> 7) & 1) != 0)
661    }
662    ///Bit 8 - RTS enable
663    #[inline(always)]
664    pub fn rtse(&self) -> RTSE_R {
665        RTSE_R::new(((self.bits >> 8) & 1) != 0)
666    }
667    ///Bit 9 - CTS enable
668    #[inline(always)]
669    pub fn ctse(&self) -> CTSE_R {
670        CTSE_R::new(((self.bits >> 9) & 1) != 0)
671    }
672    ///Bit 10 - CTS interrupt enable
673    #[inline(always)]
674    pub fn ctsie(&self) -> CTSIE_R {
675        CTSIE_R::new(((self.bits >> 10) & 1) != 0)
676    }
677}
678impl core::fmt::Debug for R {
679    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
680        f.debug_struct("CR3")
681            .field("ctsie", &self.ctsie())
682            .field("ctse", &self.ctse())
683            .field("rtse", &self.rtse())
684            .field("dmat", &self.dmat())
685            .field("dmar", &self.dmar())
686            .field("scen", &self.scen())
687            .field("nack", &self.nack())
688            .field("hdsel", &self.hdsel())
689            .field("irlp", &self.irlp())
690            .field("iren", &self.iren())
691            .field("eie", &self.eie())
692            .finish()
693    }
694}
695impl W {
696    ///Bit 0 - Error interrupt enable
697    #[inline(always)]
698    pub fn eie(&mut self) -> EIE_W<CR3rs> {
699        EIE_W::new(self, 0)
700    }
701    ///Bit 1 - IrDA mode enable
702    #[inline(always)]
703    pub fn iren(&mut self) -> IREN_W<CR3rs> {
704        IREN_W::new(self, 1)
705    }
706    ///Bit 2 - IrDA low-power
707    #[inline(always)]
708    pub fn irlp(&mut self) -> IRLP_W<CR3rs> {
709        IRLP_W::new(self, 2)
710    }
711    ///Bit 3 - Half-duplex selection
712    #[inline(always)]
713    pub fn hdsel(&mut self) -> HDSEL_W<CR3rs> {
714        HDSEL_W::new(self, 3)
715    }
716    ///Bit 4 - Smartcard NACK enable
717    #[inline(always)]
718    pub fn nack(&mut self) -> NACK_W<CR3rs> {
719        NACK_W::new(self, 4)
720    }
721    ///Bit 5 - Smartcard mode enable
722    #[inline(always)]
723    pub fn scen(&mut self) -> SCEN_W<CR3rs> {
724        SCEN_W::new(self, 5)
725    }
726    ///Bit 6 - DMA enable receiver
727    #[inline(always)]
728    pub fn dmar(&mut self) -> DMAR_W<CR3rs> {
729        DMAR_W::new(self, 6)
730    }
731    ///Bit 7 - DMA enable transmitter
732    #[inline(always)]
733    pub fn dmat(&mut self) -> DMAT_W<CR3rs> {
734        DMAT_W::new(self, 7)
735    }
736    ///Bit 8 - RTS enable
737    #[inline(always)]
738    pub fn rtse(&mut self) -> RTSE_W<CR3rs> {
739        RTSE_W::new(self, 8)
740    }
741    ///Bit 9 - CTS enable
742    #[inline(always)]
743    pub fn ctse(&mut self) -> CTSE_W<CR3rs> {
744        CTSE_W::new(self, 9)
745    }
746    ///Bit 10 - CTS interrupt enable
747    #[inline(always)]
748    pub fn ctsie(&mut self) -> CTSIE_W<CR3rs> {
749        CTSIE_W::new(self, 10)
750    }
751}
752/**Control register 3
753
754You can [`read`](crate::Reg::read) this register and get [`cr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
755
756See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#USART1:CR3)*/
757pub struct CR3rs;
758impl crate::RegisterSpec for CR3rs {
759    type Ux = u16;
760}
761///`read()` method returns [`cr3::R`](R) reader structure
762impl crate::Readable for CR3rs {}
763///`write(|w| ..)` method takes [`cr3::W`](W) writer structure
764impl crate::Writable for CR3rs {
765    type Safety = crate::Unsafe;
766}
767///`reset()` method sets CR3 to value 0
768impl crate::Resettable for CR3rs {}
stm32f1_staging/stm32f101/usart1/cr3.rs

stm32f1_staging/stm32f101/usart1/
cr3.rs
