stm32f1_staging/stm32f101/
tim10.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr1: CR1,
6    cr2: CR2,
7    _reserved2: [u8; 0x04],
8    dier: DIER,
9    sr: SR,
10    egr: EGR,
11    _reserved_5_ccmr1: [u8; 0x04],
12    _reserved6: [u8; 0x04],
13    ccer: CCER,
14    cnt: CNT,
15    psc: PSC,
16    arr: ARR,
17    _reserved10: [u8; 0x04],
18    ccr: [CCR; 1],
19}
20impl RegisterBlock {
21    ///0x00 - control register 1
22    #[inline(always)]
23    pub const fn cr1(&self) -> &CR1 {
24        &self.cr1
25    }
26    ///0x04 - control register 2
27    #[inline(always)]
28    pub const fn cr2(&self) -> &CR2 {
29        &self.cr2
30    }
31    ///0x0c - DMA/Interrupt enable register
32    #[inline(always)]
33    pub const fn dier(&self) -> &DIER {
34        &self.dier
35    }
36    ///0x10 - status register
37    #[inline(always)]
38    pub const fn sr(&self) -> &SR {
39        &self.sr
40    }
41    ///0x14 - event generation register
42    #[inline(always)]
43    pub const fn egr(&self) -> &EGR {
44        &self.egr
45    }
46    ///0x18 - capture/compare mode register (input mode)
47    #[inline(always)]
48    pub const fn ccmr1_input(&self) -> &CCMR1_INPUT {
49        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
50    }
51    ///0x18 - capture/compare mode register (output mode)
52    #[inline(always)]
53    pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
54        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
55    }
56    ///0x20 - capture/compare enable register
57    #[inline(always)]
58    pub const fn ccer(&self) -> &CCER {
59        &self.ccer
60    }
61    ///0x24 - counter
62    #[inline(always)]
63    pub const fn cnt(&self) -> &CNT {
64        &self.cnt
65    }
66    ///0x28 - prescaler
67    #[inline(always)]
68    pub const fn psc(&self) -> &PSC {
69        &self.psc
70    }
71    ///0x2c - auto-reload register
72    #[inline(always)]
73    pub const fn arr(&self) -> &ARR {
74        &self.arr
75    }
76    ///0x34 - capture/compare register
77    ///
78    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `CCR1` register.</div>
79    #[inline(always)]
80    pub const fn ccr(&self, n: usize) -> &CCR {
81        &self.ccr[n]
82    }
83    ///Iterator for array of:
84    ///0x34 - capture/compare register
85    #[inline(always)]
86    pub fn ccr_iter(&self) -> impl Iterator<Item = &CCR> {
87        self.ccr.iter()
88    }
89    ///0x34 - capture/compare register
90    #[inline(always)]
91    pub const fn ccr1(&self) -> &CCR {
92        self.ccr(0)
93    }
94}
95/**CR1 (rw) register accessor: control register 1
96
97You can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
98
99See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#TIM10:CR1)
100
101For information about available fields see [`mod@cr1`] module*/
102pub type CR1 = crate::Reg<cr1::CR1rs>;
103///control register 1
104pub mod cr1;
105/**CR2 (rw) register accessor: control register 2
106
107You can [`read`](crate::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
108
109See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#TIM10:CR2)
110
111For information about available fields see [`mod@cr2`] module*/
112pub type CR2 = crate::Reg<cr2::CR2rs>;
113///control register 2
114pub mod cr2;
115/**DIER (rw) register accessor: DMA/Interrupt enable register
116
117You can [`read`](crate::Reg::read) this register and get [`dier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
118
119See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#TIM10:DIER)
120
121For information about available fields see [`mod@dier`] module*/
122pub type DIER = crate::Reg<dier::DIERrs>;
123///DMA/Interrupt enable register
124pub mod dier;
125/**SR (rw) register accessor: status register
126
127You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
128
129See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#TIM10:SR)
130
131For information about available fields see [`mod@sr`] module*/
132pub type SR = crate::Reg<sr::SRrs>;
133///status register
134pub mod sr;
135/**EGR (w) register accessor: event generation register
136
137You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
138
139See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#TIM10:EGR)
140
141For information about available fields see [`mod@egr`] module*/
142pub type EGR = crate::Reg<egr::EGRrs>;
143///event generation register
144pub mod egr;
145/**CCMR1_Output (rw) register accessor: capture/compare mode register (output mode)
146
147You can [`read`](crate::Reg::read) this register and get [`ccmr1_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
148
149See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#TIM10:CCMR1_Output)
150
151For information about available fields see [`mod@ccmr1_output`] module*/
152#[doc(alias = "CCMR1_Output")]
153pub type CCMR1_OUTPUT = crate::Reg<ccmr1_output::CCMR1_OUTPUTrs>;
154///capture/compare mode register (output mode)
155pub mod ccmr1_output;
156/**CCMR1_Input (rw) register accessor: capture/compare mode register (input mode)
157
158You can [`read`](crate::Reg::read) this register and get [`ccmr1_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
159
160See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#TIM10:CCMR1_Input)
161
162For information about available fields see [`mod@ccmr1_input`] module*/
163#[doc(alias = "CCMR1_Input")]
164pub type CCMR1_INPUT = crate::Reg<ccmr1_input::CCMR1_INPUTrs>;
165///capture/compare mode register (input mode)
166pub mod ccmr1_input;
167/**CCER (rw) register accessor: capture/compare enable register
168
169You can [`read`](crate::Reg::read) this register and get [`ccer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
170
171See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#TIM10:CCER)
172
173For information about available fields see [`mod@ccer`] module*/
174pub type CCER = crate::Reg<ccer::CCERrs>;
175///capture/compare enable register
176pub mod ccer;
177/**CNT (rw) register accessor: counter
178
179You can [`read`](crate::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
180
181See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#TIM10:CNT)
182
183For information about available fields see [`mod@cnt`] module*/
184pub type CNT = crate::Reg<cnt::CNTrs>;
185///counter
186pub mod cnt;
187/**PSC (rw) register accessor: prescaler
188
189You can [`read`](crate::Reg::read) this register and get [`psc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
190
191See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#TIM10:PSC)
192
193For information about available fields see [`mod@psc`] module*/
194pub type PSC = crate::Reg<psc::PSCrs>;
195///prescaler
196pub mod psc;
197/**ARR (rw) register accessor: auto-reload register
198
199You can [`read`](crate::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
200
201See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#TIM10:ARR)
202
203For information about available fields see [`mod@arr`] module*/
204pub type ARR = crate::Reg<arr::ARRrs>;
205///auto-reload register
206pub mod arr;
207/**CCR (rw) register accessor: capture/compare register
208
209You can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
210
211See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#TIM10:CCR[1])
212
213For information about available fields see [`mod@ccr`] module*/
214pub type CCR = crate::Reg<ccr::CCRrs>;
215///capture/compare register
216pub mod ccr;
stm32f1_staging/stm32f101/tim10.rs

stm32f1_staging/stm32f101/
tim10.rs
