stm32f1_staging/stm32f101/rcc/
apb2enr.rs

1///Register `APB2ENR` reader
2pub type R = crate::R<APB2ENRrs>;
3///Register `APB2ENR` writer
4pub type W = crate::W<APB2ENRrs>;
5/**Alternate function I/O clock enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum AFIOEN {
11    ///0: The selected clock is disabled
12    Disabled = 0,
13    ///1: The selected clock is enabled
14    Enabled = 1,
15}
16impl From<AFIOEN> for bool {
17    #[inline(always)]
18    fn from(variant: AFIOEN) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `AFIOEN` reader - Alternate function I/O clock enable
23pub type AFIOEN_R = crate::BitReader<AFIOEN>;
24impl AFIOEN_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> AFIOEN {
28        match self.bits {
29            false => AFIOEN::Disabled,
30            true => AFIOEN::Enabled,
31        }
32    }
33    ///The selected clock is disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == AFIOEN::Disabled
37    }
38    ///The selected clock is enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == AFIOEN::Enabled
42    }
43}
44///Field `AFIOEN` writer - Alternate function I/O clock enable
45pub type AFIOEN_W<'a, REG> = crate::BitWriter<'a, REG, AFIOEN>;
46impl<'a, REG> AFIOEN_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///The selected clock is disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(AFIOEN::Disabled)
54    }
55    ///The selected clock is enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(AFIOEN::Enabled)
59    }
60}
61///Field `IOPAEN` reader - I/O port A clock enable
62pub use AFIOEN_R as IOPAEN_R;
63///Field `IOPBEN` reader - I/O port B clock enable
64pub use AFIOEN_R as IOPBEN_R;
65///Field `IOPCEN` reader - I/O port C clock enable
66pub use AFIOEN_R as IOPCEN_R;
67///Field `IOPDEN` reader - I/O port D clock enable
68pub use AFIOEN_R as IOPDEN_R;
69///Field `IOPEEN` reader - I/O port E clock enable
70pub use AFIOEN_R as IOPEEN_R;
71///Field `IOPFEN` reader - I/O port F clock enable
72pub use AFIOEN_R as IOPFEN_R;
73///Field `IOPGEN` reader - I/O port G clock enable
74pub use AFIOEN_R as IOPGEN_R;
75///Field `ADC1EN` reader - ADC 1 interface clock enable
76pub use AFIOEN_R as ADC1EN_R;
77///Field `SPI1EN` reader - SPI 1 clock enable
78pub use AFIOEN_R as SPI1EN_R;
79///Field `USART1EN` reader - USART1 clock enable
80pub use AFIOEN_R as USART1EN_R;
81///Field `TIM9EN` reader - TIM9 Timer clock enable
82pub use AFIOEN_R as TIM9EN_R;
83///Field `TIM10EN` reader - TIM10 Timer clock enable
84pub use AFIOEN_R as TIM10EN_R;
85///Field `TIM11EN` reader - TIM11 Timer clock enable
86pub use AFIOEN_R as TIM11EN_R;
87///Field `IOPAEN` writer - I/O port A clock enable
88pub use AFIOEN_W as IOPAEN_W;
89///Field `IOPBEN` writer - I/O port B clock enable
90pub use AFIOEN_W as IOPBEN_W;
91///Field `IOPCEN` writer - I/O port C clock enable
92pub use AFIOEN_W as IOPCEN_W;
93///Field `IOPDEN` writer - I/O port D clock enable
94pub use AFIOEN_W as IOPDEN_W;
95///Field `IOPEEN` writer - I/O port E clock enable
96pub use AFIOEN_W as IOPEEN_W;
97///Field `IOPFEN` writer - I/O port F clock enable
98pub use AFIOEN_W as IOPFEN_W;
99///Field `IOPGEN` writer - I/O port G clock enable
100pub use AFIOEN_W as IOPGEN_W;
101///Field `ADC1EN` writer - ADC 1 interface clock enable
102pub use AFIOEN_W as ADC1EN_W;
103///Field `SPI1EN` writer - SPI 1 clock enable
104pub use AFIOEN_W as SPI1EN_W;
105///Field `USART1EN` writer - USART1 clock enable
106pub use AFIOEN_W as USART1EN_W;
107///Field `TIM9EN` writer - TIM9 Timer clock enable
108pub use AFIOEN_W as TIM9EN_W;
109///Field `TIM10EN` writer - TIM10 Timer clock enable
110pub use AFIOEN_W as TIM10EN_W;
111///Field `TIM11EN` writer - TIM11 Timer clock enable
112pub use AFIOEN_W as TIM11EN_W;
113impl R {
114    ///Bit 0 - Alternate function I/O clock enable
115    #[inline(always)]
116    pub fn afioen(&self) -> AFIOEN_R {
117        AFIOEN_R::new((self.bits & 1) != 0)
118    }
119    ///Bit 2 - I/O port A clock enable
120    #[inline(always)]
121    pub fn iopaen(&self) -> IOPAEN_R {
122        IOPAEN_R::new(((self.bits >> 2) & 1) != 0)
123    }
124    ///Bit 3 - I/O port B clock enable
125    #[inline(always)]
126    pub fn iopben(&self) -> IOPBEN_R {
127        IOPBEN_R::new(((self.bits >> 3) & 1) != 0)
128    }
129    ///Bit 4 - I/O port C clock enable
130    #[inline(always)]
131    pub fn iopcen(&self) -> IOPCEN_R {
132        IOPCEN_R::new(((self.bits >> 4) & 1) != 0)
133    }
134    ///Bit 5 - I/O port D clock enable
135    #[inline(always)]
136    pub fn iopden(&self) -> IOPDEN_R {
137        IOPDEN_R::new(((self.bits >> 5) & 1) != 0)
138    }
139    ///Bit 6 - I/O port E clock enable
140    #[inline(always)]
141    pub fn iopeen(&self) -> IOPEEN_R {
142        IOPEEN_R::new(((self.bits >> 6) & 1) != 0)
143    }
144    ///Bit 7 - I/O port F clock enable
145    #[inline(always)]
146    pub fn iopfen(&self) -> IOPFEN_R {
147        IOPFEN_R::new(((self.bits >> 7) & 1) != 0)
148    }
149    ///Bit 8 - I/O port G clock enable
150    #[inline(always)]
151    pub fn iopgen(&self) -> IOPGEN_R {
152        IOPGEN_R::new(((self.bits >> 8) & 1) != 0)
153    }
154    ///Bit 9 - ADC 1 interface clock enable
155    #[inline(always)]
156    pub fn adc1en(&self) -> ADC1EN_R {
157        ADC1EN_R::new(((self.bits >> 9) & 1) != 0)
158    }
159    ///Bit 12 - SPI 1 clock enable
160    #[inline(always)]
161    pub fn spi1en(&self) -> SPI1EN_R {
162        SPI1EN_R::new(((self.bits >> 12) & 1) != 0)
163    }
164    ///Bit 14 - USART1 clock enable
165    #[inline(always)]
166    pub fn usart1en(&self) -> USART1EN_R {
167        USART1EN_R::new(((self.bits >> 14) & 1) != 0)
168    }
169    ///Bit 19 - TIM9 Timer clock enable
170    #[inline(always)]
171    pub fn tim9en(&self) -> TIM9EN_R {
172        TIM9EN_R::new(((self.bits >> 19) & 1) != 0)
173    }
174    ///Bit 20 - TIM10 Timer clock enable
175    #[inline(always)]
176    pub fn tim10en(&self) -> TIM10EN_R {
177        TIM10EN_R::new(((self.bits >> 20) & 1) != 0)
178    }
179    ///Bit 21 - TIM11 Timer clock enable
180    #[inline(always)]
181    pub fn tim11en(&self) -> TIM11EN_R {
182        TIM11EN_R::new(((self.bits >> 21) & 1) != 0)
183    }
184}
185impl core::fmt::Debug for R {
186    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
187        f.debug_struct("APB2ENR")
188            .field("afioen", &self.afioen())
189            .field("iopaen", &self.iopaen())
190            .field("iopben", &self.iopben())
191            .field("iopcen", &self.iopcen())
192            .field("iopden", &self.iopden())
193            .field("iopeen", &self.iopeen())
194            .field("iopfen", &self.iopfen())
195            .field("iopgen", &self.iopgen())
196            .field("adc1en", &self.adc1en())
197            .field("spi1en", &self.spi1en())
198            .field("usart1en", &self.usart1en())
199            .field("tim9en", &self.tim9en())
200            .field("tim10en", &self.tim10en())
201            .field("tim11en", &self.tim11en())
202            .finish()
203    }
204}
205impl W {
206    ///Bit 0 - Alternate function I/O clock enable
207    #[inline(always)]
208    pub fn afioen(&mut self) -> AFIOEN_W<APB2ENRrs> {
209        AFIOEN_W::new(self, 0)
210    }
211    ///Bit 2 - I/O port A clock enable
212    #[inline(always)]
213    pub fn iopaen(&mut self) -> IOPAEN_W<APB2ENRrs> {
214        IOPAEN_W::new(self, 2)
215    }
216    ///Bit 3 - I/O port B clock enable
217    #[inline(always)]
218    pub fn iopben(&mut self) -> IOPBEN_W<APB2ENRrs> {
219        IOPBEN_W::new(self, 3)
220    }
221    ///Bit 4 - I/O port C clock enable
222    #[inline(always)]
223    pub fn iopcen(&mut self) -> IOPCEN_W<APB2ENRrs> {
224        IOPCEN_W::new(self, 4)
225    }
226    ///Bit 5 - I/O port D clock enable
227    #[inline(always)]
228    pub fn iopden(&mut self) -> IOPDEN_W<APB2ENRrs> {
229        IOPDEN_W::new(self, 5)
230    }
231    ///Bit 6 - I/O port E clock enable
232    #[inline(always)]
233    pub fn iopeen(&mut self) -> IOPEEN_W<APB2ENRrs> {
234        IOPEEN_W::new(self, 6)
235    }
236    ///Bit 7 - I/O port F clock enable
237    #[inline(always)]
238    pub fn iopfen(&mut self) -> IOPFEN_W<APB2ENRrs> {
239        IOPFEN_W::new(self, 7)
240    }
241    ///Bit 8 - I/O port G clock enable
242    #[inline(always)]
243    pub fn iopgen(&mut self) -> IOPGEN_W<APB2ENRrs> {
244        IOPGEN_W::new(self, 8)
245    }
246    ///Bit 9 - ADC 1 interface clock enable
247    #[inline(always)]
248    pub fn adc1en(&mut self) -> ADC1EN_W<APB2ENRrs> {
249        ADC1EN_W::new(self, 9)
250    }
251    ///Bit 12 - SPI 1 clock enable
252    #[inline(always)]
253    pub fn spi1en(&mut self) -> SPI1EN_W<APB2ENRrs> {
254        SPI1EN_W::new(self, 12)
255    }
256    ///Bit 14 - USART1 clock enable
257    #[inline(always)]
258    pub fn usart1en(&mut self) -> USART1EN_W<APB2ENRrs> {
259        USART1EN_W::new(self, 14)
260    }
261    ///Bit 19 - TIM9 Timer clock enable
262    #[inline(always)]
263    pub fn tim9en(&mut self) -> TIM9EN_W<APB2ENRrs> {
264        TIM9EN_W::new(self, 19)
265    }
266    ///Bit 20 - TIM10 Timer clock enable
267    #[inline(always)]
268    pub fn tim10en(&mut self) -> TIM10EN_W<APB2ENRrs> {
269        TIM10EN_W::new(self, 20)
270    }
271    ///Bit 21 - TIM11 Timer clock enable
272    #[inline(always)]
273    pub fn tim11en(&mut self) -> TIM11EN_W<APB2ENRrs> {
274        TIM11EN_W::new(self, 21)
275    }
276}
277/**APB2 peripheral clock enable register (RCC_APB2ENR)
278
279You can [`read`](crate::Reg::read) this register and get [`apb2enr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb2enr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
280
281See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#RCC:APB2ENR)*/
282pub struct APB2ENRrs;
283impl crate::RegisterSpec for APB2ENRrs {
284    type Ux = u32;
285}
286///`read()` method returns [`apb2enr::R`](R) reader structure
287impl crate::Readable for APB2ENRrs {}
288///`write(|w| ..)` method takes [`apb2enr::W`](W) writer structure
289impl crate::Writable for APB2ENRrs {
290    type Safety = crate::Unsafe;
291}
292///`reset()` method sets APB2ENR to value 0
293impl crate::Resettable for APB2ENRrs {}
stm32f1_staging/stm32f101/rcc/apb2enr.rs

stm32f1_staging/stm32f101/rcc/
apb2enr.rs
