stm32f1_staging/stm32f101/otg_fs_device/doep0/
tsiz.rs

1///Register `TSIZ` reader
2pub type R = crate::R<TSIZrs>;
3///Register `TSIZ` writer
4pub type W = crate::W<TSIZrs>;
5///Field `XFRSIZ` reader - Transfer size
6pub type XFRSIZ_R = crate::FieldReader;
7///Field `XFRSIZ` writer - Transfer size
8pub type XFRSIZ_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
9///Field `PKTCNT` reader - Packet count
10pub type PKTCNT_R = crate::BitReader;
11///Field `PKTCNT` writer - Packet count
12pub type PKTCNT_W<'a, REG> = crate::BitWriter<'a, REG>;
13///Field `STUPCNT` reader - SETUP packet count
14pub type STUPCNT_R = crate::FieldReader;
15///Field `STUPCNT` writer - SETUP packet count
16pub type STUPCNT_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17impl R {
18    ///Bits 0:6 - Transfer size
19    #[inline(always)]
20    pub fn xfrsiz(&self) -> XFRSIZ_R {
21        XFRSIZ_R::new((self.bits & 0x7f) as u8)
22    }
23    ///Bit 19 - Packet count
24    #[inline(always)]
25    pub fn pktcnt(&self) -> PKTCNT_R {
26        PKTCNT_R::new(((self.bits >> 19) & 1) != 0)
27    }
28    ///Bits 29:30 - SETUP packet count
29    #[inline(always)]
30    pub fn stupcnt(&self) -> STUPCNT_R {
31        STUPCNT_R::new(((self.bits >> 29) & 3) as u8)
32    }
33}
34impl core::fmt::Debug for R {
35    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
36        f.debug_struct("TSIZ")
37            .field("stupcnt", &self.stupcnt())
38            .field("pktcnt", &self.pktcnt())
39            .field("xfrsiz", &self.xfrsiz())
40            .finish()
41    }
42}
43impl W {
44    ///Bits 0:6 - Transfer size
45    #[inline(always)]
46    pub fn xfrsiz(&mut self) -> XFRSIZ_W<TSIZrs> {
47        XFRSIZ_W::new(self, 0)
48    }
49    ///Bit 19 - Packet count
50    #[inline(always)]
51    pub fn pktcnt(&mut self) -> PKTCNT_W<TSIZrs> {
52        PKTCNT_W::new(self, 19)
53    }
54    ///Bits 29:30 - SETUP packet count
55    #[inline(always)]
56    pub fn stupcnt(&mut self) -> STUPCNT_W<TSIZrs> {
57        STUPCNT_W::new(self, 29)
58    }
59}
60/**device OUT endpoint-0 transfer size register
61
62You can [`read`](crate::Reg::read) this register and get [`tsiz::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tsiz::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).*/
63pub struct TSIZrs;
64impl crate::RegisterSpec for TSIZrs {
65    type Ux = u32;
66}
67///`read()` method returns [`tsiz::R`](R) reader structure
68impl crate::Readable for TSIZrs {}
69///`write(|w| ..)` method takes [`tsiz::W`](W) writer structure
70impl crate::Writable for TSIZrs {
71    type Safety = crate::Unsafe;
72}
73///`reset()` method sets TSIZ to value 0
74impl crate::Resettable for TSIZrs {}
stm32f1_staging/stm32f101/otg_fs_device/doep0/tsiz.rs

stm32f1_staging/stm32f101/otg_fs_device/doep0/
tsiz.rs
