stm32f1_staging/stm32f100/
mod.rs

1/*!Peripheral access API for STM32F100 microcontrollers (generated using svd2rust v0.36.1 (a85deda 2025-04-04))
2
3You can find an overview of the generated API [here].
4
5API features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.
6
7[here]: https://docs.rs/svd2rust/0.36.1/svd2rust/#peripheral-api
8[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased
9[repository]: https://github.com/rust-embedded/svd2rust*/
10///Number available in the NVIC for configuring priority
11pub const NVIC_PRIO_BITS: u8 = 4;
12#[cfg(feature = "rt")]
13pub use self::Interrupt as interrupt;
14pub use cortex_m::peripheral::Peripherals as CorePeripherals;
15pub use cortex_m::peripheral::{
16    CBP, CPUID, DCB, DWT, FPB, ITM, MPU, NVIC, SCB, SYST, TPIU,
17};
18#[cfg(feature = "rt")]
19pub use cortex_m_rt::interrupt;
20#[cfg(feature = "rt")]
21extern "C" {
22    fn WWDG();
23    fn PVD();
24    fn TAMPER_STAMP();
25    fn RTC_WKUP();
26    fn FLASH();
27    fn RCC();
28    fn EXTI0();
29    fn EXTI1();
30    fn EXTI2();
31    fn EXTI3();
32    fn EXTI4();
33    fn DMA1_CHANNEL1();
34    fn DMA1_CHANNEL2();
35    fn DMA1_CHANNEL3();
36    fn DMA1_CHANNEL4();
37    fn DMA1_CHANNEL5();
38    fn DMA1_CHANNEL6();
39    fn DMA1_CHANNEL7();
40    fn ADC();
41    fn EXTI9_5();
42    fn TIM1_BRK_TIM15();
43    fn TIM1_UP_TIM16();
44    fn TIM1_TRG_COM_TIM17();
45    fn TIM1_CC();
46    fn TIM2();
47    fn TIM3();
48    fn TIM4();
49    fn I2C1_EV();
50    fn I2C1_ER();
51    fn I2C2_EV();
52    fn I2C2_ER();
53    fn SPI1();
54    fn SPI2();
55    fn USART1();
56    fn USART2();
57    fn USART3();
58    fn EXTI15_10();
59    fn RTCALARM();
60    fn CEC();
61    fn TIM12();
62    fn TIM13();
63    fn TIM14();
64    fn FSMC();
65    fn TIM5();
66    fn SPI3();
67    fn UART4();
68    fn UART5();
69    fn TIM6_DAC();
70    fn TIM7();
71    fn DMA2_CHANNEL1();
72    fn DMA2_CHANNEL2();
73    fn DMA2_CHANNEL3();
74    fn DMA2_CHANNEL4_5();
75}
76#[doc(hidden)]
77#[repr(C)]
78pub union Vector {
79    _handler: unsafe extern "C" fn(),
80    _reserved: u32,
81}
82#[cfg(feature = "rt")]
83#[doc(hidden)]
84#[link_section = ".vector_table.interrupts"]
85#[no_mangle]
86pub static __INTERRUPTS: [Vector; 60] = [
87    Vector { _handler: WWDG },
88    Vector { _handler: PVD },
89    Vector { _handler: TAMPER_STAMP },
90    Vector { _handler: RTC_WKUP },
91    Vector { _handler: FLASH },
92    Vector { _handler: RCC },
93    Vector { _handler: EXTI0 },
94    Vector { _handler: EXTI1 },
95    Vector { _handler: EXTI2 },
96    Vector { _handler: EXTI3 },
97    Vector { _handler: EXTI4 },
98    Vector { _handler: DMA1_CHANNEL1 },
99    Vector { _handler: DMA1_CHANNEL2 },
100    Vector { _handler: DMA1_CHANNEL3 },
101    Vector { _handler: DMA1_CHANNEL4 },
102    Vector { _handler: DMA1_CHANNEL5 },
103    Vector { _handler: DMA1_CHANNEL6 },
104    Vector { _handler: DMA1_CHANNEL7 },
105    Vector { _handler: ADC },
106    Vector { _reserved: 0 },
107    Vector { _reserved: 0 },
108    Vector { _reserved: 0 },
109    Vector { _reserved: 0 },
110    Vector { _handler: EXTI9_5 },
111    Vector { _handler: TIM1_BRK_TIM15 },
112    Vector { _handler: TIM1_UP_TIM16 },
113    Vector {
114        _handler: TIM1_TRG_COM_TIM17,
115    },
116    Vector { _handler: TIM1_CC },
117    Vector { _handler: TIM2 },
118    Vector { _handler: TIM3 },
119    Vector { _handler: TIM4 },
120    Vector { _handler: I2C1_EV },
121    Vector { _handler: I2C1_ER },
122    Vector { _handler: I2C2_EV },
123    Vector { _handler: I2C2_ER },
124    Vector { _handler: SPI1 },
125    Vector { _handler: SPI2 },
126    Vector { _handler: USART1 },
127    Vector { _handler: USART2 },
128    Vector { _handler: USART3 },
129    Vector { _handler: EXTI15_10 },
130    Vector { _handler: RTCALARM },
131    Vector { _handler: CEC },
132    Vector { _handler: TIM12 },
133    Vector { _handler: TIM13 },
134    Vector { _handler: TIM14 },
135    Vector { _reserved: 0 },
136    Vector { _reserved: 0 },
137    Vector { _handler: FSMC },
138    Vector { _reserved: 0 },
139    Vector { _handler: TIM5 },
140    Vector { _handler: SPI3 },
141    Vector { _handler: UART4 },
142    Vector { _handler: UART5 },
143    Vector { _handler: TIM6_DAC },
144    Vector { _handler: TIM7 },
145    Vector { _handler: DMA2_CHANNEL1 },
146    Vector { _handler: DMA2_CHANNEL2 },
147    Vector { _handler: DMA2_CHANNEL3 },
148    Vector {
149        _handler: DMA2_CHANNEL4_5,
150    },
151];
152///Enumeration of all the interrupts.
153#[cfg_attr(feature = "defmt", derive(defmt::Format))]
154#[derive(Copy, Clone, Debug, PartialEq, Eq)]
155#[repr(u16)]
156pub enum Interrupt {
157    ///0 - Window Watchdog interrupt
158    WWDG = 0,
159    ///1 - PVD through EXTI line detection interrupt
160    PVD = 1,
161    ///2 - Tamper and TimeStamp through EXTI line interrupts
162    TAMPER_STAMP = 2,
163    ///3 - RTC Wakeup through EXTI line interrupt
164    RTC_WKUP = 3,
165    ///4 - Flash global interrupt
166    FLASH = 4,
167    ///5 - RCC global interrupt
168    RCC = 5,
169    ///6 - EXTI Line0 interrupt
170    EXTI0 = 6,
171    ///7 - EXTI Line1 interrupt
172    EXTI1 = 7,
173    ///8 - EXTI Line2 interrupt
174    EXTI2 = 8,
175    ///9 - EXTI Line3 interrupt
176    EXTI3 = 9,
177    ///10 - EXTI Line4 interrupt
178    EXTI4 = 10,
179    ///11 - DMA1 Channel1 global interrupt
180    DMA1_CHANNEL1 = 11,
181    ///12 - DMA1 Channel2 global interrupt
182    DMA1_CHANNEL2 = 12,
183    ///13 - DMA1 Channel3 global interrupt
184    DMA1_CHANNEL3 = 13,
185    ///14 - DMA1 Channel4 global interrupt
186    DMA1_CHANNEL4 = 14,
187    ///15 - DMA1 Channel5 global interrupt
188    DMA1_CHANNEL5 = 15,
189    ///16 - DMA1 Channel6 global interrupt
190    DMA1_CHANNEL6 = 16,
191    ///17 - DMA1 Channel7 global interrupt
192    DMA1_CHANNEL7 = 17,
193    ///18 - ADC1 global interrupt
194    ADC = 18,
195    ///23 - EXTI Line\[9:5\] interrupts
196    EXTI9_5 = 23,
197    ///24 - TIM1 Break interrupt and TIM15 global interrupt
198    TIM1_BRK_TIM15 = 24,
199    ///25 - TIM1 Update interrupt and TIM16 global interrupt
200    TIM1_UP_TIM16 = 25,
201    ///26 - TIM1 Trigger and Commutation interrupts and TIM17 global interrupt
202    TIM1_TRG_COM_TIM17 = 26,
203    ///27 - TIM1 Capture Compare interrupt
204    TIM1_CC = 27,
205    ///28 - TIM2 global interrupt
206    TIM2 = 28,
207    ///29 - TIM3 global interrupt
208    TIM3 = 29,
209    ///30 - TIM4 global interrupt
210    TIM4 = 30,
211    ///31 - I2C1 event interrupt
212    I2C1_EV = 31,
213    ///32 - I2C1 error interrupt
214    I2C1_ER = 32,
215    ///33 - I2C2 event interrupt
216    I2C2_EV = 33,
217    ///34 - I2C2 error interrupt
218    I2C2_ER = 34,
219    ///35 - SPI1 global interrupt
220    SPI1 = 35,
221    ///36 - SPI2 global interrupt
222    SPI2 = 36,
223    ///37 - USART1 global interrupt
224    USART1 = 37,
225    ///38 - USART2 global interrupt
226    USART2 = 38,
227    ///39 - USART3 global interrupt
228    USART3 = 39,
229    ///40 - EXTI Line\[15:10\] interrupts
230    EXTI15_10 = 40,
231    ///41 - RTC Alarms through EXTI line interrupt
232    RTCALARM = 41,
233    ///42 - CEC global interrupt
234    CEC = 42,
235    ///43 - TIM12 global interrupt
236    TIM12 = 43,
237    ///44 - TIM13 global interrupt
238    TIM13 = 44,
239    ///45 - TIM14 global interrupt
240    TIM14 = 45,
241    ///48 - FSMC global interrupt
242    FSMC = 48,
243    ///50 - TIM5 global interrupt
244    TIM5 = 50,
245    ///51 - SPI3 global interrupt
246    SPI3 = 51,
247    ///52 - UART4 global interrupt
248    UART4 = 52,
249    ///53 - UART5 global interrupt
250    UART5 = 53,
251    ///54 - TIM6 global and DAC underrun interrupts
252    TIM6_DAC = 54,
253    ///55 - TIM7 global interrupt
254    TIM7 = 55,
255    ///56 - DMA2 Channel1 global interrupt
256    DMA2_CHANNEL1 = 56,
257    ///57 - DMA2 Channel2 global interrupt
258    DMA2_CHANNEL2 = 57,
259    ///58 - DMA2 Channel3 global interrupt
260    DMA2_CHANNEL3 = 58,
261    ///59 - DMA2 Channel4 and DMA2 Channel5 global interrupt
262    DMA2_CHANNEL4_5 = 59,
263}
264unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
265    #[inline(always)]
266    fn number(self) -> u16 {
267        self as u16
268    }
269}
270///Flexible static memory controller
271///
272///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#FSMC)
273pub type FSMC = crate::Periph<fsmc::RegisterBlock, 0xa000_0000>;
274impl core::fmt::Debug for FSMC {
275    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
276        f.debug_struct("FSMC").finish()
277    }
278}
279///Flexible static memory controller
280pub mod fsmc;
281///Power control
282///
283///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#PWR)
284pub type PWR = crate::Periph<pwr::RegisterBlock, 0x4000_7000>;
285impl core::fmt::Debug for PWR {
286    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
287        f.debug_struct("PWR").finish()
288    }
289}
290///Power control
291pub mod pwr;
292///Reset and clock control
293///
294///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#RCC)
295pub type RCC = crate::Periph<rcc::RegisterBlock, 0x4002_1000>;
296impl core::fmt::Debug for RCC {
297    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
298        f.debug_struct("RCC").finish()
299    }
300}
301///Reset and clock control
302pub mod rcc;
303///General purpose I/O
304///
305///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#GPIOA)
306pub type GPIOA = crate::Periph<gpioa::RegisterBlock, 0x4001_0800>;
307impl core::fmt::Debug for GPIOA {
308    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
309        f.debug_struct("GPIOA").finish()
310    }
311}
312///General purpose I/O
313pub mod gpioa;
314///General purpose I/O
315///
316///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#GPIOA)
317pub type GPIOB = crate::Periph<gpioa::RegisterBlock, 0x4001_0c00>;
318impl core::fmt::Debug for GPIOB {
319    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
320        f.debug_struct("GPIOB").finish()
321    }
322}
323///General purpose I/O
324pub use self::gpioa as gpiob;
325///General purpose I/O
326///
327///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#GPIOA)
328pub type GPIOC = crate::Periph<gpioa::RegisterBlock, 0x4001_1000>;
329impl core::fmt::Debug for GPIOC {
330    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
331        f.debug_struct("GPIOC").finish()
332    }
333}
334///General purpose I/O
335pub use self::gpioa as gpioc;
336///General purpose I/O
337///
338///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#GPIOA)
339pub type GPIOD = crate::Periph<gpioa::RegisterBlock, 0x4001_1400>;
340impl core::fmt::Debug for GPIOD {
341    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
342        f.debug_struct("GPIOD").finish()
343    }
344}
345///General purpose I/O
346pub use self::gpioa as gpiod;
347///General purpose I/O
348///
349///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#GPIOA)
350pub type GPIOE = crate::Periph<gpioa::RegisterBlock, 0x4001_1800>;
351impl core::fmt::Debug for GPIOE {
352    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
353        f.debug_struct("GPIOE").finish()
354    }
355}
356///General purpose I/O
357pub use self::gpioa as gpioe;
358///General purpose I/O
359///
360///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#GPIOA)
361pub type GPIOF = crate::Periph<gpioa::RegisterBlock, 0x4001_1c00>;
362impl core::fmt::Debug for GPIOF {
363    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
364        f.debug_struct("GPIOF").finish()
365    }
366}
367///General purpose I/O
368pub use self::gpioa as gpiof;
369///General purpose I/O
370///
371///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#GPIOA)
372pub type GPIOG = crate::Periph<gpioa::RegisterBlock, 0x4001_2000>;
373impl core::fmt::Debug for GPIOG {
374    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
375        f.debug_struct("GPIOG").finish()
376    }
377}
378///General purpose I/O
379pub use self::gpioa as gpiog;
380///Alternate function I/O
381///
382///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#AFIO)
383pub type AFIO = crate::Periph<afio::RegisterBlock, 0x4001_0000>;
384impl core::fmt::Debug for AFIO {
385    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
386        f.debug_struct("AFIO").finish()
387    }
388}
389///Alternate function I/O
390pub mod afio;
391///EXTI
392///
393///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#EXTI)
394pub type EXTI = crate::Periph<exti::RegisterBlock, 0x4001_0400>;
395impl core::fmt::Debug for EXTI {
396    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
397        f.debug_struct("EXTI").finish()
398    }
399}
400///EXTI
401pub mod exti;
402///DMA controller
403///
404///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#DMA1)
405pub type DMA1 = crate::Periph<dma1::RegisterBlock, 0x4002_0000>;
406impl core::fmt::Debug for DMA1 {
407    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
408        f.debug_struct("DMA1").finish()
409    }
410}
411///DMA controller
412pub mod dma1;
413///DMA controller
414///
415///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#DMA1)
416pub type DMA2 = crate::Periph<dma1::RegisterBlock, 0x4002_0400>;
417impl core::fmt::Debug for DMA2 {
418    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
419        f.debug_struct("DMA2").finish()
420    }
421}
422///DMA controller
423pub use self::dma1 as dma2;
424///Real time clock
425///
426///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#RTC)
427pub type RTC = crate::Periph<rtc::RegisterBlock, 0x4000_2800>;
428impl core::fmt::Debug for RTC {
429    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
430        f.debug_struct("RTC").finish()
431    }
432}
433///Real time clock
434pub mod rtc;
435///Backup registers
436///
437///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#BKP)
438pub type BKP = crate::Periph<bkp::RegisterBlock, 0x4000_6c04>;
439impl core::fmt::Debug for BKP {
440    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
441        f.debug_struct("BKP").finish()
442    }
443}
444///Backup registers
445pub mod bkp;
446///Independent watchdog
447///
448///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#IWDG)
449pub type IWDG = crate::Periph<iwdg::RegisterBlock, 0x4000_3000>;
450impl core::fmt::Debug for IWDG {
451    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
452        f.debug_struct("IWDG").finish()
453    }
454}
455///Independent watchdog
456pub mod iwdg;
457///Window watchdog
458///
459///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#WWDG)
460pub type WWDG = crate::Periph<wwdg::RegisterBlock, 0x4000_2c00>;
461impl core::fmt::Debug for WWDG {
462    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
463        f.debug_struct("WWDG").finish()
464    }
465}
466///Window watchdog
467pub mod wwdg;
468///Advanced timer
469///
470///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM1)
471pub type TIM1 = crate::Periph<tim1::RegisterBlock, 0x4001_2c00>;
472impl core::fmt::Debug for TIM1 {
473    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
474        f.debug_struct("TIM1").finish()
475    }
476}
477///Advanced timer
478pub mod tim1;
479///General purpose timer
480///
481///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM2)
482pub type TIM2 = crate::Periph<tim2::RegisterBlock, 0x4000_0000>;
483impl core::fmt::Debug for TIM2 {
484    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
485        f.debug_struct("TIM2").finish()
486    }
487}
488///General purpose timer
489pub mod tim2;
490///General purpose timer
491///
492///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM2)
493pub type TIM3 = crate::Periph<tim2::RegisterBlock, 0x4000_0400>;
494impl core::fmt::Debug for TIM3 {
495    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
496        f.debug_struct("TIM3").finish()
497    }
498}
499///General purpose timer
500pub use self::tim2 as tim3;
501///General purpose timer
502///
503///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM2)
504pub type TIM4 = crate::Periph<tim2::RegisterBlock, 0x4000_0800>;
505impl core::fmt::Debug for TIM4 {
506    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
507        f.debug_struct("TIM4").finish()
508    }
509}
510///General purpose timer
511pub use self::tim2 as tim4;
512///General purpose timer
513///
514///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM2)
515pub type TIM5 = crate::Periph<tim2::RegisterBlock, 0x4000_0c00>;
516impl core::fmt::Debug for TIM5 {
517    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
518        f.debug_struct("TIM5").finish()
519    }
520}
521///General purpose timer
522pub use self::tim2 as tim5;
523///General purpose timer
524///
525///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM12)
526pub type TIM12 = crate::Periph<tim12::RegisterBlock, 0x4000_1800>;
527impl core::fmt::Debug for TIM12 {
528    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
529        f.debug_struct("TIM12").finish()
530    }
531}
532///General purpose timer
533pub mod tim12;
534///General purpose timer
535///
536///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM13)
537pub type TIM13 = crate::Periph<tim13::RegisterBlock, 0x4000_1c00>;
538impl core::fmt::Debug for TIM13 {
539    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
540        f.debug_struct("TIM13").finish()
541    }
542}
543///General purpose timer
544pub mod tim13;
545///General purpose timer
546///
547///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM13)
548pub type TIM14 = crate::Periph<tim13::RegisterBlock, 0x4000_2000>;
549impl core::fmt::Debug for TIM14 {
550    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
551        f.debug_struct("TIM14").finish()
552    }
553}
554///General purpose timer
555pub use self::tim13 as tim14;
556///Basic timer
557///
558///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM6)
559pub type TIM6 = crate::Periph<tim6::RegisterBlock, 0x4000_1000>;
560impl core::fmt::Debug for TIM6 {
561    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
562        f.debug_struct("TIM6").finish()
563    }
564}
565///Basic timer
566pub mod tim6;
567///Basic timer
568///
569///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM6)
570pub type TIM7 = crate::Periph<tim6::RegisterBlock, 0x4000_1400>;
571impl core::fmt::Debug for TIM7 {
572    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
573        f.debug_struct("TIM7").finish()
574    }
575}
576///Basic timer
577pub use self::tim6 as tim7;
578///Inter integrated circuit
579///
580///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#I2C1)
581pub type I2C1 = crate::Periph<i2c1::RegisterBlock, 0x4000_5400>;
582impl core::fmt::Debug for I2C1 {
583    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
584        f.debug_struct("I2C1").finish()
585    }
586}
587///Inter integrated circuit
588pub mod i2c1;
589///Inter integrated circuit
590///
591///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#I2C1)
592pub type I2C2 = crate::Periph<i2c1::RegisterBlock, 0x4000_5800>;
593impl core::fmt::Debug for I2C2 {
594    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
595        f.debug_struct("I2C2").finish()
596    }
597}
598///Inter integrated circuit
599pub use self::i2c1 as i2c2;
600///Serial peripheral interface
601///
602///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#SPI1)
603pub type SPI1 = crate::Periph<spi1::RegisterBlock, 0x4001_3000>;
604impl core::fmt::Debug for SPI1 {
605    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
606        f.debug_struct("SPI1").finish()
607    }
608}
609///Serial peripheral interface
610pub mod spi1;
611///Serial peripheral interface
612///
613///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#SPI1)
614pub type SPI2 = crate::Periph<spi1::RegisterBlock, 0x4000_3800>;
615impl core::fmt::Debug for SPI2 {
616    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
617        f.debug_struct("SPI2").finish()
618    }
619}
620///Serial peripheral interface
621pub use self::spi1 as spi2;
622///Serial peripheral interface
623///
624///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#SPI1)
625pub type SPI3 = crate::Periph<spi1::RegisterBlock, 0x4000_3c00>;
626impl core::fmt::Debug for SPI3 {
627    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
628        f.debug_struct("SPI3").finish()
629    }
630}
631///Serial peripheral interface
632pub use self::spi1 as spi3;
633///Universal synchronous asynchronous receiver transmitter
634///
635///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#USART1)
636pub type USART1 = crate::Periph<usart1::RegisterBlock, 0x4001_3800>;
637impl core::fmt::Debug for USART1 {
638    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
639        f.debug_struct("USART1").finish()
640    }
641}
642///Universal synchronous asynchronous receiver transmitter
643pub mod usart1;
644///Universal synchronous asynchronous receiver transmitter
645///
646///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#USART1)
647pub type USART2 = crate::Periph<usart1::RegisterBlock, 0x4000_4400>;
648impl core::fmt::Debug for USART2 {
649    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
650        f.debug_struct("USART2").finish()
651    }
652}
653///Universal synchronous asynchronous receiver transmitter
654pub use self::usart1 as usart2;
655///Universal synchronous asynchronous receiver transmitter
656///
657///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#USART1)
658pub type USART3 = crate::Periph<usart1::RegisterBlock, 0x4000_4800>;
659impl core::fmt::Debug for USART3 {
660    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
661        f.debug_struct("USART3").finish()
662    }
663}
664///Universal synchronous asynchronous receiver transmitter
665pub use self::usart1 as usart3;
666///Analog to digital converter
667///
668///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#ADC1)
669pub type ADC1 = crate::Periph<adc1::RegisterBlock, 0x4001_2400>;
670impl core::fmt::Debug for ADC1 {
671    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
672        f.debug_struct("ADC1").finish()
673    }
674}
675///Analog to digital converter
676pub mod adc1;
677///Digital to analog converter
678///
679///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#DAC)
680pub type DAC = crate::Periph<dac::RegisterBlock, 0x4000_7400>;
681impl core::fmt::Debug for DAC {
682    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
683        f.debug_struct("DAC").finish()
684    }
685}
686///Digital to analog converter
687pub mod dac;
688///Debug support
689///
690///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#DBGMCU)
691pub type DBGMCU = crate::Periph<dbgmcu::RegisterBlock, 0xe004_2000>;
692impl core::fmt::Debug for DBGMCU {
693    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
694        f.debug_struct("DBGMCU").finish()
695    }
696}
697///Debug support
698pub mod dbgmcu;
699///Universal asynchronous receiver transmitter
700///
701///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#UART4)
702pub type UART4 = crate::Periph<uart4::RegisterBlock, 0x4000_4c00>;
703impl core::fmt::Debug for UART4 {
704    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
705        f.debug_struct("UART4").finish()
706    }
707}
708///Universal asynchronous receiver transmitter
709pub mod uart4;
710///Universal asynchronous receiver transmitter
711///
712///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#UART4)
713pub type UART5 = crate::Periph<uart4::RegisterBlock, 0x4000_5000>;
714impl core::fmt::Debug for UART5 {
715    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
716        f.debug_struct("UART5").finish()
717    }
718}
719///Universal asynchronous receiver transmitter
720pub use self::uart4 as uart5;
721///CRC calculation unit
722///
723///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#CRC)
724pub type CRC = crate::Periph<crc::RegisterBlock, 0x4002_3000>;
725impl core::fmt::Debug for CRC {
726    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
727        f.debug_struct("CRC").finish()
728    }
729}
730///CRC calculation unit
731pub mod crc;
732///FLASH
733///
734///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#FLASH)
735pub type FLASH = crate::Periph<flash::RegisterBlock, 0x4002_2000>;
736impl core::fmt::Debug for FLASH {
737    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
738        f.debug_struct("FLASH").finish()
739    }
740}
741///FLASH
742pub mod flash;
743///General purpose timers
744///
745///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM15)
746pub type TIM15 = crate::Periph<tim15::RegisterBlock, 0x4001_4000>;
747impl core::fmt::Debug for TIM15 {
748    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
749        f.debug_struct("TIM15").finish()
750    }
751}
752///General purpose timers
753pub mod tim15;
754///General-purpose-timers
755///
756///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM16)
757pub type TIM16 = crate::Periph<tim16::RegisterBlock, 0x4001_4400>;
758impl core::fmt::Debug for TIM16 {
759    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
760        f.debug_struct("TIM16").finish()
761    }
762}
763///General-purpose-timers
764pub mod tim16;
765///General-purpose-timers
766///
767///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM16)
768pub type TIM17 = crate::Periph<tim16::RegisterBlock, 0x4001_4800>;
769impl core::fmt::Debug for TIM17 {
770    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
771        f.debug_struct("TIM17").finish()
772    }
773}
774///General-purpose-timers
775pub use self::tim16 as tim17;
776///HDMI-CEC controller
777///
778///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#CEC)
779pub type CEC = crate::Periph<cec::RegisterBlock, 0x4000_7800>;
780impl core::fmt::Debug for CEC {
781    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
782        f.debug_struct("CEC").finish()
783    }
784}
785///HDMI-CEC controller
786pub mod cec;
787///System control block ACTLR
788///
789///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#SCB_ACTRL)
790pub type SCB_ACTRL = crate::Periph<scb_actrl::RegisterBlock, 0xe000_e008>;
791impl core::fmt::Debug for SCB_ACTRL {
792    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
793        f.debug_struct("SCB_ACTRL").finish()
794    }
795}
796///System control block ACTLR
797pub mod scb_actrl;
798///Nested vectored interrupt controller
799///
800///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#NVIC_STIR)
801pub type NVIC_STIR = crate::Periph<nvic_stir::RegisterBlock, 0xe000_ef00>;
802impl core::fmt::Debug for NVIC_STIR {
803    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
804        f.debug_struct("NVIC_STIR").finish()
805    }
806}
807///Nested vectored interrupt controller
808pub mod nvic_stir;
809///SysTick timer
810///
811///See peripheral [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#STK)
812pub type STK = crate::Periph<stk::RegisterBlock, 0xe000_e010>;
813impl core::fmt::Debug for STK {
814    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
815        f.debug_struct("STK").finish()
816    }
817}
818///SysTick timer
819pub mod stk;
820#[no_mangle]
821static mut DEVICE_PERIPHERALS: bool = false;
822/// All the peripherals.
823#[allow(non_snake_case)]
824pub struct Peripherals {
825    ///FSMC
826    pub FSMC: FSMC,
827    ///PWR
828    pub PWR: PWR,
829    ///RCC
830    pub RCC: RCC,
831    ///GPIOA
832    pub GPIOA: GPIOA,
833    ///GPIOB
834    pub GPIOB: GPIOB,
835    ///GPIOC
836    pub GPIOC: GPIOC,
837    ///GPIOD
838    pub GPIOD: GPIOD,
839    ///GPIOE
840    pub GPIOE: GPIOE,
841    ///GPIOF
842    pub GPIOF: GPIOF,
843    ///GPIOG
844    pub GPIOG: GPIOG,
845    ///AFIO
846    pub AFIO: AFIO,
847    ///EXTI
848    pub EXTI: EXTI,
849    ///DMA1
850    pub DMA1: DMA1,
851    ///DMA2
852    pub DMA2: DMA2,
853    ///RTC
854    pub RTC: RTC,
855    ///BKP
856    pub BKP: BKP,
857    ///IWDG
858    pub IWDG: IWDG,
859    ///WWDG
860    pub WWDG: WWDG,
861    ///TIM1
862    pub TIM1: TIM1,
863    ///TIM2
864    pub TIM2: TIM2,
865    ///TIM3
866    pub TIM3: TIM3,
867    ///TIM4
868    pub TIM4: TIM4,
869    ///TIM5
870    pub TIM5: TIM5,
871    ///TIM12
872    pub TIM12: TIM12,
873    ///TIM13
874    pub TIM13: TIM13,
875    ///TIM14
876    pub TIM14: TIM14,
877    ///TIM6
878    pub TIM6: TIM6,
879    ///TIM7
880    pub TIM7: TIM7,
881    ///I2C1
882    pub I2C1: I2C1,
883    ///I2C2
884    pub I2C2: I2C2,
885    ///SPI1
886    pub SPI1: SPI1,
887    ///SPI2
888    pub SPI2: SPI2,
889    ///SPI3
890    pub SPI3: SPI3,
891    ///USART1
892    pub USART1: USART1,
893    ///USART2
894    pub USART2: USART2,
895    ///USART3
896    pub USART3: USART3,
897    ///ADC1
898    pub ADC1: ADC1,
899    ///DAC
900    pub DAC: DAC,
901    ///DBGMCU
902    pub DBGMCU: DBGMCU,
903    ///UART4
904    pub UART4: UART4,
905    ///UART5
906    pub UART5: UART5,
907    ///CRC
908    pub CRC: CRC,
909    ///FLASH
910    pub FLASH: FLASH,
911    ///TIM15
912    pub TIM15: TIM15,
913    ///TIM16
914    pub TIM16: TIM16,
915    ///TIM17
916    pub TIM17: TIM17,
917    ///CEC
918    pub CEC: CEC,
919    ///SCB_ACTRL
920    pub SCB_ACTRL: SCB_ACTRL,
921    ///NVIC_STIR
922    pub NVIC_STIR: NVIC_STIR,
923    ///STK
924    pub STK: STK,
925}
926impl Peripherals {
927    /// Returns all the peripherals *once*.
928    #[cfg(feature = "critical-section")]
929    #[inline]
930    pub fn take() -> Option<Self> {
931        critical_section::with(|_| {
932            if unsafe { DEVICE_PERIPHERALS } {
933                return None;
934            }
935            Some(unsafe { Peripherals::steal() })
936        })
937    }
938    /// Unchecked version of `Peripherals::take`.
939    ///
940    /// # Safety
941    ///
942    /// Each of the returned peripherals must be used at most once.
943    #[inline]
944    pub unsafe fn steal() -> Self {
945        DEVICE_PERIPHERALS = true;
946        Peripherals {
947            FSMC: FSMC::steal(),
948            PWR: PWR::steal(),
949            RCC: RCC::steal(),
950            GPIOA: GPIOA::steal(),
951            GPIOB: GPIOB::steal(),
952            GPIOC: GPIOC::steal(),
953            GPIOD: GPIOD::steal(),
954            GPIOE: GPIOE::steal(),
955            GPIOF: GPIOF::steal(),
956            GPIOG: GPIOG::steal(),
957            AFIO: AFIO::steal(),
958            EXTI: EXTI::steal(),
959            DMA1: DMA1::steal(),
960            DMA2: DMA2::steal(),
961            RTC: RTC::steal(),
962            BKP: BKP::steal(),
963            IWDG: IWDG::steal(),
964            WWDG: WWDG::steal(),
965            TIM1: TIM1::steal(),
966            TIM2: TIM2::steal(),
967            TIM3: TIM3::steal(),
968            TIM4: TIM4::steal(),
969            TIM5: TIM5::steal(),
970            TIM12: TIM12::steal(),
971            TIM13: TIM13::steal(),
972            TIM14: TIM14::steal(),
973            TIM6: TIM6::steal(),
974            TIM7: TIM7::steal(),
975            I2C1: I2C1::steal(),
976            I2C2: I2C2::steal(),
977            SPI1: SPI1::steal(),
978            SPI2: SPI2::steal(),
979            SPI3: SPI3::steal(),
980            USART1: USART1::steal(),
981            USART2: USART2::steal(),
982            USART3: USART3::steal(),
983            ADC1: ADC1::steal(),
984            DAC: DAC::steal(),
985            DBGMCU: DBGMCU::steal(),
986            UART4: UART4::steal(),
987            UART5: UART5::steal(),
988            CRC: CRC::steal(),
989            FLASH: FLASH::steal(),
990            TIM15: TIM15::steal(),
991            TIM16: TIM16::steal(),
992            TIM17: TIM17::steal(),
993            CEC: CEC::steal(),
994            SCB_ACTRL: SCB_ACTRL::steal(),
995            NVIC_STIR: NVIC_STIR::steal(),
996            STK: STK::steal(),
997        }
998    }
999}
stm32f1_staging/stm32f100/mod.rs

stm32f1_staging/stm32f100/
mod.rs
