stm32f1_staging/stm32f100/
fsmc.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    bcr1: BCR1,
6    btr: (),
7    _reserved2: [u8; 0x04],
8    bcr: (),
9    _reserved3: [u8; 0xfc],
10    bwtr: (),
11}
12impl RegisterBlock {
13    ///0x00 - SRAM/NOR-Flash chip-select control register 1
14    #[inline(always)]
15    pub const fn bcr1(&self) -> &BCR1 {
16        &self.bcr1
17    }
18    ///0x04..0x14 - SRAM/NOR-Flash chip-select timing register %s
19    ///
20    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `BTR1` register.</div>
21    #[inline(always)]
22    pub const fn btr(&self, n: usize) -> &BTR {
23        #[allow(clippy::no_effect)] [(); 4][n];
24        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(4).add(8 * n).cast() }
25    }
26    ///Iterator for array of:
27    ///0x04..0x14 - SRAM/NOR-Flash chip-select timing register %s
28    #[inline(always)]
29    pub fn btr_iter(&self) -> impl Iterator<Item = &BTR> {
30        (0..4)
31            .map(move |n| unsafe {
32                &*core::ptr::from_ref(self).cast::<u8>().add(4).add(8 * n).cast()
33            })
34    }
35    ///0x04 - SRAM/NOR-Flash chip-select timing register 1
36    #[inline(always)]
37    pub const fn btr1(&self) -> &BTR {
38        self.btr(0)
39    }
40    ///0x0c - SRAM/NOR-Flash chip-select timing register 2
41    #[inline(always)]
42    pub const fn btr2(&self) -> &BTR {
43        self.btr(1)
44    }
45    ///0x14 - SRAM/NOR-Flash chip-select timing register 3
46    #[inline(always)]
47    pub const fn btr3(&self) -> &BTR {
48        self.btr(2)
49    }
50    ///0x1c - SRAM/NOR-Flash chip-select timing register 4
51    #[inline(always)]
52    pub const fn btr4(&self) -> &BTR {
53        self.btr(3)
54    }
55    ///0x08..0x14 - SRAM/NOR-Flash chip-select control register %s
56    ///
57    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `BCR2` register.</div>
58    #[inline(always)]
59    pub const fn bcr(&self, n: usize) -> &BCR {
60        #[allow(clippy::no_effect)] [(); 3][n];
61        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(8).add(8 * n).cast() }
62    }
63    ///Iterator for array of:
64    ///0x08..0x14 - SRAM/NOR-Flash chip-select control register %s
65    #[inline(always)]
66    pub fn bcr_iter(&self) -> impl Iterator<Item = &BCR> {
67        (0..3)
68            .map(move |n| unsafe {
69                &*core::ptr::from_ref(self).cast::<u8>().add(8).add(8 * n).cast()
70            })
71    }
72    ///0x08 - SRAM/NOR-Flash chip-select control register 2
73    #[inline(always)]
74    pub const fn bcr2(&self) -> &BCR {
75        self.bcr(0)
76    }
77    ///0x10 - SRAM/NOR-Flash chip-select control register 3
78    #[inline(always)]
79    pub const fn bcr3(&self) -> &BCR {
80        self.bcr(1)
81    }
82    ///0x18 - SRAM/NOR-Flash chip-select control register 4
83    #[inline(always)]
84    pub const fn bcr4(&self) -> &BCR {
85        self.bcr(2)
86    }
87    ///0x104..0x114 - SRAM/NOR-Flash write timing registers %s
88    ///
89    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `BWTR1` register.</div>
90    #[inline(always)]
91    pub const fn bwtr(&self, n: usize) -> &BWTR {
92        #[allow(clippy::no_effect)] [(); 4][n];
93        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(260).add(8 * n).cast() }
94    }
95    ///Iterator for array of:
96    ///0x104..0x114 - SRAM/NOR-Flash write timing registers %s
97    #[inline(always)]
98    pub fn bwtr_iter(&self) -> impl Iterator<Item = &BWTR> {
99        (0..4)
100            .map(move |n| unsafe {
101                &*core::ptr::from_ref(self).cast::<u8>().add(260).add(8 * n).cast()
102            })
103    }
104    ///0x104 - SRAM/NOR-Flash write timing registers 1
105    #[inline(always)]
106    pub const fn bwtr1(&self) -> &BWTR {
107        self.bwtr(0)
108    }
109    ///0x10c - SRAM/NOR-Flash write timing registers 2
110    #[inline(always)]
111    pub const fn bwtr2(&self) -> &BWTR {
112        self.bwtr(1)
113    }
114    ///0x114 - SRAM/NOR-Flash write timing registers 3
115    #[inline(always)]
116    pub const fn bwtr3(&self) -> &BWTR {
117        self.bwtr(2)
118    }
119    ///0x11c - SRAM/NOR-Flash write timing registers 4
120    #[inline(always)]
121    pub const fn bwtr4(&self) -> &BWTR {
122        self.bwtr(3)
123    }
124}
125/**BCR1 (rw) register accessor: SRAM/NOR-Flash chip-select control register 1
126
127You can [`read`](crate::Reg::read) this register and get [`bcr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
128
129See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#FSMC:BCR1)
130
131For information about available fields see [`mod@bcr1`] module*/
132pub type BCR1 = crate::Reg<bcr1::BCR1rs>;
133///SRAM/NOR-Flash chip-select control register 1
134pub mod bcr1;
135/**BTR (rw) register accessor: SRAM/NOR-Flash chip-select timing register %s
136
137You can [`read`](crate::Reg::read) this register and get [`btr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`btr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
138
139See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#FSMC:BTR[1])
140
141For information about available fields see [`mod@btr`] module*/
142pub type BTR = crate::Reg<btr::BTRrs>;
143///SRAM/NOR-Flash chip-select timing register %s
144pub mod btr;
145/**BCR (rw) register accessor: SRAM/NOR-Flash chip-select control register %s
146
147You can [`read`](crate::Reg::read) this register and get [`bcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
148
149See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#FSMC:BCR[2])
150
151For information about available fields see [`mod@bcr`] module*/
152pub type BCR = crate::Reg<bcr::BCRrs>;
153///SRAM/NOR-Flash chip-select control register %s
154pub mod bcr;
155/**BWTR (rw) register accessor: SRAM/NOR-Flash write timing registers %s
156
157You can [`read`](crate::Reg::read) this register and get [`bwtr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bwtr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
158
159See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#FSMC:BWTR[1])
160
161For information about available fields see [`mod@bwtr`] module*/
162pub type BWTR = crate::Reg<bwtr::BWTRrs>;
163///SRAM/NOR-Flash write timing registers %s
164pub mod bwtr;
stm32f1_staging/stm32f100/fsmc.rs

stm32f1_staging/stm32f100/
fsmc.rs
