stm32f1_staging/stm32f107/tim9/
smcr.rs

1///Register `SMCR` reader
2pub type R = crate::R<SMCRrs>;
3///Register `SMCR` writer
4pub type W = crate::W<SMCRrs>;
5///Field `SMS` reader - Slave mode selection
6pub type SMS_R = crate::FieldReader;
7///Field `SMS` writer - Slave mode selection
8pub type SMS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
9///Field `TS` reader - Trigger selection
10pub type TS_R = crate::FieldReader;
11///Field `TS` writer - Trigger selection
12pub type TS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
13///Field `MSM` reader - Master/Slave mode
14pub type MSM_R = crate::BitReader;
15///Field `MSM` writer - Master/Slave mode
16pub type MSM_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    ///Bits 0:2 - Slave mode selection
19    #[inline(always)]
20    pub fn sms(&self) -> SMS_R {
21        SMS_R::new((self.bits & 7) as u8)
22    }
23    ///Bits 4:6 - Trigger selection
24    #[inline(always)]
25    pub fn ts(&self) -> TS_R {
26        TS_R::new(((self.bits >> 4) & 7) as u8)
27    }
28    ///Bit 7 - Master/Slave mode
29    #[inline(always)]
30    pub fn msm(&self) -> MSM_R {
31        MSM_R::new(((self.bits >> 7) & 1) != 0)
32    }
33}
34impl core::fmt::Debug for R {
35    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
36        f.debug_struct("SMCR")
37            .field("msm", &self.msm())
38            .field("ts", &self.ts())
39            .field("sms", &self.sms())
40            .finish()
41    }
42}
43impl W {
44    ///Bits 0:2 - Slave mode selection
45    #[inline(always)]
46    pub fn sms(&mut self) -> SMS_W<SMCRrs> {
47        SMS_W::new(self, 0)
48    }
49    ///Bits 4:6 - Trigger selection
50    #[inline(always)]
51    pub fn ts(&mut self) -> TS_W<SMCRrs> {
52        TS_W::new(self, 4)
53    }
54    ///Bit 7 - Master/Slave mode
55    #[inline(always)]
56    pub fn msm(&mut self) -> MSM_W<SMCRrs> {
57        MSM_W::new(self, 7)
58    }
59}
60/**slave mode control register
61
62You can [`read`](crate::Reg::read) this register and get [`smcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
63
64See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F107.html#TIM9:SMCR)*/
65pub struct SMCRrs;
66impl crate::RegisterSpec for SMCRrs {
67    type Ux = u32;
68}
69///`read()` method returns [`smcr::R`](R) reader structure
70impl crate::Readable for SMCRrs {}
71///`write(|w| ..)` method takes [`smcr::W`](W) writer structure
72impl crate::Writable for SMCRrs {
73    type Safety = crate::Unsafe;
74}
75///`reset()` method sets SMCR to value 0
76impl crate::Resettable for SMCRrs {}
stm32f1_staging/stm32f107/tim9/smcr.rs

stm32f1_staging/stm32f107/tim9/
smcr.rs
