stm32f1_staging/stm32f101/wwdg/
cfr.rs

1///Register `CFR` reader
2pub type R = crate::R<CFRrs>;
3///Register `CFR` writer
4pub type W = crate::W<CFRrs>;
5///Field `W` reader - 7-bit window value
6pub type W_R = crate::FieldReader;
7///Field `W` writer - 7-bit window value
8pub type W_W<'a, REG> = crate::FieldWriter<'a, REG, 7, u8, crate::Safe>;
9/**Timer Base
10
11Value on reset: 0*/
12#[cfg_attr(feature = "defmt", derive(defmt::Format))]
13#[derive(Clone, Copy, Debug, PartialEq, Eq)]
14#[repr(u8)]
15pub enum WDGTB {
16    ///0: Counter clock (PCLK1 div 4096) div 1
17    Div1 = 0,
18    ///1: Counter clock (PCLK1 div 4096) div 2
19    Div2 = 1,
20    ///2: Counter clock (PCLK1 div 4096) div 4
21    Div4 = 2,
22    ///3: Counter clock (PCLK1 div 4096) div 8
23    Div8 = 3,
24}
25impl From<WDGTB> for u8 {
26    #[inline(always)]
27    fn from(variant: WDGTB) -> Self {
28        variant as _
29    }
30}
31impl crate::FieldSpec for WDGTB {
32    type Ux = u8;
33}
34impl crate::IsEnum for WDGTB {}
35///Field `WDGTB` reader - Timer Base
36pub type WDGTB_R = crate::FieldReader<WDGTB>;
37impl WDGTB_R {
38    ///Get enumerated values variant
39    #[inline(always)]
40    pub const fn variant(&self) -> WDGTB {
41        match self.bits {
42            0 => WDGTB::Div1,
43            1 => WDGTB::Div2,
44            2 => WDGTB::Div4,
45            3 => WDGTB::Div8,
46            _ => unreachable!(),
47        }
48    }
49    ///Counter clock (PCLK1 div 4096) div 1
50    #[inline(always)]
51    pub fn is_div1(&self) -> bool {
52        *self == WDGTB::Div1
53    }
54    ///Counter clock (PCLK1 div 4096) div 2
55    #[inline(always)]
56    pub fn is_div2(&self) -> bool {
57        *self == WDGTB::Div2
58    }
59    ///Counter clock (PCLK1 div 4096) div 4
60    #[inline(always)]
61    pub fn is_div4(&self) -> bool {
62        *self == WDGTB::Div4
63    }
64    ///Counter clock (PCLK1 div 4096) div 8
65    #[inline(always)]
66    pub fn is_div8(&self) -> bool {
67        *self == WDGTB::Div8
68    }
69}
70///Field `WDGTB` writer - Timer Base
71pub type WDGTB_W<'a, REG> = crate::FieldWriter<'a, REG, 2, WDGTB, crate::Safe>;
72impl<'a, REG> WDGTB_W<'a, REG>
73where
74    REG: crate::Writable + crate::RegisterSpec,
75    REG::Ux: From<u8>,
76{
77    ///Counter clock (PCLK1 div 4096) div 1
78    #[inline(always)]
79    pub fn div1(self) -> &'a mut crate::W<REG> {
80        self.variant(WDGTB::Div1)
81    }
82    ///Counter clock (PCLK1 div 4096) div 2
83    #[inline(always)]
84    pub fn div2(self) -> &'a mut crate::W<REG> {
85        self.variant(WDGTB::Div2)
86    }
87    ///Counter clock (PCLK1 div 4096) div 4
88    #[inline(always)]
89    pub fn div4(self) -> &'a mut crate::W<REG> {
90        self.variant(WDGTB::Div4)
91    }
92    ///Counter clock (PCLK1 div 4096) div 8
93    #[inline(always)]
94    pub fn div8(self) -> &'a mut crate::W<REG> {
95        self.variant(WDGTB::Div8)
96    }
97}
98/**Early Wakeup Interrupt
99
100Value on reset: 0*/
101#[cfg_attr(feature = "defmt", derive(defmt::Format))]
102#[derive(Clone, Copy, Debug, PartialEq, Eq)]
103pub enum EWIW {
104    ///1: interrupt occurs whenever the counter reaches the value 0x40
105    Enable = 1,
106}
107impl From<EWIW> for bool {
108    #[inline(always)]
109    fn from(variant: EWIW) -> Self {
110        variant as u8 != 0
111    }
112}
113///Field `EWI` reader - Early Wakeup Interrupt
114pub type EWI_R = crate::BitReader<EWIW>;
115impl EWI_R {
116    ///Get enumerated values variant
117    #[inline(always)]
118    pub const fn variant(&self) -> Option<EWIW> {
119        match self.bits {
120            true => Some(EWIW::Enable),
121            _ => None,
122        }
123    }
124    ///interrupt occurs whenever the counter reaches the value 0x40
125    #[inline(always)]
126    pub fn is_enable(&self) -> bool {
127        *self == EWIW::Enable
128    }
129}
130///Field `EWI` writer - Early Wakeup Interrupt
131pub type EWI_W<'a, REG> = crate::BitWriter<'a, REG, EWIW>;
132impl<'a, REG> EWI_W<'a, REG>
133where
134    REG: crate::Writable + crate::RegisterSpec,
135{
136    ///interrupt occurs whenever the counter reaches the value 0x40
137    #[inline(always)]
138    pub fn enable(self) -> &'a mut crate::W<REG> {
139        self.variant(EWIW::Enable)
140    }
141}
142impl R {
143    ///Bits 0:6 - 7-bit window value
144    #[inline(always)]
145    pub fn w(&self) -> W_R {
146        W_R::new((self.bits & 0x7f) as u8)
147    }
148    ///Bits 7:8 - Timer Base
149    #[inline(always)]
150    pub fn wdgtb(&self) -> WDGTB_R {
151        WDGTB_R::new(((self.bits >> 7) & 3) as u8)
152    }
153    ///Bit 9 - Early Wakeup Interrupt
154    #[inline(always)]
155    pub fn ewi(&self) -> EWI_R {
156        EWI_R::new(((self.bits >> 9) & 1) != 0)
157    }
158}
159impl core::fmt::Debug for R {
160    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
161        f.debug_struct("CFR")
162            .field("w", &self.w())
163            .field("wdgtb", &self.wdgtb())
164            .field("ewi", &self.ewi())
165            .finish()
166    }
167}
168impl W {
169    ///Bits 0:6 - 7-bit window value
170    #[inline(always)]
171    pub fn w(&mut self) -> W_W<CFRrs> {
172        W_W::new(self, 0)
173    }
174    ///Bits 7:8 - Timer Base
175    #[inline(always)]
176    pub fn wdgtb(&mut self) -> WDGTB_W<CFRrs> {
177        WDGTB_W::new(self, 7)
178    }
179    ///Bit 9 - Early Wakeup Interrupt
180    #[inline(always)]
181    pub fn ewi(&mut self) -> EWI_W<CFRrs> {
182        EWI_W::new(self, 9)
183    }
184}
185/**Configuration register (WWDG_CFR)
186
187You can [`read`](crate::Reg::read) this register and get [`cfr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
188
189See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#WWDG:CFR)*/
190pub struct CFRrs;
191impl crate::RegisterSpec for CFRrs {
192    type Ux = u16;
193}
194///`read()` method returns [`cfr::R`](R) reader structure
195impl crate::Readable for CFRrs {}
196///`write(|w| ..)` method takes [`cfr::W`](W) writer structure
197impl crate::Writable for CFRrs {
198    type Safety = crate::Unsafe;
199}
200///`reset()` method sets CFR to value 0x7f
201impl crate::Resettable for CFRrs {
202    const RESET_VALUE: u16 = 0x7f;
203}
stm32f1_staging/stm32f101/wwdg/cfr.rs

stm32f1_staging/stm32f101/wwdg/
cfr.rs
