stm32f1_staging/stm32f100/
tim1.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr1: CR1,
6    cr2: CR2,
7    smcr: SMCR,
8    dier: DIER,
9    sr: SR,
10    egr: EGR,
11    _reserved_6_ccmr1: [u8; 0x04],
12    _reserved_7_ccmr2: [u8; 0x04],
13    ccer: CCER,
14    cnt: CNT,
15    psc: PSC,
16    arr: ARR,
17    rcr: RCR,
18    ccr: [CCR; 4],
19    bdtr: BDTR,
20    dcr: DCR,
21    dmar: DMAR,
22}
23impl RegisterBlock {
24    ///0x00 - control register 1
25    #[inline(always)]
26    pub const fn cr1(&self) -> &CR1 {
27        &self.cr1
28    }
29    ///0x04 - control register 2
30    #[inline(always)]
31    pub const fn cr2(&self) -> &CR2 {
32        &self.cr2
33    }
34    ///0x08 - slave mode control register
35    #[inline(always)]
36    pub const fn smcr(&self) -> &SMCR {
37        &self.smcr
38    }
39    ///0x0c - DMA/Interrupt enable register
40    #[inline(always)]
41    pub const fn dier(&self) -> &DIER {
42        &self.dier
43    }
44    ///0x10 - status register
45    #[inline(always)]
46    pub const fn sr(&self) -> &SR {
47        &self.sr
48    }
49    ///0x14 - event generation register
50    #[inline(always)]
51    pub const fn egr(&self) -> &EGR {
52        &self.egr
53    }
54    ///0x18 - capture/compare mode register 1 (input mode)
55    #[inline(always)]
56    pub const fn ccmr1_input(&self) -> &CCMR1_INPUT {
57        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
58    }
59    ///0x18 - capture/compare mode register (output mode)
60    #[inline(always)]
61    pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
62        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
63    }
64    ///0x1c - capture/compare mode register 2 (input mode)
65    #[inline(always)]
66    pub const fn ccmr2_input(&self) -> &CCMR2_INPUT {
67        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
68    }
69    ///0x1c - capture/compare mode register (output mode)
70    #[inline(always)]
71    pub const fn ccmr2_output(&self) -> &CCMR2_OUTPUT {
72        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(28).cast() }
73    }
74    ///0x20 - capture/compare enable register
75    #[inline(always)]
76    pub const fn ccer(&self) -> &CCER {
77        &self.ccer
78    }
79    ///0x24 - counter
80    #[inline(always)]
81    pub const fn cnt(&self) -> &CNT {
82        &self.cnt
83    }
84    ///0x28 - prescaler
85    #[inline(always)]
86    pub const fn psc(&self) -> &PSC {
87        &self.psc
88    }
89    ///0x2c - auto-reload register
90    #[inline(always)]
91    pub const fn arr(&self) -> &ARR {
92        &self.arr
93    }
94    ///0x30 - repetition counter register
95    #[inline(always)]
96    pub const fn rcr(&self) -> &RCR {
97        &self.rcr
98    }
99    ///0x34..0x44 - capture/compare register
100    ///
101    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `CCR1` register.</div>
102    #[inline(always)]
103    pub const fn ccr(&self, n: usize) -> &CCR {
104        &self.ccr[n]
105    }
106    ///Iterator for array of:
107    ///0x34..0x44 - capture/compare register
108    #[inline(always)]
109    pub fn ccr_iter(&self) -> impl Iterator<Item = &CCR> {
110        self.ccr.iter()
111    }
112    ///0x34 - capture/compare register
113    #[inline(always)]
114    pub const fn ccr1(&self) -> &CCR {
115        self.ccr(0)
116    }
117    ///0x38 - capture/compare register
118    #[inline(always)]
119    pub const fn ccr2(&self) -> &CCR {
120        self.ccr(1)
121    }
122    ///0x3c - capture/compare register
123    #[inline(always)]
124    pub const fn ccr3(&self) -> &CCR {
125        self.ccr(2)
126    }
127    ///0x40 - capture/compare register
128    #[inline(always)]
129    pub const fn ccr4(&self) -> &CCR {
130        self.ccr(3)
131    }
132    ///0x44 - break and dead-time register
133    #[inline(always)]
134    pub const fn bdtr(&self) -> &BDTR {
135        &self.bdtr
136    }
137    ///0x48 - DMA control register
138    #[inline(always)]
139    pub const fn dcr(&self) -> &DCR {
140        &self.dcr
141    }
142    ///0x4c - DMA address for full transfer
143    #[inline(always)]
144    pub const fn dmar(&self) -> &DMAR {
145        &self.dmar
146    }
147}
148/**CR1 (rw) register accessor: control register 1
149
150You can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
151
152See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM1:CR1)
153
154For information about available fields see [`mod@cr1`] module*/
155pub type CR1 = crate::Reg<cr1::CR1rs>;
156///control register 1
157pub mod cr1;
158/**CR2 (rw) register accessor: control register 2
159
160You can [`read`](crate::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
161
162See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM1:CR2)
163
164For information about available fields see [`mod@cr2`] module*/
165pub type CR2 = crate::Reg<cr2::CR2rs>;
166///control register 2
167pub mod cr2;
168/**SMCR (rw) register accessor: slave mode control register
169
170You can [`read`](crate::Reg::read) this register and get [`smcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
171
172See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM1:SMCR)
173
174For information about available fields see [`mod@smcr`] module*/
175pub type SMCR = crate::Reg<smcr::SMCRrs>;
176///slave mode control register
177pub mod smcr;
178/**DIER (rw) register accessor: DMA/Interrupt enable register
179
180You can [`read`](crate::Reg::read) this register and get [`dier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
181
182See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM1:DIER)
183
184For information about available fields see [`mod@dier`] module*/
185pub type DIER = crate::Reg<dier::DIERrs>;
186///DMA/Interrupt enable register
187pub mod dier;
188/**SR (rw) register accessor: status register
189
190You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
191
192See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM1:SR)
193
194For information about available fields see [`mod@sr`] module*/
195pub type SR = crate::Reg<sr::SRrs>;
196///status register
197pub mod sr;
198/**EGR (w) register accessor: event generation register
199
200You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
201
202See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM1:EGR)
203
204For information about available fields see [`mod@egr`] module*/
205pub type EGR = crate::Reg<egr::EGRrs>;
206///event generation register
207pub mod egr;
208/**CCMR1_Output (rw) register accessor: capture/compare mode register (output mode)
209
210You can [`read`](crate::Reg::read) this register and get [`ccmr1_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
211
212See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM1:CCMR1_Output)
213
214For information about available fields see [`mod@ccmr1_output`] module*/
215#[doc(alias = "CCMR1_Output")]
216pub type CCMR1_OUTPUT = crate::Reg<ccmr1_output::CCMR1_OUTPUTrs>;
217///capture/compare mode register (output mode)
218pub mod ccmr1_output;
219/**CCMR1_Input (rw) register accessor: capture/compare mode register 1 (input mode)
220
221You can [`read`](crate::Reg::read) this register and get [`ccmr1_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
222
223See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM1:CCMR1_Input)
224
225For information about available fields see [`mod@ccmr1_input`] module*/
226#[doc(alias = "CCMR1_Input")]
227pub type CCMR1_INPUT = crate::Reg<ccmr1_input::CCMR1_INPUTrs>;
228///capture/compare mode register 1 (input mode)
229pub mod ccmr1_input;
230/**CCMR2_Output (rw) register accessor: capture/compare mode register (output mode)
231
232You can [`read`](crate::Reg::read) this register and get [`ccmr2_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr2_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
233
234See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM1:CCMR2_Output)
235
236For information about available fields see [`mod@ccmr2_output`] module*/
237#[doc(alias = "CCMR2_Output")]
238pub type CCMR2_OUTPUT = crate::Reg<ccmr2_output::CCMR2_OUTPUTrs>;
239///capture/compare mode register (output mode)
240pub mod ccmr2_output;
241/**CCMR2_Input (rw) register accessor: capture/compare mode register 2 (input mode)
242
243You can [`read`](crate::Reg::read) this register and get [`ccmr2_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr2_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
244
245See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM1:CCMR2_Input)
246
247For information about available fields see [`mod@ccmr2_input`] module*/
248#[doc(alias = "CCMR2_Input")]
249pub type CCMR2_INPUT = crate::Reg<ccmr2_input::CCMR2_INPUTrs>;
250///capture/compare mode register 2 (input mode)
251pub mod ccmr2_input;
252/**CCER (rw) register accessor: capture/compare enable register
253
254You can [`read`](crate::Reg::read) this register and get [`ccer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
255
256See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM1:CCER)
257
258For information about available fields see [`mod@ccer`] module*/
259pub type CCER = crate::Reg<ccer::CCERrs>;
260///capture/compare enable register
261pub mod ccer;
262/**CNT (rw) register accessor: counter
263
264You can [`read`](crate::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
265
266See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM1:CNT)
267
268For information about available fields see [`mod@cnt`] module*/
269pub type CNT = crate::Reg<cnt::CNTrs>;
270///counter
271pub mod cnt;
272/**PSC (rw) register accessor: prescaler
273
274You can [`read`](crate::Reg::read) this register and get [`psc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
275
276See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM1:PSC)
277
278For information about available fields see [`mod@psc`] module*/
279pub type PSC = crate::Reg<psc::PSCrs>;
280///prescaler
281pub mod psc;
282/**ARR (rw) register accessor: auto-reload register
283
284You can [`read`](crate::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
285
286See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM1:ARR)
287
288For information about available fields see [`mod@arr`] module*/
289pub type ARR = crate::Reg<arr::ARRrs>;
290///auto-reload register
291pub mod arr;
292/**CCR (rw) register accessor: capture/compare register
293
294You can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
295
296See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM1:CCR[1])
297
298For information about available fields see [`mod@ccr`] module*/
299pub type CCR = crate::Reg<ccr::CCRrs>;
300///capture/compare register
301pub mod ccr;
302/**DCR (rw) register accessor: DMA control register
303
304You can [`read`](crate::Reg::read) this register and get [`dcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
305
306See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM1:DCR)
307
308For information about available fields see [`mod@dcr`] module*/
309pub type DCR = crate::Reg<dcr::DCRrs>;
310///DMA control register
311pub mod dcr;
312/**DMAR (rw) register accessor: DMA address for full transfer
313
314You can [`read`](crate::Reg::read) this register and get [`dmar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
315
316See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM1:DMAR)
317
318For information about available fields see [`mod@dmar`] module*/
319pub type DMAR = crate::Reg<dmar::DMARrs>;
320///DMA address for full transfer
321pub mod dmar;
322/**RCR (rw) register accessor: repetition counter register
323
324You can [`read`](crate::Reg::read) this register and get [`rcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
325
326See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM1:RCR)
327
328For information about available fields see [`mod@rcr`] module*/
329pub type RCR = crate::Reg<rcr::RCRrs>;
330///repetition counter register
331pub mod rcr;
332/**BDTR (rw) register accessor: break and dead-time register
333
334You can [`read`](crate::Reg::read) this register and get [`bdtr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdtr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
335
336See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F100.html#TIM1:BDTR)
337
338For information about available fields see [`mod@bdtr`] module*/
339pub type BDTR = crate::Reg<bdtr::BDTRrs>;
340///break and dead-time register
341pub mod bdtr;
stm32f1_staging/stm32f100/tim1.rs

stm32f1_staging/stm32f100/
tim1.rs
