stm32f1_staging/stm32f101/exti/
imr.rs

1///Register `IMR` reader
2pub type R = crate::R<IMRrs>;
3///Register `IMR` writer
4pub type W = crate::W<IMRrs>;
5/**Interrupt Mask on line %s
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum MR0 {
11    ///0: Interrupt request line is masked
12    Masked = 0,
13    ///1: Interrupt request line is unmasked
14    Unmasked = 1,
15}
16impl From<MR0> for bool {
17    #[inline(always)]
18    fn from(variant: MR0) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `MR(0-18)` reader - Interrupt Mask on line %s
23pub type MR_R = crate::BitReader<MR0>;
24impl MR_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> MR0 {
28        match self.bits {
29            false => MR0::Masked,
30            true => MR0::Unmasked,
31        }
32    }
33    ///Interrupt request line is masked
34    #[inline(always)]
35    pub fn is_masked(&self) -> bool {
36        *self == MR0::Masked
37    }
38    ///Interrupt request line is unmasked
39    #[inline(always)]
40    pub fn is_unmasked(&self) -> bool {
41        *self == MR0::Unmasked
42    }
43}
44///Field `MR(0-18)` writer - Interrupt Mask on line %s
45pub type MR_W<'a, REG> = crate::BitWriter<'a, REG, MR0>;
46impl<'a, REG> MR_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Interrupt request line is masked
51    #[inline(always)]
52    pub fn masked(self) -> &'a mut crate::W<REG> {
53        self.variant(MR0::Masked)
54    }
55    ///Interrupt request line is unmasked
56    #[inline(always)]
57    pub fn unmasked(self) -> &'a mut crate::W<REG> {
58        self.variant(MR0::Unmasked)
59    }
60}
61impl R {
62    ///Interrupt Mask on line (0-18)
63    ///
64    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `MR0` field.</div>
65    #[inline(always)]
66    pub fn mr(&self, n: u8) -> MR_R {
67        #[allow(clippy::no_effect)] [(); 19][n as usize];
68        MR_R::new(((self.bits >> n) & 1) != 0)
69    }
70    ///Iterator for array of:
71    ///Interrupt Mask on line (0-18)
72    #[inline(always)]
73    pub fn mr_iter(&self) -> impl Iterator<Item = MR_R> + '_ {
74        (0..19).map(move |n| MR_R::new(((self.bits >> n) & 1) != 0))
75    }
76    ///Bit 0 - Interrupt Mask on line 0
77    #[inline(always)]
78    pub fn mr0(&self) -> MR_R {
79        MR_R::new((self.bits & 1) != 0)
80    }
81    ///Bit 1 - Interrupt Mask on line 1
82    #[inline(always)]
83    pub fn mr1(&self) -> MR_R {
84        MR_R::new(((self.bits >> 1) & 1) != 0)
85    }
86    ///Bit 2 - Interrupt Mask on line 2
87    #[inline(always)]
88    pub fn mr2(&self) -> MR_R {
89        MR_R::new(((self.bits >> 2) & 1) != 0)
90    }
91    ///Bit 3 - Interrupt Mask on line 3
92    #[inline(always)]
93    pub fn mr3(&self) -> MR_R {
94        MR_R::new(((self.bits >> 3) & 1) != 0)
95    }
96    ///Bit 4 - Interrupt Mask on line 4
97    #[inline(always)]
98    pub fn mr4(&self) -> MR_R {
99        MR_R::new(((self.bits >> 4) & 1) != 0)
100    }
101    ///Bit 5 - Interrupt Mask on line 5
102    #[inline(always)]
103    pub fn mr5(&self) -> MR_R {
104        MR_R::new(((self.bits >> 5) & 1) != 0)
105    }
106    ///Bit 6 - Interrupt Mask on line 6
107    #[inline(always)]
108    pub fn mr6(&self) -> MR_R {
109        MR_R::new(((self.bits >> 6) & 1) != 0)
110    }
111    ///Bit 7 - Interrupt Mask on line 7
112    #[inline(always)]
113    pub fn mr7(&self) -> MR_R {
114        MR_R::new(((self.bits >> 7) & 1) != 0)
115    }
116    ///Bit 8 - Interrupt Mask on line 8
117    #[inline(always)]
118    pub fn mr8(&self) -> MR_R {
119        MR_R::new(((self.bits >> 8) & 1) != 0)
120    }
121    ///Bit 9 - Interrupt Mask on line 9
122    #[inline(always)]
123    pub fn mr9(&self) -> MR_R {
124        MR_R::new(((self.bits >> 9) & 1) != 0)
125    }
126    ///Bit 10 - Interrupt Mask on line 10
127    #[inline(always)]
128    pub fn mr10(&self) -> MR_R {
129        MR_R::new(((self.bits >> 10) & 1) != 0)
130    }
131    ///Bit 11 - Interrupt Mask on line 11
132    #[inline(always)]
133    pub fn mr11(&self) -> MR_R {
134        MR_R::new(((self.bits >> 11) & 1) != 0)
135    }
136    ///Bit 12 - Interrupt Mask on line 12
137    #[inline(always)]
138    pub fn mr12(&self) -> MR_R {
139        MR_R::new(((self.bits >> 12) & 1) != 0)
140    }
141    ///Bit 13 - Interrupt Mask on line 13
142    #[inline(always)]
143    pub fn mr13(&self) -> MR_R {
144        MR_R::new(((self.bits >> 13) & 1) != 0)
145    }
146    ///Bit 14 - Interrupt Mask on line 14
147    #[inline(always)]
148    pub fn mr14(&self) -> MR_R {
149        MR_R::new(((self.bits >> 14) & 1) != 0)
150    }
151    ///Bit 15 - Interrupt Mask on line 15
152    #[inline(always)]
153    pub fn mr15(&self) -> MR_R {
154        MR_R::new(((self.bits >> 15) & 1) != 0)
155    }
156    ///Bit 16 - Interrupt Mask on line 16
157    #[inline(always)]
158    pub fn mr16(&self) -> MR_R {
159        MR_R::new(((self.bits >> 16) & 1) != 0)
160    }
161    ///Bit 17 - Interrupt Mask on line 17
162    #[inline(always)]
163    pub fn mr17(&self) -> MR_R {
164        MR_R::new(((self.bits >> 17) & 1) != 0)
165    }
166    ///Bit 18 - Interrupt Mask on line 18
167    #[inline(always)]
168    pub fn mr18(&self) -> MR_R {
169        MR_R::new(((self.bits >> 18) & 1) != 0)
170    }
171}
172impl core::fmt::Debug for R {
173    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
174        f.debug_struct("IMR")
175            .field("mr0", &self.mr0())
176            .field("mr1", &self.mr1())
177            .field("mr2", &self.mr2())
178            .field("mr3", &self.mr3())
179            .field("mr4", &self.mr4())
180            .field("mr5", &self.mr5())
181            .field("mr6", &self.mr6())
182            .field("mr7", &self.mr7())
183            .field("mr8", &self.mr8())
184            .field("mr9", &self.mr9())
185            .field("mr10", &self.mr10())
186            .field("mr11", &self.mr11())
187            .field("mr12", &self.mr12())
188            .field("mr13", &self.mr13())
189            .field("mr14", &self.mr14())
190            .field("mr15", &self.mr15())
191            .field("mr16", &self.mr16())
192            .field("mr17", &self.mr17())
193            .field("mr18", &self.mr18())
194            .finish()
195    }
196}
197impl W {
198    ///Interrupt Mask on line (0-18)
199    ///
200    ///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `MR0` field.</div>
201    #[inline(always)]
202    pub fn mr(&mut self, n: u8) -> MR_W<IMRrs> {
203        #[allow(clippy::no_effect)] [(); 19][n as usize];
204        MR_W::new(self, n)
205    }
206    ///Bit 0 - Interrupt Mask on line 0
207    #[inline(always)]
208    pub fn mr0(&mut self) -> MR_W<IMRrs> {
209        MR_W::new(self, 0)
210    }
211    ///Bit 1 - Interrupt Mask on line 1
212    #[inline(always)]
213    pub fn mr1(&mut self) -> MR_W<IMRrs> {
214        MR_W::new(self, 1)
215    }
216    ///Bit 2 - Interrupt Mask on line 2
217    #[inline(always)]
218    pub fn mr2(&mut self) -> MR_W<IMRrs> {
219        MR_W::new(self, 2)
220    }
221    ///Bit 3 - Interrupt Mask on line 3
222    #[inline(always)]
223    pub fn mr3(&mut self) -> MR_W<IMRrs> {
224        MR_W::new(self, 3)
225    }
226    ///Bit 4 - Interrupt Mask on line 4
227    #[inline(always)]
228    pub fn mr4(&mut self) -> MR_W<IMRrs> {
229        MR_W::new(self, 4)
230    }
231    ///Bit 5 - Interrupt Mask on line 5
232    #[inline(always)]
233    pub fn mr5(&mut self) -> MR_W<IMRrs> {
234        MR_W::new(self, 5)
235    }
236    ///Bit 6 - Interrupt Mask on line 6
237    #[inline(always)]
238    pub fn mr6(&mut self) -> MR_W<IMRrs> {
239        MR_W::new(self, 6)
240    }
241    ///Bit 7 - Interrupt Mask on line 7
242    #[inline(always)]
243    pub fn mr7(&mut self) -> MR_W<IMRrs> {
244        MR_W::new(self, 7)
245    }
246    ///Bit 8 - Interrupt Mask on line 8
247    #[inline(always)]
248    pub fn mr8(&mut self) -> MR_W<IMRrs> {
249        MR_W::new(self, 8)
250    }
251    ///Bit 9 - Interrupt Mask on line 9
252    #[inline(always)]
253    pub fn mr9(&mut self) -> MR_W<IMRrs> {
254        MR_W::new(self, 9)
255    }
256    ///Bit 10 - Interrupt Mask on line 10
257    #[inline(always)]
258    pub fn mr10(&mut self) -> MR_W<IMRrs> {
259        MR_W::new(self, 10)
260    }
261    ///Bit 11 - Interrupt Mask on line 11
262    #[inline(always)]
263    pub fn mr11(&mut self) -> MR_W<IMRrs> {
264        MR_W::new(self, 11)
265    }
266    ///Bit 12 - Interrupt Mask on line 12
267    #[inline(always)]
268    pub fn mr12(&mut self) -> MR_W<IMRrs> {
269        MR_W::new(self, 12)
270    }
271    ///Bit 13 - Interrupt Mask on line 13
272    #[inline(always)]
273    pub fn mr13(&mut self) -> MR_W<IMRrs> {
274        MR_W::new(self, 13)
275    }
276    ///Bit 14 - Interrupt Mask on line 14
277    #[inline(always)]
278    pub fn mr14(&mut self) -> MR_W<IMRrs> {
279        MR_W::new(self, 14)
280    }
281    ///Bit 15 - Interrupt Mask on line 15
282    #[inline(always)]
283    pub fn mr15(&mut self) -> MR_W<IMRrs> {
284        MR_W::new(self, 15)
285    }
286    ///Bit 16 - Interrupt Mask on line 16
287    #[inline(always)]
288    pub fn mr16(&mut self) -> MR_W<IMRrs> {
289        MR_W::new(self, 16)
290    }
291    ///Bit 17 - Interrupt Mask on line 17
292    #[inline(always)]
293    pub fn mr17(&mut self) -> MR_W<IMRrs> {
294        MR_W::new(self, 17)
295    }
296    ///Bit 18 - Interrupt Mask on line 18
297    #[inline(always)]
298    pub fn mr18(&mut self) -> MR_W<IMRrs> {
299        MR_W::new(self, 18)
300    }
301}
302/**Interrupt mask register (EXTI_IMR)
303
304You can [`read`](crate::Reg::read) this register and get [`imr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`imr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
305
306See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F101.html#EXTI:IMR)*/
307pub struct IMRrs;
308impl crate::RegisterSpec for IMRrs {
309    type Ux = u32;
310}
311///`read()` method returns [`imr::R`](R) reader structure
312impl crate::Readable for IMRrs {}
313///`write(|w| ..)` method takes [`imr::W`](W) writer structure
314impl crate::Writable for IMRrs {
315    type Safety = crate::Unsafe;
316    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
317    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
318}
319///`reset()` method sets IMR to value 0
320impl crate::Resettable for IMRrs {
321    const RESET_VALUE: u32 = 0;
322}
stm32f1_staging/stm32f101/exti/imr.rs

stm32f1_staging/stm32f101/exti/
imr.rs
