stm32f1_staging/stm32f103/tim9/sr.rs
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///Register `SR` reader
pub type R = crate::R<SRrs>;
///Register `SR` writer
pub type W = crate::W<SRrs>;
/**Update interrupt flag
Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum UIFR {
///0: No update occurred
NoUpdateOccurred = 0,
///1: Update interrupt pending
UpdatePending = 1,
}
impl From<UIFR> for bool {
#[inline(always)]
fn from(variant: UIFR) -> Self {
variant as u8 != 0
}
}
///Field `UIF` reader - Update interrupt flag
pub type UIF_R = crate::BitReader<UIFR>;
impl UIF_R {
///Get enumerated values variant
#[inline(always)]
pub const fn variant(&self) -> UIFR {
match self.bits {
false => UIFR::NoUpdateOccurred,
true => UIFR::UpdatePending,
}
}
///No update occurred
#[inline(always)]
pub fn is_no_update_occurred(&self) -> bool {
*self == UIFR::NoUpdateOccurred
}
///Update interrupt pending
#[inline(always)]
pub fn is_update_pending(&self) -> bool {
*self == UIFR::UpdatePending
}
}
/**Update interrupt flag
Value on reset: 0*/
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum UIFW {
///0: Clear flag
Clear = 0,
}
impl From<UIFW> for bool {
#[inline(always)]
fn from(variant: UIFW) -> Self {
variant as u8 != 0
}
}
///Field `UIF` writer - Update interrupt flag
pub type UIF_W<'a, REG> = crate::BitWriter0C<'a, REG, UIFW>;
impl<'a, REG> UIF_W<'a, REG>
where
REG: crate::Writable + crate::RegisterSpec,
{
///Clear flag
#[inline(always)]
pub fn clear(self) -> &'a mut crate::W<REG> {
self.variant(UIFW::Clear)
}
}
///Field `CCIF(1-2)` reader - Capture/compare %s interrupt flag
pub type CCIF_R = crate::BitReader;
///Field `CCIF(1-2)` writer - Capture/compare %s interrupt flag
pub type CCIF_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `TIF` reader - Trigger interrupt flag
pub type TIF_R = crate::BitReader;
///Field `TIF` writer - Trigger interrupt flag
pub type TIF_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `CCOF(1-2)` reader - Capture/Compare %s overcapture flag
pub type CCOF_R = crate::BitReader;
///Field `CCOF(1-2)` writer - Capture/Compare %s overcapture flag
pub type CCOF_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
///Bit 0 - Update interrupt flag
#[inline(always)]
pub fn uif(&self) -> UIF_R {
UIF_R::new((self.bits & 1) != 0)
}
///Capture/compare (1-2) interrupt flag
///
///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1IF` field.</div>
#[inline(always)]
pub fn ccif(&self, n: u8) -> CCIF_R {
#[allow(clippy::no_effect)]
[(); 2][n as usize];
CCIF_R::new(((self.bits >> (n + 1)) & 1) != 0)
}
///Iterator for array of:
///Capture/compare (1-2) interrupt flag
#[inline(always)]
pub fn ccif_iter(&self) -> impl Iterator<Item = CCIF_R> + '_ {
(0..2).map(move |n| CCIF_R::new(((self.bits >> (n + 1)) & 1) != 0))
}
///Bit 1 - Capture/compare 1 interrupt flag
#[inline(always)]
pub fn cc1if(&self) -> CCIF_R {
CCIF_R::new(((self.bits >> 1) & 1) != 0)
}
///Bit 2 - Capture/compare 2 interrupt flag
#[inline(always)]
pub fn cc2if(&self) -> CCIF_R {
CCIF_R::new(((self.bits >> 2) & 1) != 0)
}
///Bit 6 - Trigger interrupt flag
#[inline(always)]
pub fn tif(&self) -> TIF_R {
TIF_R::new(((self.bits >> 6) & 1) != 0)
}
///Capture/Compare (1-2) overcapture flag
///
///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1OF` field.</div>
#[inline(always)]
pub fn ccof(&self, n: u8) -> CCOF_R {
#[allow(clippy::no_effect)]
[(); 2][n as usize];
CCOF_R::new(((self.bits >> (n + 9)) & 1) != 0)
}
///Iterator for array of:
///Capture/Compare (1-2) overcapture flag
#[inline(always)]
pub fn ccof_iter(&self) -> impl Iterator<Item = CCOF_R> + '_ {
(0..2).map(move |n| CCOF_R::new(((self.bits >> (n + 9)) & 1) != 0))
}
///Bit 9 - Capture/Compare 1 overcapture flag
#[inline(always)]
pub fn cc1of(&self) -> CCOF_R {
CCOF_R::new(((self.bits >> 9) & 1) != 0)
}
///Bit 10 - Capture/Compare 2 overcapture flag
#[inline(always)]
pub fn cc2of(&self) -> CCOF_R {
CCOF_R::new(((self.bits >> 10) & 1) != 0)
}
}
impl core::fmt::Debug for R {
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
f.debug_struct("SR")
.field("cc1of", &self.cc1of())
.field("cc2of", &self.cc2of())
.field("tif", &self.tif())
.field("cc1if", &self.cc1if())
.field("cc2if", &self.cc2if())
.field("uif", &self.uif())
.finish()
}
}
impl W {
///Bit 0 - Update interrupt flag
#[inline(always)]
#[must_use]
pub fn uif(&mut self) -> UIF_W<SRrs> {
UIF_W::new(self, 0)
}
///Capture/compare (1-2) interrupt flag
///
///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1IF` field.</div>
#[inline(always)]
#[must_use]
pub fn ccif(&mut self, n: u8) -> CCIF_W<SRrs> {
#[allow(clippy::no_effect)]
[(); 2][n as usize];
CCIF_W::new(self, n + 1)
}
///Bit 1 - Capture/compare 1 interrupt flag
#[inline(always)]
#[must_use]
pub fn cc1if(&mut self) -> CCIF_W<SRrs> {
CCIF_W::new(self, 1)
}
///Bit 2 - Capture/compare 2 interrupt flag
#[inline(always)]
#[must_use]
pub fn cc2if(&mut self) -> CCIF_W<SRrs> {
CCIF_W::new(self, 2)
}
///Bit 6 - Trigger interrupt flag
#[inline(always)]
#[must_use]
pub fn tif(&mut self) -> TIF_W<SRrs> {
TIF_W::new(self, 6)
}
///Capture/Compare (1-2) overcapture flag
///
///<div class="warning">`n` is number of field in register. `n == 0` corresponds to `CC1OF` field.</div>
#[inline(always)]
#[must_use]
pub fn ccof(&mut self, n: u8) -> CCOF_W<SRrs> {
#[allow(clippy::no_effect)]
[(); 2][n as usize];
CCOF_W::new(self, n + 9)
}
///Bit 9 - Capture/Compare 1 overcapture flag
#[inline(always)]
#[must_use]
pub fn cc1of(&mut self) -> CCOF_W<SRrs> {
CCOF_W::new(self, 9)
}
///Bit 10 - Capture/Compare 2 overcapture flag
#[inline(always)]
#[must_use]
pub fn cc2of(&mut self) -> CCOF_W<SRrs> {
CCOF_W::new(self, 10)
}
}
/**status register
You can [`read`](crate::Reg::read) this register and get [`sr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#TIM9:SR)*/
pub struct SRrs;
impl crate::RegisterSpec for SRrs {
type Ux = u32;
}
///`read()` method returns [`sr::R`](R) reader structure
impl crate::Readable for SRrs {}
///`write(|w| ..)` method takes [`sr::W`](W) writer structure
impl crate::Writable for SRrs {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
///`reset()` method sets SR to value 0
impl crate::Resettable for SRrs {
const RESET_VALUE: u32 = 0;
}