stm32f1_staging/stm32f103/sdio/
clkcr.rs

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
///Register `CLKCR` reader
pub type R = crate::R<CLKCRrs>;
///Register `CLKCR` writer
pub type W = crate::W<CLKCRrs>;
///Field `CLKDIV` reader - Clock divide factor
pub type CLKDIV_R = crate::FieldReader;
///Field `CLKDIV` writer - Clock divide factor
pub type CLKDIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
///Field `CLKEN` reader - Clock enable bit
pub type CLKEN_R = crate::BitReader;
///Field `CLKEN` writer - Clock enable bit
pub type CLKEN_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `PWRSAV` reader - Power saving configuration bit
pub type PWRSAV_R = crate::BitReader;
///Field `PWRSAV` writer - Power saving configuration bit
pub type PWRSAV_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `BYPASS` reader - Clock divider bypass enable bit
pub type BYPASS_R = crate::BitReader;
///Field `BYPASS` writer - Clock divider bypass enable bit
pub type BYPASS_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `WIDBUS` reader - Wide bus mode enable bit
pub type WIDBUS_R = crate::FieldReader;
///Field `WIDBUS` writer - Wide bus mode enable bit
pub type WIDBUS_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
///Field `NEGEDGE` reader - SDIO_CK dephasing selection bit
pub type NEGEDGE_R = crate::BitReader;
///Field `NEGEDGE` writer - SDIO_CK dephasing selection bit
pub type NEGEDGE_W<'a, REG> = crate::BitWriter<'a, REG>;
///Field `HWFC_EN` reader - HW Flow Control enable
pub type HWFC_EN_R = crate::BitReader;
///Field `HWFC_EN` writer - HW Flow Control enable
pub type HWFC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    ///Bits 0:7 - Clock divide factor
    #[inline(always)]
    pub fn clkdiv(&self) -> CLKDIV_R {
        CLKDIV_R::new((self.bits & 0xff) as u8)
    }
    ///Bit 8 - Clock enable bit
    #[inline(always)]
    pub fn clken(&self) -> CLKEN_R {
        CLKEN_R::new(((self.bits >> 8) & 1) != 0)
    }
    ///Bit 9 - Power saving configuration bit
    #[inline(always)]
    pub fn pwrsav(&self) -> PWRSAV_R {
        PWRSAV_R::new(((self.bits >> 9) & 1) != 0)
    }
    ///Bit 10 - Clock divider bypass enable bit
    #[inline(always)]
    pub fn bypass(&self) -> BYPASS_R {
        BYPASS_R::new(((self.bits >> 10) & 1) != 0)
    }
    ///Bits 11:12 - Wide bus mode enable bit
    #[inline(always)]
    pub fn widbus(&self) -> WIDBUS_R {
        WIDBUS_R::new(((self.bits >> 11) & 3) as u8)
    }
    ///Bit 13 - SDIO_CK dephasing selection bit
    #[inline(always)]
    pub fn negedge(&self) -> NEGEDGE_R {
        NEGEDGE_R::new(((self.bits >> 13) & 1) != 0)
    }
    ///Bit 14 - HW Flow Control enable
    #[inline(always)]
    pub fn hwfc_en(&self) -> HWFC_EN_R {
        HWFC_EN_R::new(((self.bits >> 14) & 1) != 0)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("CLKCR")
            .field("clkdiv", &self.clkdiv())
            .field("clken", &self.clken())
            .field("pwrsav", &self.pwrsav())
            .field("bypass", &self.bypass())
            .field("widbus", &self.widbus())
            .field("negedge", &self.negedge())
            .field("hwfc_en", &self.hwfc_en())
            .finish()
    }
}
impl W {
    ///Bits 0:7 - Clock divide factor
    #[inline(always)]
    #[must_use]
    pub fn clkdiv(&mut self) -> CLKDIV_W<CLKCRrs> {
        CLKDIV_W::new(self, 0)
    }
    ///Bit 8 - Clock enable bit
    #[inline(always)]
    #[must_use]
    pub fn clken(&mut self) -> CLKEN_W<CLKCRrs> {
        CLKEN_W::new(self, 8)
    }
    ///Bit 9 - Power saving configuration bit
    #[inline(always)]
    #[must_use]
    pub fn pwrsav(&mut self) -> PWRSAV_W<CLKCRrs> {
        PWRSAV_W::new(self, 9)
    }
    ///Bit 10 - Clock divider bypass enable bit
    #[inline(always)]
    #[must_use]
    pub fn bypass(&mut self) -> BYPASS_W<CLKCRrs> {
        BYPASS_W::new(self, 10)
    }
    ///Bits 11:12 - Wide bus mode enable bit
    #[inline(always)]
    #[must_use]
    pub fn widbus(&mut self) -> WIDBUS_W<CLKCRrs> {
        WIDBUS_W::new(self, 11)
    }
    ///Bit 13 - SDIO_CK dephasing selection bit
    #[inline(always)]
    #[must_use]
    pub fn negedge(&mut self) -> NEGEDGE_W<CLKCRrs> {
        NEGEDGE_W::new(self, 13)
    }
    ///Bit 14 - HW Flow Control enable
    #[inline(always)]
    #[must_use]
    pub fn hwfc_en(&mut self) -> HWFC_EN_W<CLKCRrs> {
        HWFC_EN_W::new(self, 14)
    }
}
/**SDI clock control register (SDIO_CLKCR)

You can [`read`](crate::Reg::read) this register and get [`clkcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#SDIO:CLKCR)*/
pub struct CLKCRrs;
impl crate::RegisterSpec for CLKCRrs {
    type Ux = u32;
}
///`read()` method returns [`clkcr::R`](R) reader structure
impl crate::Readable for CLKCRrs {}
///`write(|w| ..)` method takes [`clkcr::W`](W) writer structure
impl crate::Writable for CLKCRrs {
    type Safety = crate::Unsafe;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
///`reset()` method sets CLKCR to value 0
impl crate::Resettable for CLKCRrs {
    const RESET_VALUE: u32 = 0;
}