stm32f1_staging/stm32f103/adc3/
sqr3.rs

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///Register `SQR3` reader
pub type R = crate::R<SQR3rs>;
///Register `SQR3` writer
pub type W = crate::W<SQR3rs>;
///Field `SQ1` reader - 1st conversion in regular sequence
pub type SQ1_R = crate::FieldReader;
///Field `SQ1` writer - 1st conversion in regular sequence
pub type SQ1_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
///Field `SQ2` reader - 2nd conversion in regular sequence
pub type SQ2_R = crate::FieldReader;
///Field `SQ2` writer - 2nd conversion in regular sequence
pub type SQ2_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
///Field `SQ3` reader - 3rd conversion in regular sequence
pub type SQ3_R = crate::FieldReader;
///Field `SQ3` writer - 3rd conversion in regular sequence
pub type SQ3_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
///Field `SQ4` reader - 4th conversion in regular sequence
pub type SQ4_R = crate::FieldReader;
///Field `SQ4` writer - 4th conversion in regular sequence
pub type SQ4_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
///Field `SQ5` reader - 5th conversion in regular sequence
pub type SQ5_R = crate::FieldReader;
///Field `SQ5` writer - 5th conversion in regular sequence
pub type SQ5_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
///Field `SQ6` reader - 6th conversion in regular sequence
pub type SQ6_R = crate::FieldReader;
///Field `SQ6` writer - 6th conversion in regular sequence
pub type SQ6_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
impl R {
    ///Bits 0:4 - 1st conversion in regular sequence
    #[inline(always)]
    pub fn sq1(&self) -> SQ1_R {
        SQ1_R::new((self.bits & 0x1f) as u8)
    }
    ///Bits 5:9 - 2nd conversion in regular sequence
    #[inline(always)]
    pub fn sq2(&self) -> SQ2_R {
        SQ2_R::new(((self.bits >> 5) & 0x1f) as u8)
    }
    ///Bits 10:14 - 3rd conversion in regular sequence
    #[inline(always)]
    pub fn sq3(&self) -> SQ3_R {
        SQ3_R::new(((self.bits >> 10) & 0x1f) as u8)
    }
    ///Bits 15:19 - 4th conversion in regular sequence
    #[inline(always)]
    pub fn sq4(&self) -> SQ4_R {
        SQ4_R::new(((self.bits >> 15) & 0x1f) as u8)
    }
    ///Bits 20:24 - 5th conversion in regular sequence
    #[inline(always)]
    pub fn sq5(&self) -> SQ5_R {
        SQ5_R::new(((self.bits >> 20) & 0x1f) as u8)
    }
    ///Bits 25:29 - 6th conversion in regular sequence
    #[inline(always)]
    pub fn sq6(&self) -> SQ6_R {
        SQ6_R::new(((self.bits >> 25) & 0x1f) as u8)
    }
}
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SQR3")
            .field("sq6", &self.sq6())
            .field("sq5", &self.sq5())
            .field("sq4", &self.sq4())
            .field("sq3", &self.sq3())
            .field("sq2", &self.sq2())
            .field("sq1", &self.sq1())
            .finish()
    }
}
impl W {
    ///Bits 0:4 - 1st conversion in regular sequence
    #[inline(always)]
    #[must_use]
    pub fn sq1(&mut self) -> SQ1_W<SQR3rs> {
        SQ1_W::new(self, 0)
    }
    ///Bits 5:9 - 2nd conversion in regular sequence
    #[inline(always)]
    #[must_use]
    pub fn sq2(&mut self) -> SQ2_W<SQR3rs> {
        SQ2_W::new(self, 5)
    }
    ///Bits 10:14 - 3rd conversion in regular sequence
    #[inline(always)]
    #[must_use]
    pub fn sq3(&mut self) -> SQ3_W<SQR3rs> {
        SQ3_W::new(self, 10)
    }
    ///Bits 15:19 - 4th conversion in regular sequence
    #[inline(always)]
    #[must_use]
    pub fn sq4(&mut self) -> SQ4_W<SQR3rs> {
        SQ4_W::new(self, 15)
    }
    ///Bits 20:24 - 5th conversion in regular sequence
    #[inline(always)]
    #[must_use]
    pub fn sq5(&mut self) -> SQ5_W<SQR3rs> {
        SQ5_W::new(self, 20)
    }
    ///Bits 25:29 - 6th conversion in regular sequence
    #[inline(always)]
    #[must_use]
    pub fn sq6(&mut self) -> SQ6_W<SQR3rs> {
        SQ6_W::new(self, 25)
    }
}
/**regular sequence register 3

You can [`read`](crate::Reg::read) this register and get [`sqr3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sqr3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).

See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F103.html#ADC3:SQR3)*/
pub struct SQR3rs;
impl crate::RegisterSpec for SQR3rs {
    type Ux = u32;
}
///`read()` method returns [`sqr3::R`](R) reader structure
impl crate::Readable for SQR3rs {}
///`write(|w| ..)` method takes [`sqr3::W`](W) writer structure
impl crate::Writable for SQR3rs {
    type Safety = crate::Unsafe;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
///`reset()` method sets SQR3 to value 0
impl crate::Resettable for SQR3rs {
    const RESET_VALUE: u32 = 0;
}