stm32f1_hal/timer/
timer6.rs

1type TimerX = pac::TIM6;
2type Width = u16;
3
4// Do NOT manually modify the code between begin and end!
5// It's synced by scripts/sync_code.py.
6// sync begin
7
8use super::*;
9use crate::{Mcu, pac};
10
11impl Instance for TimerX {}
12
13impl TimerInit<TimerX> for TimerX {
14    fn constrain(self, mcu: &mut Mcu) -> Timer<TimerX> {
15        Timer::new(self, mcu)
16    }
17}
18
19impl GeneralTimer for TimerX {
20    #[inline(always)]
21    fn reset_config(&mut self) {
22        self.cr1().reset();
23    }
24
25    #[inline(always)]
26    fn enable_counter(&mut self) {
27        self.cr1().modify(|_, w| w.cen().set_bit());
28    }
29
30    #[inline(always)]
31    fn disable_counter(&mut self) {
32        self.cr1().modify(|_, w| w.cen().clear_bit());
33    }
34
35    #[inline(always)]
36    fn is_counter_enabled(&self) -> bool {
37        self.cr1().read().cen().is_enabled()
38    }
39
40    #[inline(always)]
41    fn reset_counter(&mut self) {
42        self.cnt().reset();
43    }
44
45    #[inline(always)]
46    fn max_auto_reload() -> u32 {
47        Width::MAX as u32
48    }
49
50    #[inline(always)]
51    unsafe fn set_auto_reload_unchecked(&mut self, arr: u32) {
52        unsafe {
53            self.arr().write(|w| w.bits(arr));
54        }
55    }
56
57    #[inline(always)]
58    fn set_auto_reload(&mut self, arr: u32) -> Result<(), Error> {
59        // Note: Make it impossible to set the ARR value to 0, since this
60        // would cause an infinite loop.
61        if arr > 0 && arr <= Self::max_auto_reload() {
62            unsafe { self.set_auto_reload_unchecked(arr) }
63            Ok(())
64        } else {
65            Err(Error::WrongAutoReload)
66        }
67    }
68
69    #[inline(always)]
70    fn read_auto_reload(&self) -> u32 {
71        self.arr().read().bits()
72    }
73
74    #[inline(always)]
75    fn set_prescaler(&mut self, psc: u16) {
76        self.psc().write(|w| w.psc().set(psc));
77    }
78
79    #[inline(always)]
80    fn read_prescaler(&self) -> u16 {
81        self.psc().read().psc().bits()
82    }
83
84    #[inline(always)]
85    fn read_count(&self) -> u32 {
86        self.cnt().read().bits()
87    }
88
89    #[inline(always)]
90    fn trigger_update(&mut self) {
91        // Sets the URS bit to prevent an interrupt from being triggered by
92        // the UG bit
93        self.cr1().modify(|_, w| w.urs().set_bit());
94        self.egr().write(|w| w.ug().set_bit());
95        self.cr1().modify(|_, w| w.urs().clear_bit());
96    }
97
98    #[inline]
99    fn config_freq(&mut self, clock: Hertz, update_freq: Hertz) {
100        let (prescaler, arr) = compute_prescaler_arr(clock.raw(), update_freq.raw());
101        self.set_prescaler(prescaler as u16);
102        self.set_auto_reload(arr).unwrap();
103        // Trigger update event to load the registers
104        self.trigger_update();
105    }
106
107    #[inline(always)]
108    fn clear_interrupt_flag(&mut self, event: Event) {
109        self.sr()
110            .write(|w| unsafe { w.bits(0xffff & !event.bits()) });
111    }
112
113    #[inline(always)]
114    fn listen_interrupt(&mut self, event: Event, b: bool) {
115        self.dier().modify(|r, w| unsafe {
116            w.bits(if b {
117                r.bits() | event.bits()
118            } else {
119                r.bits() & !event.bits()
120            })
121        });
122    }
123
124    #[inline(always)]
125    fn get_interrupt_flag(&self) -> Event {
126        Event::from_bits_truncate(self.sr().read().bits())
127    }
128
129    #[inline(always)]
130    fn start_one_pulse(&mut self) {
131        self.cr1().modify(|_, w| w.opm().set_bit().cen().set_bit());
132    }
133
134    #[inline(always)]
135    fn stop_in_debug(&mut self, state: bool) {
136        let dbg = unsafe { DBG::steal() };
137        // sync dbg_t6
138        dbg.cr().modify(|_, w| w.dbg_tim6_stop().bit(state));
139        // sync dbg_end
140    }
141
142    #[inline(always)]
143    fn enable_preload(&mut self, b: bool) {
144        self.cr1().modify(|_, w| w.arpe().bit(b));
145    }
146}
147
148// sync master
149impl MasterTimer for TimerX {
150    #[inline(always)]
151    fn master_mode(&mut self, mode: MasterMode) {
152        self.cr2().modify(|_, w| w.mms().variant(mode.into()));
153    }
154}
155
156// sync end
157
158use pac::tim6::cr2::MMS;
159impl From<MasterMode> for MMS {
160    fn from(value: MasterMode) -> Self {
161        match value {
162            MasterMode::Reset => MMS::Reset,
163            MasterMode::Enable => MMS::Enable,
164            MasterMode::Update => MMS::Update,
165            _ => panic!(),
166        }
167    }
168}
stm32f1_hal/timer/timer6.rs

stm32f1_hal/timer/
timer6.rs
