stm32f1_hal/common/timer/
mod.rs

1pub mod pwm;
2pub use pwm::*;
3pub mod counter;
4pub use counter::*;
5pub mod fix_timer;
6pub use fix_timer::*;
7pub mod delay;
8pub use delay::*;
9
10use fugit::HertzU32 as Hertz;
11
12pub trait PwmChannel: embedded_hal::pwm::SetDutyCycle {
13    fn config(&mut self, mode: PwmMode, polarity: PwmPolarity);
14    fn set_enable(&mut self, en: bool);
15}
16
17// ----------------------------------------------------------------------------
18
19pub trait GeneralTimer {
20    fn reset_config(&mut self);
21    fn enable_counter(&mut self);
22    fn disable_counter(&mut self);
23    fn is_counter_enabled(&self) -> bool;
24    fn reset_counter(&mut self);
25    fn enable_preload(&mut self, b: bool);
26    fn max_auto_reload() -> u32;
27    /// # Safety
28    ///
29    /// `arr` must be greater than 0
30    unsafe fn set_auto_reload_unchecked(&mut self, arr: u32);
31    fn set_auto_reload(&mut self, arr: u32) -> Result<(), Error>;
32    fn read_auto_reload(&self) -> u32;
33    fn set_prescaler(&mut self, psc: u16);
34    fn read_prescaler(&self) -> u16;
35    fn read_count(&self) -> u32;
36    fn trigger_update(&mut self);
37    fn stop_in_debug(&mut self, state: bool);
38    fn config_freq(&mut self, clock: Hertz, update_freq: Hertz);
39
40    fn clear_interrupt_flag(&mut self, event: Event);
41    fn listen_interrupt(&mut self, event: Event, b: bool);
42    fn get_interrupt_flag(&self) -> Event;
43    fn start_one_pulse(&mut self);
44}
45
46pub trait TimerDirection: GeneralTimer {
47    fn set_count_direction(&mut self, dir: CountDirection);
48}
49
50pub trait MasterTimer: GeneralTimer {
51    fn master_mode(&mut self, mode: MasterMode);
52}
53
54pub trait TimerWithPwm: GeneralTimer {
55    fn start_pwm(&mut self);
56    fn stop_pwm(&mut self);
57
58    fn preload_output_channel_in_mode(&mut self, channel: Channel, mode: PwmMode);
59    fn set_polarity(&mut self, channel: Channel, polarity: PwmPolarity);
60}
61
62pub trait TimerWithPwm1Ch: TimerWithPwm {
63    fn enable_ch1(&mut self, en: bool);
64    fn set_ch1_cc_value(&mut self, value: u32);
65    fn get_ch1_cc_value(&self) -> u32;
66}
67
68pub trait TimerWithPwm2Ch: TimerWithPwm1Ch {
69    fn enable_ch2(&mut self, en: bool);
70    fn set_ch2_cc_value(&mut self, value: u32);
71    fn get_ch2_cc_value(&self) -> u32;
72}
73
74pub trait TimerWithPwm3Ch: TimerWithPwm2Ch {
75    fn enable_ch3(&mut self, en: bool);
76    fn set_ch3_cc_value(&mut self, value: u32);
77    fn get_ch3_cc_value(&self) -> u32;
78}
79
80pub trait TimerWithPwm4Ch: TimerWithPwm3Ch {
81    fn enable_ch4(&mut self, en: bool);
82    fn set_ch4_cc_value(&mut self, value: u32);
83    fn get_ch4_cc_value(&self) -> u32;
84}
85
86// Enumerate ------------------------------------------------------------------
87
88#[derive(Clone, Copy, PartialEq, Eq)]
89pub enum Channel {
90    C1,
91    C2,
92    C3,
93    C4,
94}
95
96#[derive(Clone, Copy, Debug, PartialEq, Eq)]
97pub enum CountDirection {
98    Up,
99    Down,
100}
101
102#[derive(Clone, Copy, Debug, PartialEq, Eq)]
103pub enum PwmMode {
104    Mode1,
105    Mode2,
106}
107
108#[derive(Clone, Copy, Debug, PartialEq, Eq)]
109pub enum PwmPolarity {
110    ActiveHigh,
111    ActiveLow,
112}
113
114#[derive(Debug, Eq, PartialEq, Copy, Clone)]
115pub enum Error {
116    /// Timer is disabled
117    Disabled,
118    WrongAutoReload,
119}
120
121/// Interrupt events
122#[derive(Clone, Copy, PartialEq, Eq)]
123pub enum SysEvent {
124    /// [Timer] timed out / count down ended
125    Update,
126}
127
128bitflags::bitflags! {
129    pub struct Event: u32 {
130        const Update  = 1 << 0;
131        const C1 = 1 << 1;
132        const C2 = 1 << 2;
133        const C3 = 1 << 3;
134        const C4 = 1 << 4;
135    }
136}
137
138#[derive(Clone, Copy, Debug, PartialEq, Eq)]
139pub enum MasterMode {
140    ///0: The UG bit from the TIMx_EGR register is used as trigger output
141    Reset,
142    ///1: The counter enable signal, CNT_EN, is used as trigger output
143    Enable,
144    ///2: The update event is selected as trigger output
145    Update,
146    ///3: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
147    ComparePulse,
148    ///4: OC1REF signal is used as trigger output
149    CompareOc1,
150    ///5: OC2REF signal is used as trigger output
151    CompareOc2,
152    ///6: OC3REF signal is used as trigger output
153    CompareOc3,
154    ///7: OC4REF signal is used as trigger output
155    CompareOc4,
156}
stm32f1_hal/common/timer/mod.rs

stm32f1_hal/common/timer/
mod.rs
