stm32f1_hal/common/timer/
mod.rs

1pub mod counter;
2pub mod fix_timer;
3pub mod pwm;
4
5pub use counter::*;
6pub use fix_timer::*;
7pub use pwm::*;
8
9use crate::fugit::HertzU32;
10
11pub trait PwmChannel: embedded_hal::pwm::SetDutyCycle {
12    fn config(&mut self, mode: PwmMode, polarity: PwmPolarity);
13    fn set_enable(&mut self, en: bool);
14}
15
16// ----------------------------------------------------------------------------
17
18pub trait GeneralTimer {
19    fn reset_config(&mut self);
20    fn enable_counter(&mut self);
21    fn disable_counter(&mut self);
22    fn is_counter_enabled(&self) -> bool;
23    fn reset_counter(&mut self);
24    fn enable_preload(&mut self, b: bool);
25    fn max_auto_reload() -> u32;
26    /// # Safety
27    ///
28    /// `arr` must be greater than 0
29    unsafe fn set_auto_reload_unchecked(&mut self, arr: u32);
30    fn set_auto_reload(&mut self, arr: u32) -> Result<(), Error>;
31    fn read_auto_reload(&self) -> u32;
32    fn set_prescaler(&mut self, psc: u16);
33    fn read_prescaler(&self) -> u16;
34    fn read_count(&self) -> u32;
35    fn trigger_update(&mut self);
36    fn stop_in_debug(&mut self, state: bool);
37    fn config_freq(&mut self, clock: HertzU32, update_freq: HertzU32);
38
39    fn clear_interrupt_flag(&mut self, event: Event);
40    fn listen_interrupt(&mut self, event: Event, b: bool);
41    fn get_interrupt_flag(&self) -> Event;
42    fn start_one_pulse(&mut self);
43}
44
45pub trait TimerDirection: GeneralTimer {
46    fn set_count_direction(&mut self, dir: CountDirection);
47}
48
49pub trait MasterTimer: GeneralTimer {
50    fn master_mode(&mut self, mode: MasterMode);
51}
52
53pub trait TimerWithPwm: GeneralTimer {
54    fn start_pwm(&mut self);
55    fn stop_pwm(&mut self);
56
57    fn preload_output_channel_in_mode(&mut self, channel: Channel, mode: PwmMode);
58    fn set_polarity(&mut self, channel: Channel, polarity: PwmPolarity);
59}
60
61pub trait TimerWithPwm1Ch: TimerWithPwm {
62    fn enable_ch1(&mut self, en: bool);
63    fn set_ch1_cc_value(&mut self, value: u32);
64    fn get_ch1_cc_value(&self) -> u32;
65}
66
67pub trait TimerWithPwm2Ch: TimerWithPwm1Ch {
68    fn enable_ch2(&mut self, en: bool);
69    fn set_ch2_cc_value(&mut self, value: u32);
70    fn get_ch2_cc_value(&self) -> u32;
71}
72
73pub trait TimerWithPwm3Ch: TimerWithPwm2Ch {
74    fn enable_ch3(&mut self, en: bool);
75    fn set_ch3_cc_value(&mut self, value: u32);
76    fn get_ch3_cc_value(&self) -> u32;
77}
78
79pub trait TimerWithPwm4Ch: TimerWithPwm3Ch {
80    fn enable_ch4(&mut self, en: bool);
81    fn set_ch4_cc_value(&mut self, value: u32);
82    fn get_ch4_cc_value(&self) -> u32;
83}
84
85// Enumerate ------------------------------------------------------------------
86
87#[derive(Clone, Copy, PartialEq, Eq)]
88pub enum Channel {
89    C1,
90    C2,
91    C3,
92    C4,
93}
94
95#[derive(Clone, Copy, Debug, PartialEq, Eq)]
96pub enum CountDirection {
97    Up,
98    Down,
99}
100
101#[derive(Clone, Copy, Debug, PartialEq, Eq)]
102pub enum PwmMode {
103    Mode1,
104    Mode2,
105}
106
107#[derive(Clone, Copy, Debug, PartialEq, Eq)]
108pub enum PwmPolarity {
109    ActiveHigh,
110    ActiveLow,
111}
112
113#[derive(Debug, Eq, PartialEq, Copy, Clone)]
114pub enum Error {
115    /// Timer is disabled
116    Disabled,
117    WrongAutoReload,
118}
119
120/// Interrupt events
121#[derive(Clone, Copy, PartialEq, Eq)]
122pub enum SysEvent {
123    /// Timer timed out / count down ended
124    Update,
125}
126
127bitflags::bitflags! {
128    pub struct Event: u32 {
129        const Update  = 1 << 0;
130        const C1 = 1 << 1;
131        const C2 = 1 << 2;
132        const C3 = 1 << 3;
133        const C4 = 1 << 4;
134    }
135}
136
137#[derive(Clone, Copy, Debug, PartialEq, Eq)]
138pub enum MasterMode {
139    ///0: The UG bit from the TIMx_EGR register is used as trigger output
140    Reset,
141    ///1: The counter enable signal, CNT_EN, is used as trigger output
142    Enable,
143    ///2: The update event is selected as trigger output
144    Update,
145    ///3: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
146    ComparePulse,
147    ///4: OC1REF signal is used as trigger output
148    CompareOc1,
149    ///5: OC2REF signal is used as trigger output
150    CompareOc2,
151    ///6: OC3REF signal is used as trigger output
152    CompareOc3,
153    ///7: OC4REF signal is used as trigger output
154    CompareOc4,
155}
stm32f1_hal/common/timer/mod.rs

stm32f1_hal/common/timer/
mod.rs
