stm32f1_hal/common/
bus_device.rs

1pub use crate::common::embedded_hal::spi::Operation;
2
3use crate::common::embedded_hal::i2c;
4
5pub trait BusDevice<WD: Word>: Send {
6    fn transaction(&mut self, operations: &mut [Operation<'_, WD>]) -> Result<(), BusError>;
7
8    #[inline]
9    fn write_read(&mut self, write: &[WD], read: &mut [WD]) -> Result<(), BusError> {
10        self.transaction(&mut [Operation::Write(write), Operation::Read(read)])
11    }
12
13    #[inline]
14    fn read(&mut self, buf: &mut [WD]) -> Result<(), BusError> {
15        self.transaction(&mut [Operation::Read(buf)])
16    }
17
18    #[inline]
19    fn write(&mut self, buf: &[WD]) -> Result<(), BusError> {
20        self.transaction(&mut [Operation::Write(buf)])
21    }
22}
23
24pub trait BusDeviceTransfer<WD: Word>: BusDevice<WD> {
25    /// Read data into the first buffer, while writing data from the second buffer.
26    fn transfer(&mut self, read: &mut [WD], write: &[WD]) -> Result<(), BusError>;
27    /// Write data out while reading data into the provided buffer.
28    fn transfer_in_place(&mut self, buf: &mut [WD]) -> Result<(), BusError>;
29}
30
31pub use super::i2c::Address;
32pub trait BusDeviceWithAddress<WD: Word>: BusDevice<WD> {
33    fn set_address(&mut self, address: Address);
34}
35
36pub trait Word: Copy + 'static {}
37impl Word for u8 {}
38impl Word for u16 {}
39
40pub fn from_spi_to_i2c_operation<'a>(value: Operation<'a, u8>) -> i2c::Operation<'a> {
41    match value {
42        Operation::Write(buf) => i2c::Operation::Write(buf),
43        Operation::Read(buf) => i2c::Operation::Read(buf),
44        _ => panic!(),
45    }
46}
47
48#[derive(Debug, Clone, Copy, Eq, PartialEq)]
49pub enum BusError {
50    Busy,
51    ArbitrationLoss,
52    NoAcknowledge,
53    Timeout,
54    Other,
55}
stm32f1_hal/common/bus_device.rs

stm32f1_hal/common/
bus_device.rs
