stm32f1_hal/uart/
mod.rs

1#[cfg(any(all(feature = "stm32f103", feature = "high"), feature = "connectivity"))]
2pub mod uart4;
3#[cfg(any(all(feature = "stm32f103", feature = "high"), feature = "connectivity"))]
4pub mod uart5;
5pub mod usart1;
6pub mod usart2;
7pub mod usart3;
8pub use crate::common::uart::*;
9
10use crate::{
11    Steal,
12    afio::{RemapMode, uart_remap::*},
13    common::os::*,
14    dma::{DmaBindRx, DmaBindTx, DmaRingbufTxLoader},
15    rcc::{BusClock, Enable, Reset},
16};
17
18use crate::Mcu;
19
20pub trait UartInit<U> {
21    fn init(self, mcu: &mut Mcu) -> Uart<U>;
22}
23
24pub trait UartPeriphExt: UartPeriph + BusClock + Enable + Reset + Steal {
25    fn config(&mut self, config: Config, mcu: &mut Mcu);
26    fn enable_comm(&mut self, tx: bool, rx: bool);
27    fn set_stop_bits(&mut self, bits: StopBits);
28}
29
30// wrapper
31pub struct Uart<U> {
32    uart: U,
33}
34
35impl<U: UartPeriphExt> Uart<U> {
36    pub fn into_tx_rx<REMAP: RemapMode<U>>(
37        mut self,
38        pins: (impl UartTxPin<REMAP>, impl UartRxPin<REMAP>),
39        config: Config,
40        mcu: &mut Mcu,
41    ) -> (Option<Tx<U>>, Option<Rx<U>>) {
42        REMAP::remap(&mut mcu.afio);
43        self.uart.config(config, mcu);
44        self.uart.enable_comm(pins.0.is_pin(), pins.1.is_pin());
45        unsafe {
46            (
47                if pins.0.is_pin() {
48                    Some(Tx::new(self.uart.steal()))
49                } else {
50                    None
51                },
52                if pins.1.is_pin() {
53                    Some(Rx::new(self.uart.steal()))
54                } else {
55                    None
56                },
57            )
58        }
59    }
60
61    pub fn get_idle_interrupt_handler(&self) -> UartIdleInterrupt<U> {
62        UartIdleInterrupt::new(unsafe { self.uart.steal() })
63    }
64}
65
66// ------------------------------------------------------------------------------------------------
67
68/// UART Transmitter
69pub struct Tx<U> {
70    uart: U,
71}
72
73impl<U: UartPeriphExt> Tx<U> {
74    pub(crate) fn new(uart: U) -> Self {
75        Self { uart }
76    }
77
78    pub fn into_poll<W: Waiter>(self, timeout: W, flush_timeout: W) -> UartPollTx<U, W> {
79        UartPollTx::new(self.uart, timeout, flush_timeout)
80    }
81
82    pub fn into_interrupt<W: Waiter>(
83        self,
84        buf_size: usize,
85        timeout: W,
86        flush_timeout: W,
87    ) -> (UartInterruptTx<U, W>, UartInterruptTxHandler<U>) {
88        let u2 = unsafe { self.uart.steal() };
89        UartInterruptTx::new([self.uart, u2], buf_size, timeout, flush_timeout)
90    }
91
92    // pub fn into_dma<CH>(self, dma_ch: CH) -> UartDmaTx<U, CH>
93    // where
94    //     CH: BindDmaTx<U>,
95    // {
96    //     UartDmaTx::<U, CH>::new(self.uart, dma_ch)
97    // }
98
99    pub fn into_dma_ringbuf<CH, W>(
100        self,
101        dma_ch: CH,
102        buf_size: usize,
103        timeout: W,
104        flush_timeout: W,
105    ) -> (UartDmaBufTx<U, CH, W>, DmaRingbufTxLoader<u8, CH>)
106    where
107        CH: DmaBindTx<U>,
108        W: Waiter,
109    {
110        UartDmaBufTx::new(self.uart, dma_ch, buf_size, timeout, flush_timeout)
111    }
112}
113
114// ------------------------------------------------------------------------------------------------
115
116/// UART Receiver
117pub struct Rx<U> {
118    uart: U,
119}
120
121impl<U: UartPeriphExt> Rx<U> {
122    pub(crate) fn new(uart: U) -> Self {
123        Self { uart }
124    }
125
126    pub fn into_poll<W: Waiter>(self, timeout: W, continue_timeout: W) -> UartPollRx<U, W> {
127        UartPollRx::new(self.uart, timeout, continue_timeout)
128    }
129
130    pub fn into_interrupt<W: Waiter>(
131        self,
132        buf_size: usize,
133        timeout: W,
134    ) -> (UartInterruptRx<U, W>, UartInterruptRxHandler<U>) {
135        let u2 = unsafe { self.uart.steal() };
136        UartInterruptRx::new([self.uart, u2], buf_size, timeout)
137    }
138
139    pub fn into_dma_circle<CH, W>(
140        self,
141        dma_ch: CH,
142        buf_size: usize,
143        timeout: W,
144    ) -> UartDmaRx<U, CH, W>
145    where
146        CH: DmaBindRx<U>,
147        W: Waiter,
148    {
149        UartDmaRx::new(self.uart, dma_ch, buf_size, timeout)
150    }
151}
stm32f1_hal/uart/mod.rs

stm32f1_hal/uart/
mod.rs
