stm32f1_hal/timer/
mod.rs

1use crate::{
2    Mcu, Steal,
3    afio::{RemapMode, timer_remap::*},
4    pac::DBGMCU as DBG,
5    rcc,
6    time::Hertz,
7};
8
9pub use crate::common::timer::*;
10
11#[cfg(feature = "rtic")]
12pub mod monotonic;
13#[cfg(feature = "rtic")]
14pub use monotonic::*;
15pub mod syst;
16pub use syst::*;
17#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity"))]
18pub mod timer1;
19#[cfg(feature = "xl")]
20pub mod timer10;
21#[cfg(feature = "xl")]
22pub mod timer11;
23#[cfg(any(feature = "xl", all(feature = "stm32f100", feature = "high",)))]
24pub mod timer12;
25#[cfg(any(feature = "xl", all(feature = "stm32f100", feature = "high",)))]
26pub mod timer13;
27#[cfg(any(feature = "xl", all(feature = "stm32f100", feature = "high",)))]
28pub mod timer14;
29#[cfg(feature = "stm32f100")]
30pub mod timer15;
31#[cfg(feature = "stm32f100")]
32pub mod timer16;
33#[cfg(feature = "stm32f100")]
34pub mod timer17;
35pub mod timer2;
36pub mod timer3;
37#[cfg(feature = "medium")]
38pub mod timer4;
39#[cfg(any(feature = "high", feature = "connectivity"))]
40pub mod timer5;
41#[cfg(any(feature = "stm32f100", feature = "high", feature = "connectivity"))]
42pub mod timer6;
43#[cfg(any(
44    all(feature = "high", any(feature = "stm32f101", feature = "stm32f103")),
45    any(feature = "stm32f100", feature = "connectivity")
46))]
47pub mod timer7;
48#[cfg(all(feature = "stm32f103", feature = "high"))]
49pub mod timer8;
50#[cfg(feature = "xl")]
51pub mod timer9;
52
53pub trait Instance: rcc::Enable + rcc::Reset + rcc::BusTimerClock + GeneralTimer {}
54
55// Initialize -----------------------------------------------------------------
56
57pub trait TimerInit<TIM> {
58    fn constrain(self, mcu: &mut Mcu) -> Timer<TIM>;
59}
60
61/// Timer wrapper
62pub struct Timer<TIM> {
63    tim: TIM,
64    clk: Hertz,
65}
66
67impl<TIM: Instance + Steal> Timer<TIM> {
68    /// Initialize timer
69    pub fn new(tim: TIM, mcu: &mut Mcu) -> Self {
70        // Enable and reset the timer peripheral
71        mcu.rcc.enable(&tim);
72        mcu.rcc.reset(&tim);
73
74        Self {
75            clk: mcu.rcc.get_timer_clock(&tim),
76            tim,
77        }
78    }
79
80    /// Non-blocking [Counter] with custom fixed precision
81    pub fn counter<const FREQ: u32>(self) -> Counter<TIM, FREQ> {
82        FTimer::new(self.tim, self.clk).counter()
83    }
84
85    /// Non-blocking [Counter] with fixed precision of 1 ms (1 kHz sampling)
86    ///
87    /// Can wait from 2 ms to 65 sec for 16-bit timer and from 2 ms to 49 days for 32-bit timer.
88    ///
89    /// NOTE: don't use this if your system frequency more than 65 MHz
90    pub fn counter_ms(self) -> CounterMs<TIM> {
91        self.counter::<1_000>()
92    }
93
94    /// Non-blocking [Counter] with fixed precision of 1 μs (1 MHz sampling)
95    ///
96    /// Can wait from 2 μs to 65 ms for 16-bit timer and from 2 μs to 71 min for 32-bit timer.
97    pub fn counter_us(self) -> CounterUs<TIM> {
98        self.counter::<1_000_000>()
99    }
100
101    /// Non-blocking [Counter] with dynamic precision which uses `Hertz` as Duration units
102    pub fn counter_hz(self) -> CounterHz<TIM> {
103        CounterHz {
104            tim: self.tim,
105            clk: self.clk,
106        }
107    }
108
109    pub fn release(self) -> TIM {
110        self.tim
111    }
112
113    /// Starts listening for an `event`
114    ///
115    /// Note, you will also have to enable the TIM2 interrupt in the NVIC to start
116    /// receiving events.
117    pub fn listen(&mut self, event: Event) {
118        self.tim.listen_interrupt(event, true);
119    }
120
121    /// Clears interrupt associated with `event`.
122    ///
123    /// If the interrupt is not cleared, it will immediately retrigger after
124    /// the ISR has finished.
125    pub fn clear_interrupt(&mut self, event: Event) {
126        self.tim.clear_interrupt_flag(event);
127    }
128
129    pub fn get_interrupt(&mut self) -> Event {
130        self.tim.get_interrupt_flag()
131    }
132
133    /// Stops listening for an `event`
134    pub fn unlisten(&mut self, event: Event) {
135        self.tim.listen_interrupt(event, false);
136    }
137
138    /// Stopping timer in debug mode can cause troubles when sampling the signal
139    pub fn stop_in_debug(&mut self, state: bool) {
140        self.tim.stop_in_debug(state);
141    }
142}
143
144impl<TIM: Instance + MasterTimer> Timer<TIM> {
145    pub fn set_master_mode(&mut self, mode: MasterMode) {
146        self.tim.master_mode(mode)
147    }
148}
149
150impl<TIM: Instance + TimerDirection> Timer<TIM> {
151    pub fn set_count_direction(&mut self, dir: CountDirection) {
152        self.tim.set_count_direction(dir);
153    }
154}
155
156// Initialize PWM -------------------------------------------------------------
157
158impl<'a, TIM: Instance + TimerWithPwm1Ch + Steal + 'a> Timer<TIM> {
159    pub fn into_pwm1<REMAP: RemapMode<TIM>>(
160        mut self,
161        _pin: impl TimCh1Pin<REMAP>,
162        update_freq: Hertz,
163        preload: bool,
164        mcu: &mut Mcu,
165    ) -> (PwmTimer<TIM>, impl PwmChannel + 'a) {
166        REMAP::remap(&mut mcu.afio);
167        self.tim.enable_preload(preload);
168        self.tim.config_freq(self.clk, update_freq);
169
170        let c1 = PwmChannel1::new(unsafe { self.tim.steal() });
171        let t = PwmTimer::new(self.tim, self.clk);
172        (t, c1)
173    }
174}
175
176impl<'a, TIM: Instance + TimerWithPwm2Ch + Steal + 'a> Timer<TIM> {
177    pub fn into_pwm2<REMAP: RemapMode<TIM>>(
178        mut self,
179        pins: (Option<impl TimCh1Pin<REMAP>>, Option<impl TimCh2Pin<REMAP>>),
180        update_freq: Hertz,
181        preload: bool,
182        mcu: &mut Mcu,
183    ) -> (
184        PwmTimer<TIM>,
185        Option<impl PwmChannel + 'a>,
186        Option<impl PwmChannel + 'a>,
187    ) {
188        REMAP::remap(&mut mcu.afio);
189        self.tim.enable_preload(preload);
190        self.tim.config_freq(self.clk, update_freq);
191
192        let c1 = pins
193            .0
194            .map(|_| PwmChannel1::new(unsafe { self.tim.steal() }));
195        let c2 = pins
196            .1
197            .map(|_| PwmChannel2::new(unsafe { self.tim.steal() }));
198        let t = PwmTimer::new(self.tim, self.clk);
199        (t, c1, c2)
200    }
201}
202
203impl<'a, TIM: Instance + TimerWithPwm4Ch + Steal + 'a> Timer<TIM> {
204    pub fn into_pwm4<REMAP: RemapMode<TIM>>(
205        mut self,
206        pins: (
207            Option<impl TimCh1Pin<REMAP>>,
208            Option<impl TimCh2Pin<REMAP>>,
209            Option<impl TimCh3Pin<REMAP>>,
210            Option<impl TimCh4Pin<REMAP>>,
211        ),
212        update_freq: Hertz,
213        preload: bool,
214        mcu: &mut Mcu,
215    ) -> (
216        PwmTimer<TIM>,
217        Option<impl PwmChannel + 'a>,
218        Option<impl PwmChannel + 'a>,
219        Option<impl PwmChannel + 'a>,
220        Option<impl PwmChannel + 'a>,
221    ) {
222        REMAP::remap(&mut mcu.afio);
223        self.tim.enable_preload(preload);
224        self.tim.config_freq(self.clk, update_freq);
225
226        let c1 = pins
227            .0
228            .map(|_| PwmChannel1::new(unsafe { self.tim.steal() }));
229        let c2 = pins
230            .1
231            .map(|_| PwmChannel2::new(unsafe { self.tim.steal() }));
232        let c3 = pins
233            .2
234            .map(|_| PwmChannel3::new(unsafe { self.tim.steal() }));
235        let c4 = pins
236            .3
237            .map(|_| PwmChannel4::new(unsafe { self.tim.steal() }));
238        let t = PwmTimer::new(self.tim, self.clk);
239        (t, c1, c2, c3, c4)
240    }
241}
242
243// Destroy --------------------------------------------------------------------
244
245pub fn destroy_counter_hz<TIM: GeneralTimer>(mut counter: CounterHz<TIM>) -> Timer<TIM> {
246    // stop timer
247    counter.tim.reset_config();
248    Timer {
249        tim: counter.tim,
250        clk: counter.clk,
251    }
252}
253
254#[cfg(feature = "rtic")]
255pub fn destroy_mono_timer<TIM: GeneralTimer, const FREQ: u32>(
256    mut timer: MonoTimer<TIM, FREQ>,
257) -> FTimer<TIM, FREQ> {
258    timer.tim.reset_config();
259    timer.timer
260}
261
262// Enumerate ------------------------------------------------------------------
263
264#[derive(Clone, Copy, Debug, PartialEq, Eq)]
265#[repr(u8)]
266pub enum Ocm {
267    Frozen = 0,
268    ActiveOnMatch = 1,
269    InactiveOnMatch = 2,
270    Toggle = 3,
271    ForceInactive = 4,
272    ForceActive = 5,
273    PwmMode1 = 6,
274    PwmMode2 = 7,
275}
276
277impl From<PwmMode> for Ocm {
278    fn from(value: PwmMode) -> Self {
279        match value {
280            PwmMode::Mode1 => Ocm::PwmMode1,
281            PwmMode::Mode2 => Ocm::PwmMode2,
282        }
283    }
284}
285
286// Utilities ------------------------------------------------------------------
287
288const fn compute_prescaler_arr(timer_clk: u32, update_freq: u32) -> (u32, u32) {
289    let ticks = timer_clk / update_freq;
290    let prescaler = (ticks - 1) / (1 << 16);
291    let arr = ticks / (prescaler + 1) - 1;
292    (prescaler, arr)
293}
stm32f1_hal/timer/mod.rs

stm32f1_hal/timer/
mod.rs
