stm32f1_hal/common/timer/
mod.rs

1pub mod pwm;
2pub use pwm::*;
3pub mod counter;
4pub use counter::*;
5pub mod fix_timer;
6pub use fix_timer::*;
7
8use fugit::HertzU32 as Hertz;
9
10pub trait PwmChannel: embedded_hal::pwm::SetDutyCycle {
11    fn config(&mut self, mode: PwmMode, polarity: PwmPolarity);
12    fn set_enable(&mut self, en: bool);
13}
14
15// ----------------------------------------------------------------------------
16
17pub trait GeneralTimer {
18    fn reset_config(&mut self);
19    fn enable_counter(&mut self);
20    fn disable_counter(&mut self);
21    fn is_counter_enabled(&self) -> bool;
22    fn reset_counter(&mut self);
23    fn enable_preload(&mut self, b: bool);
24    fn max_auto_reload() -> u32;
25    /// # Safety
26    ///
27    /// `arr` must be greater than 0
28    unsafe fn set_auto_reload_unchecked(&mut self, arr: u32);
29    fn set_auto_reload(&mut self, arr: u32) -> Result<(), Error>;
30    fn read_auto_reload(&self) -> u32;
31    fn set_prescaler(&mut self, psc: u16);
32    fn read_prescaler(&self) -> u16;
33    fn read_count(&self) -> u32;
34    fn trigger_update(&mut self);
35    fn stop_in_debug(&mut self, state: bool);
36    fn config_freq(&mut self, clock: Hertz, update_freq: Hertz);
37
38    fn clear_interrupt_flag(&mut self, event: Event);
39    fn listen_interrupt(&mut self, event: Event, b: bool);
40    fn get_interrupt_flag(&self) -> Event;
41    fn start_one_pulse(&mut self);
42}
43
44pub trait TimerDirection: GeneralTimer {
45    fn set_count_direction(&mut self, dir: CountDirection);
46}
47
48pub trait MasterTimer: GeneralTimer {
49    fn master_mode(&mut self, mode: MasterMode);
50}
51
52pub trait TimerWithPwm: GeneralTimer {
53    fn start_pwm(&mut self);
54    fn stop_pwm(&mut self);
55
56    fn preload_output_channel_in_mode(&mut self, channel: Channel, mode: PwmMode);
57    fn set_polarity(&mut self, channel: Channel, polarity: PwmPolarity);
58}
59
60pub trait TimerWithPwm1Ch: TimerWithPwm {
61    fn enable_ch1(&mut self, en: bool);
62    fn set_ch1_cc_value(&mut self, value: u32);
63    fn get_ch1_cc_value(&self) -> u32;
64}
65
66pub trait TimerWithPwm2Ch: TimerWithPwm1Ch {
67    fn enable_ch2(&mut self, en: bool);
68    fn set_ch2_cc_value(&mut self, value: u32);
69    fn get_ch2_cc_value(&self) -> u32;
70}
71
72pub trait TimerWithPwm3Ch: TimerWithPwm2Ch {
73    fn enable_ch3(&mut self, en: bool);
74    fn set_ch3_cc_value(&mut self, value: u32);
75    fn get_ch3_cc_value(&self) -> u32;
76}
77
78pub trait TimerWithPwm4Ch: TimerWithPwm3Ch {
79    fn enable_ch4(&mut self, en: bool);
80    fn set_ch4_cc_value(&mut self, value: u32);
81    fn get_ch4_cc_value(&self) -> u32;
82}
83
84// Enumerate ------------------------------------------------------------------
85
86#[derive(Clone, Copy, PartialEq, Eq)]
87pub enum Channel {
88    C1,
89    C2,
90    C3,
91    C4,
92}
93
94#[derive(Clone, Copy, Debug, PartialEq, Eq)]
95pub enum CountDirection {
96    Up,
97    Down,
98}
99
100#[derive(Clone, Copy, Debug, PartialEq, Eq)]
101pub enum PwmMode {
102    Mode1,
103    Mode2,
104}
105
106#[derive(Clone, Copy, Debug, PartialEq, Eq)]
107pub enum PwmPolarity {
108    ActiveHigh,
109    ActiveLow,
110}
111
112#[derive(Debug, Eq, PartialEq, Copy, Clone)]
113pub enum Error {
114    /// Timer is disabled
115    Disabled,
116    WrongAutoReload,
117}
118
119/// Interrupt events
120#[derive(Clone, Copy, PartialEq, Eq)]
121pub enum SysEvent {
122    /// [Timer] timed out / count down ended
123    Update,
124}
125
126bitflags::bitflags! {
127    pub struct Event: u32 {
128        const Update  = 1 << 0;
129        const C1 = 1 << 1;
130        const C2 = 1 << 2;
131        const C3 = 1 << 3;
132        const C4 = 1 << 4;
133    }
134}
135
136#[derive(Clone, Copy, Debug, PartialEq, Eq)]
137pub enum MasterMode {
138    ///0: The UG bit from the TIMx_EGR register is used as trigger output
139    Reset,
140    ///1: The counter enable signal, CNT_EN, is used as trigger output
141    Enable,
142    ///2: The update event is selected as trigger output
143    Update,
144    ///3: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
145    ComparePulse,
146    ///4: OC1REF signal is used as trigger output
147    CompareOc1,
148    ///5: OC2REF signal is used as trigger output
149    CompareOc2,
150    ///6: OC3REF signal is used as trigger output
151    CompareOc3,
152    ///7: OC4REF signal is used as trigger output
153    CompareOc4,
154}
stm32f1_hal/common/timer/mod.rs

stm32f1_hal/common/timer/
mod.rs
