stm32f1_hal/timer/
timer11.rs

1#![allow(unused_variables)]
2type TimerX = pac::TIM11;
3type Width = u16;
4
5// sync begin
6
7use super::*;
8use crate::{Mcu, pac};
9
10impl Instance for TimerX {}
11
12impl TimerInit<TimerX> for TimerX {
13    fn constrain(self, mcu: &mut Mcu) -> Timer<TimerX> {
14        Timer::new(self, mcu)
15    }
16}
17
18impl GeneralTimer for TimerX {
19    #[inline(always)]
20    fn reset_config(&mut self) {
21        self.cr1().reset();
22    }
23
24    #[inline(always)]
25    fn enable_counter(&mut self) {
26        self.cr1().modify(|_, w| w.cen().set_bit());
27    }
28
29    #[inline(always)]
30    fn disable_counter(&mut self) {
31        self.cr1().modify(|_, w| w.cen().clear_bit());
32    }
33
34    #[inline(always)]
35    fn is_counter_enabled(&self) -> bool {
36        self.cr1().read().cen().is_enabled()
37    }
38
39    #[inline(always)]
40    fn reset_counter(&mut self) {
41        self.cnt().reset();
42    }
43
44    #[inline(always)]
45    fn max_auto_reload() -> u32 {
46        Width::MAX as u32
47    }
48
49    #[inline(always)]
50    unsafe fn set_auto_reload_unchecked(&mut self, arr: u32) {
51        unsafe {
52            self.arr().write(|w| w.bits(arr));
53        }
54    }
55
56    #[inline(always)]
57    fn set_auto_reload(&mut self, arr: u32) -> Result<(), Error> {
58        // Note: Make it impossible to set the ARR value to 0, since this
59        // would cause an infinite loop.
60        if arr > 0 && arr <= Self::max_auto_reload() {
61            unsafe { self.set_auto_reload_unchecked(arr) }
62            Ok(())
63        } else {
64            Err(Error::WrongAutoReload)
65        }
66    }
67
68    #[inline(always)]
69    fn read_auto_reload(&self) -> u32 {
70        self.arr().read().bits()
71    }
72
73    #[inline(always)]
74    fn set_prescaler(&mut self, psc: u16) {
75        self.psc().write(|w| w.psc().set(psc));
76    }
77
78    #[inline(always)]
79    fn read_prescaler(&self) -> u16 {
80        self.psc().read().psc().bits()
81    }
82
83    #[inline(always)]
84    fn read_count(&self) -> u32 {
85        self.cnt().read().bits()
86    }
87
88    #[inline(always)]
89    fn trigger_update(&mut self) {
90        // Sets the URS bit to prevent an interrupt from being triggered by
91        // the UG bit
92        self.cr1().modify(|_, w| w.urs().set_bit());
93        self.egr().write(|w| w.ug().set_bit());
94        self.cr1().modify(|_, w| w.urs().clear_bit());
95    }
96
97    #[inline]
98    fn config_freq(&mut self, clock: Hertz, update_freq: Hertz) {
99        let (prescaler, arr) = compute_prescaler_arr(clock.raw(), update_freq.raw());
100        self.set_prescaler(prescaler as u16);
101        self.set_auto_reload(arr).unwrap();
102        // Trigger update event to load the registers
103        self.trigger_update();
104    }
105
106    #[inline(always)]
107    fn clear_interrupt_flag(&mut self, event: Event) {
108        self.sr()
109            .write(|w| unsafe { w.bits(0xffff & !event.bits()) });
110    }
111
112    #[inline(always)]
113    fn listen_interrupt(&mut self, event: Event, b: bool) {
114        self.dier().modify(|r, w| unsafe {
115            w.bits(if b {
116                r.bits() | event.bits()
117            } else {
118                r.bits() & !event.bits()
119            })
120        });
121    }
122
123    #[inline(always)]
124    fn get_interrupt_flag(&self) -> Event {
125        Event::from_bits_truncate(self.sr().read().bits())
126    }
127
128    #[inline(always)]
129    fn start_one_pulse(&mut self) {
130        self.cr1().modify(|_, w| w.opm().set_bit().cen().set_bit());
131    }
132
133    #[inline(always)]
134    fn stop_in_debug(&mut self, state: bool) {
135        let dbg = unsafe { DBG::steal() };
136        // sync dbg_t11
137        //TODO: restore these timers once stm32-rs has been updated
138        // dbg.cr().modify(|_, w| w.dbg_tim11_stop().bit(state));
139        // sync dbg_end
140    }
141
142    #[inline(always)]
143    fn enable_preload(&mut self, b: bool) {
144        self.cr1().modify(|_, w| w.arpe().bit(b));
145    }
146}
147
148// sync pwm
149// PWM ------------------------------------------------------------------------
150
151impl TimerWithPwm for TimerX {
152    fn stop_pwm(&mut self) {
153        self.disable_counter();
154    }
155
156    // sync start_pwm
157
158    #[inline(always)]
159    fn start_pwm(&mut self) {
160        self.reset_counter();
161        self.enable_counter();
162    }
163
164    // sync pwm_cfg_1
165
166    #[inline(always)]
167    fn preload_output_channel_in_mode(&mut self, channel: Channel, mode: PwmMode) {
168        let mode = Ocm::from(mode);
169        if channel == Channel::C1 {
170            self.ccmr1_output()
171                .modify(|_, w| w.oc1pe().set_bit().oc1m().set(mode as _));
172        }
173    }
174
175    fn set_polarity(&mut self, channel: Channel, polarity: PwmPolarity) {
176        if channel == Channel::C1 {
177            self.ccer()
178                .modify(|_, w| w.cc1p().bit(polarity == PwmPolarity::ActiveLow));
179        }
180    }
181}
182
183// sync pwm_ch1
184// PWM Channels ---------------------------------------------------------------
185
186impl TimerWithPwm1Ch for TimerX {
187    #[inline(always)]
188    fn enable_ch1(&mut self, en: bool) {
189        self.ccer().modify(|_, w| w.cc1e().bit(en));
190    }
191
192    #[inline(always)]
193    fn set_ch1_cc_value(&mut self, value: u32) {
194        unsafe { self.ccr1().write(|w| w.bits(value)) };
195    }
196
197    #[inline(always)]
198    fn get_ch1_cc_value(&self) -> u32 {
199        self.ccr1().read().bits()
200    }
201}
202
203// sync end
stm32f1_hal/timer/timer11.rs

stm32f1_hal/timer/
timer11.rs
