stm32f1_hal/common/timer/
fix_timer.rs1use super::*;
2
3pub struct FTimer<TIM, const FREQ: u32> {
7 pub(crate) tim: TIM,
8 clk: Hertz,
9}
10
11pub type FTimerUs<TIM> = FTimer<TIM, 1_000_000>;
13
14pub type FTimerMs<TIM> = FTimer<TIM, 1_000>;
18
19impl<TIM: GeneralTimer, const FREQ: u32> FTimer<TIM, FREQ> {
20 pub fn new(tim: TIM, clk: Hertz) -> Self {
22 let mut t = Self { tim, clk };
23 t.configure();
24 t
25 }
26
27 pub fn configure(&mut self) {
29 assert!(self.clk.raw() % FREQ == 0);
30 let psc = self.clk.raw() / FREQ;
31 self.tim.set_prescaler(u16::try_from(psc - 1).unwrap());
32 }
33
34 pub fn counter(self) -> Counter<TIM, FREQ> {
36 Counter(self)
37 }
38
39 pub fn delay(self) -> Delay<TIM, FREQ> {
41 Delay(self)
42 }
43
44 pub fn release(self) -> TIM {
46 self.tim
47 }
48
49 pub fn listen(&mut self, event: Event) {
54 self.tim.listen_interrupt(event, true);
55 }
56
57 pub fn clear_interrupt(&mut self, event: Event) {
62 self.tim.clear_interrupt_flag(event);
63 }
64
65 pub fn get_interrupt(&mut self) -> Event {
66 self.tim.get_interrupt_flag()
67 }
68
69 pub fn unlisten(&mut self, event: Event) {
71 self.tim.listen_interrupt(event, false);
72 }
73
74 pub fn stop_in_debug(&mut self, state: bool) {
76 self.tim.stop_in_debug(state);
77 }
78}
79
80impl<TIM: MasterTimer, const FREQ: u32> FTimer<TIM, FREQ> {
81 pub fn set_master_mode(&mut self, mode: MasterMode) {
82 self.tim.master_mode(mode)
83 }
84}