stm32f1_hal/afio/
timer_remap.rs

1#![allow(unused_variables)]
2use super::*;
3use crate::{gpio::*, pac::*};
4
5// table
6// Do NOT manually modify the code.
7// It's generated by scripts/generate_remap_table.py from scripts/table/stm32f1_remap_peripheral.csv
8
9// Binder types ------------------
10
11pub trait TimBkinPin<REMAP> {}
12impl<T> TimBkinPin<T> for NonePin {}
13pub trait TimCh1Pin<REMAP> {}
14impl<T> TimCh1Pin<T> for NonePin {}
15pub trait TimCh1nPin<REMAP> {}
16impl<T> TimCh1nPin<T> for NonePin {}
17pub trait TimCh2Pin<REMAP> {}
18impl<T> TimCh2Pin<T> for NonePin {}
19pub trait TimCh2nPin<REMAP> {}
20impl<T> TimCh2nPin<T> for NonePin {}
21pub trait TimCh3Pin<REMAP> {}
22impl<T> TimCh3Pin<T> for NonePin {}
23pub trait TimCh3nPin<REMAP> {}
24impl<T> TimCh3nPin<T> for NonePin {}
25pub trait TimCh4Pin<REMAP> {}
26impl<T> TimCh4Pin<T> for NonePin {}
27pub trait TimEtrPin<REMAP> {}
28impl<T> TimEtrPin<T> for NonePin {}
29
30// Bind pins ---------------------
31
32#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity"))]
33impl TimCh1Pin<RemapDefault<TIM1>> for PA8<Alternate<PushPull>> {}
34#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity"))]
35impl TimCh2Pin<RemapDefault<TIM1>> for PA9<Alternate<PushPull>> {}
36#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity"))]
37impl TimCh3Pin<RemapDefault<TIM1>> for PA10<Alternate<PushPull>> {}
38#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity"))]
39impl TimCh4Pin<RemapDefault<TIM1>> for PA11<Alternate<PushPull>> {}
40#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity"))]
41impl TimCh1Pin<RemapFull<TIM1>> for PE9<Alternate<PushPull>> {}
42#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity"))]
43impl TimCh2Pin<RemapFull<TIM1>> for PE11<Alternate<PushPull>> {}
44#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity"))]
45impl TimCh3Pin<RemapFull<TIM1>> for PE13<Alternate<PushPull>> {}
46#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity"))]
47impl TimCh4Pin<RemapFull<TIM1>> for PE14<Alternate<PushPull>> {}
48#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity"))]
49impl TimCh1Pin<RemapPartial1<TIM1>> for PA8<Alternate<PushPull>> {}
50#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity"))]
51impl TimCh2Pin<RemapPartial1<TIM1>> for PA9<Alternate<PushPull>> {}
52#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity"))]
53impl TimCh3Pin<RemapPartial1<TIM1>> for PA10<Alternate<PushPull>> {}
54#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity"))]
55impl TimCh4Pin<RemapPartial1<TIM1>> for PA11<Alternate<PushPull>> {}
56#[cfg(feature = "xl")]
57impl TimCh1Pin<RemapDefault<TIM10>> for PB8<Alternate<PushPull>> {}
58#[cfg(feature = "xl")]
59impl TimCh1Pin<RemapFull<TIM10>> for PF6<Alternate<PushPull>> {}
60#[cfg(feature = "xl")]
61impl TimCh1Pin<RemapDefault<TIM11>> for PB9<Alternate<PushPull>> {}
62#[cfg(feature = "xl")]
63impl TimCh1Pin<RemapFull<TIM11>> for PF7<Alternate<PushPull>> {}
64#[cfg(any(feature = "xl", all(feature = "stm32f100", feature = "high",)))]
65impl TimCh1Pin<RemapDefault<TIM12>> for PB14<Alternate<PushPull>> {}
66#[cfg(any(feature = "xl", all(feature = "stm32f100", feature = "high",)))]
67impl TimCh2Pin<RemapDefault<TIM12>> for PB15<Alternate<PushPull>> {}
68#[cfg(any(feature = "xl", all(feature = "stm32f100", feature = "high",)))]
69impl TimCh1Pin<RemapDefault<TIM13>> for PA6<Alternate<PushPull>> {}
70#[cfg(any(feature = "xl", all(feature = "stm32f100", feature = "high",)))]
71impl TimCh1Pin<RemapFull<TIM13>> for PF8<Alternate<PushPull>> {}
72#[cfg(any(feature = "xl", all(feature = "stm32f100", feature = "high",)))]
73impl TimCh1Pin<RemapDefault<TIM14>> for PA7<Alternate<PushPull>> {}
74#[cfg(any(feature = "xl", all(feature = "stm32f100", feature = "high",)))]
75impl TimCh1Pin<RemapFull<TIM14>> for PF9<Alternate<PushPull>> {}
76impl TimCh1Pin<RemapDefault<TIM2>> for PA0<Alternate<PushPull>> {}
77impl TimCh2Pin<RemapDefault<TIM2>> for PA1<Alternate<PushPull>> {}
78impl TimCh3Pin<RemapDefault<TIM2>> for PA2<Alternate<PushPull>> {}
79impl TimCh4Pin<RemapDefault<TIM2>> for PA3<Alternate<PushPull>> {}
80impl TimCh1Pin<RemapFull<TIM2>> for PA15<Alternate<PushPull>> {}
81impl TimCh2Pin<RemapFull<TIM2>> for PB3<Alternate<PushPull>> {}
82impl TimCh3Pin<RemapFull<TIM2>> for PB10<Alternate<PushPull>> {}
83impl TimCh4Pin<RemapFull<TIM2>> for PB11<Alternate<PushPull>> {}
84impl TimCh1Pin<RemapPartial1<TIM2>> for PA15<Alternate<PushPull>> {}
85impl TimCh2Pin<RemapPartial1<TIM2>> for PB3<Alternate<PushPull>> {}
86impl TimCh3Pin<RemapPartial1<TIM2>> for PA2<Alternate<PushPull>> {}
87impl TimCh4Pin<RemapPartial1<TIM2>> for PA3<Alternate<PushPull>> {}
88impl TimCh1Pin<RemapPartial2<TIM2>> for PA0<Alternate<PushPull>> {}
89impl TimCh2Pin<RemapPartial2<TIM2>> for PA1<Alternate<PushPull>> {}
90impl TimCh3Pin<RemapPartial2<TIM2>> for PB10<Alternate<PushPull>> {}
91impl TimCh4Pin<RemapPartial2<TIM2>> for PB11<Alternate<PushPull>> {}
92impl TimCh1Pin<RemapDefault<TIM3>> for PA6<Alternate<PushPull>> {}
93impl TimCh2Pin<RemapDefault<TIM3>> for PA7<Alternate<PushPull>> {}
94impl TimCh3Pin<RemapDefault<TIM3>> for PB0<Alternate<PushPull>> {}
95impl TimCh4Pin<RemapDefault<TIM3>> for PB1<Alternate<PushPull>> {}
96impl TimCh1Pin<RemapFull<TIM3>> for PC6<Alternate<PushPull>> {}
97impl TimCh2Pin<RemapFull<TIM3>> for PC7<Alternate<PushPull>> {}
98impl TimCh3Pin<RemapFull<TIM3>> for PC8<Alternate<PushPull>> {}
99impl TimCh4Pin<RemapFull<TIM3>> for PC9<Alternate<PushPull>> {}
100impl TimCh1Pin<RemapPartial1<TIM3>> for PB4<Alternate<PushPull>> {}
101impl TimCh2Pin<RemapPartial1<TIM3>> for PB5<Alternate<PushPull>> {}
102impl TimCh3Pin<RemapPartial1<TIM3>> for PB0<Alternate<PushPull>> {}
103impl TimCh4Pin<RemapPartial1<TIM3>> for PB1<Alternate<PushPull>> {}
104#[cfg(feature = "medium")]
105impl TimCh1Pin<RemapDefault<TIM4>> for PB6<Alternate<PushPull>> {}
106#[cfg(feature = "medium")]
107impl TimCh2Pin<RemapDefault<TIM4>> for PB7<Alternate<PushPull>> {}
108#[cfg(feature = "medium")]
109impl TimCh3Pin<RemapDefault<TIM4>> for PB8<Alternate<PushPull>> {}
110#[cfg(feature = "medium")]
111impl TimCh4Pin<RemapDefault<TIM4>> for PB9<Alternate<PushPull>> {}
112#[cfg(feature = "medium")]
113impl TimCh1Pin<RemapFull<TIM4>> for PD12<Alternate<PushPull>> {}
114#[cfg(feature = "medium")]
115impl TimCh2Pin<RemapFull<TIM4>> for PD13<Alternate<PushPull>> {}
116#[cfg(feature = "medium")]
117impl TimCh3Pin<RemapFull<TIM4>> for PD14<Alternate<PushPull>> {}
118#[cfg(feature = "medium")]
119impl TimCh4Pin<RemapFull<TIM4>> for PD15<Alternate<PushPull>> {}
120#[cfg(any(feature = "high", feature = "connectivity"))]
121impl TimCh1Pin<RemapDefault<TIM5>> for PA0<Alternate<PushPull>> {}
122#[cfg(any(feature = "high", feature = "connectivity"))]
123impl TimCh2Pin<RemapDefault<TIM5>> for PA1<Alternate<PushPull>> {}
124#[cfg(any(feature = "high", feature = "connectivity"))]
125impl TimCh3Pin<RemapDefault<TIM5>> for PA2<Alternate<PushPull>> {}
126#[cfg(any(feature = "high", feature = "connectivity"))]
127impl TimCh4Pin<RemapDefault<TIM5>> for PA3<Alternate<PushPull>> {}
128#[cfg(any(feature = "high", feature = "connectivity"))]
129impl TimCh1Pin<RemapFull<TIM5>> for PA0<Alternate<PushPull>> {}
130#[cfg(any(feature = "high", feature = "connectivity"))]
131impl TimCh2Pin<RemapFull<TIM5>> for PA1<Alternate<PushPull>> {}
132#[cfg(any(feature = "high", feature = "connectivity"))]
133impl TimCh3Pin<RemapFull<TIM5>> for PA2<Alternate<PushPull>> {}
134#[cfg(all(feature = "stm32f103", feature = "high"))]
135impl TimCh1Pin<RemapDefault<TIM8>> for PC6<Alternate<PushPull>> {}
136#[cfg(all(feature = "stm32f103", feature = "high"))]
137impl TimCh2Pin<RemapDefault<TIM8>> for PC7<Alternate<PushPull>> {}
138#[cfg(all(feature = "stm32f103", feature = "high"))]
139impl TimCh3Pin<RemapDefault<TIM8>> for PC8<Alternate<PushPull>> {}
140#[cfg(all(feature = "stm32f103", feature = "high"))]
141impl TimCh4Pin<RemapDefault<TIM8>> for PC9<Alternate<PushPull>> {}
142#[cfg(feature = "xl")]
143impl TimCh1Pin<RemapDefault<TIM9>> for PA2<Alternate<PushPull>> {}
144#[cfg(feature = "xl")]
145impl TimCh2Pin<RemapDefault<TIM9>> for PA3<Alternate<PushPull>> {}
146#[cfg(feature = "xl")]
147impl TimCh1Pin<RemapFull<TIM9>> for PE5<Alternate<PushPull>> {}
148#[cfg(feature = "xl")]
149impl TimCh2Pin<RemapFull<TIM9>> for PE6<Alternate<PushPull>> {}
150
151// Register operations ------------
152
153#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity"))]
154impl RemapMode<TIM1> for RemapDefault<TIM1> {
155    fn remap(afio: &mut Afio) {
156        afio.mapr
157            .modify_mapr(unsafe { |_, w| w.tim1_remap().bits(0b00) });
158    }
159}
160#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity"))]
161impl RemapMode<TIM1> for RemapFull<TIM1> {
162    fn remap(afio: &mut Afio) {
163        afio.mapr
164            .modify_mapr(unsafe { |_, w| w.tim1_remap().bits(0b11) });
165    }
166}
167#[cfg(any(feature = "stm32f100", feature = "stm32f103", feature = "connectivity"))]
168impl RemapMode<TIM1> for RemapPartial1<TIM1> {
169    fn remap(afio: &mut Afio) {
170        afio.mapr
171            .modify_mapr(unsafe { |_, w| w.tim1_remap().bits(0b01) });
172    }
173}
174#[cfg(feature = "xl")]
175impl RemapMode<TIM10> for RemapDefault<TIM10> {
176    fn remap(afio: &mut Afio) {
177        afio.mapr2.modify_mapr(|_, w| w.tim10_remap().clear_bit());
178    }
179}
180#[cfg(feature = "xl")]
181impl RemapMode<TIM10> for RemapFull<TIM10> {
182    fn remap(afio: &mut Afio) {
183        afio.mapr2.modify_mapr(|_, w| w.tim10_remap().set_bit());
184    }
185}
186#[cfg(feature = "xl")]
187impl RemapMode<TIM11> for RemapDefault<TIM11> {
188    fn remap(afio: &mut Afio) {
189        afio.mapr2.modify_mapr(|_, w| w.tim11_remap().clear_bit());
190    }
191}
192#[cfg(feature = "xl")]
193impl RemapMode<TIM11> for RemapFull<TIM11> {
194    fn remap(afio: &mut Afio) {
195        afio.mapr2.modify_mapr(|_, w| w.tim11_remap().set_bit());
196    }
197}
198#[cfg(any(feature = "xl", all(feature = "stm32f100", feature = "high",)))]
199impl RemapMode<TIM12> for RemapDefault<TIM12> {
200    fn remap(afio: &mut Afio) {}
201}
202#[cfg(any(feature = "xl", all(feature = "stm32f100", feature = "high",)))]
203impl RemapMode<TIM13> for RemapDefault<TIM13> {
204    fn remap(afio: &mut Afio) {
205        afio.mapr2.modify_mapr(|_, w| w.tim13_remap().clear_bit());
206    }
207}
208#[cfg(any(feature = "xl", all(feature = "stm32f100", feature = "high",)))]
209impl RemapMode<TIM13> for RemapFull<TIM13> {
210    fn remap(afio: &mut Afio) {
211        afio.mapr2.modify_mapr(|_, w| w.tim13_remap().set_bit());
212    }
213}
214#[cfg(any(feature = "xl", all(feature = "stm32f100", feature = "high",)))]
215impl RemapMode<TIM14> for RemapDefault<TIM14> {
216    fn remap(afio: &mut Afio) {
217        afio.mapr2.modify_mapr(|_, w| w.tim14_remap().clear_bit());
218    }
219}
220#[cfg(any(feature = "xl", all(feature = "stm32f100", feature = "high",)))]
221impl RemapMode<TIM14> for RemapFull<TIM14> {
222    fn remap(afio: &mut Afio) {
223        afio.mapr2.modify_mapr(|_, w| w.tim14_remap().set_bit());
224    }
225}
226impl RemapMode<TIM2> for RemapDefault<TIM2> {
227    fn remap(afio: &mut Afio) {
228        afio.mapr
229            .modify_mapr(unsafe { |_, w| w.tim2_remap().bits(0b00) });
230    }
231}
232impl RemapMode<TIM2> for RemapFull<TIM2> {
233    fn remap(afio: &mut Afio) {
234        afio.mapr
235            .modify_mapr(unsafe { |_, w| w.tim2_remap().bits(0b11) });
236    }
237}
238impl RemapMode<TIM2> for RemapPartial1<TIM2> {
239    fn remap(afio: &mut Afio) {
240        afio.mapr
241            .modify_mapr(unsafe { |_, w| w.tim2_remap().bits(0b01) });
242    }
243}
244impl RemapMode<TIM2> for RemapPartial2<TIM2> {
245    fn remap(afio: &mut Afio) {
246        afio.mapr
247            .modify_mapr(unsafe { |_, w| w.tim2_remap().bits(0b10) });
248    }
249}
250impl RemapMode<TIM3> for RemapDefault<TIM3> {
251    fn remap(afio: &mut Afio) {
252        afio.mapr
253            .modify_mapr(unsafe { |_, w| w.tim3_remap().bits(0b00) });
254    }
255}
256impl RemapMode<TIM3> for RemapFull<TIM3> {
257    fn remap(afio: &mut Afio) {
258        afio.mapr
259            .modify_mapr(unsafe { |_, w| w.tim3_remap().bits(0b11) });
260    }
261}
262impl RemapMode<TIM3> for RemapPartial1<TIM3> {
263    fn remap(afio: &mut Afio) {
264        afio.mapr
265            .modify_mapr(unsafe { |_, w| w.tim3_remap().bits(0b10) });
266    }
267}
268#[cfg(feature = "medium")]
269impl RemapMode<TIM4> for RemapDefault<TIM4> {
270    fn remap(afio: &mut Afio) {
271        afio.mapr.modify_mapr(|_, w| w.tim4_remap().clear_bit());
272    }
273}
274#[cfg(feature = "medium")]
275impl RemapMode<TIM4> for RemapFull<TIM4> {
276    fn remap(afio: &mut Afio) {
277        afio.mapr.modify_mapr(|_, w| w.tim4_remap().set_bit());
278    }
279}
280#[cfg(any(feature = "high", feature = "connectivity"))]
281impl RemapMode<TIM5> for RemapDefault<TIM5> {
282    fn remap(afio: &mut Afio) {
283        afio.mapr.modify_mapr(|_, w| w.tim5ch4_iremap().clear_bit());
284    }
285}
286#[cfg(any(feature = "high", feature = "connectivity"))]
287impl RemapMode<TIM5> for RemapFull<TIM5> {
288    fn remap(afio: &mut Afio) {
289        afio.mapr.modify_mapr(|_, w| w.tim5ch4_iremap().set_bit());
290    }
291}
292#[cfg(all(feature = "stm32f103", feature = "high"))]
293impl RemapMode<TIM8> for RemapDefault<TIM8> {
294    fn remap(afio: &mut Afio) {}
295}
296#[cfg(feature = "xl")]
297impl RemapMode<TIM9> for RemapDefault<TIM9> {
298    fn remap(afio: &mut Afio) {
299        afio.mapr2.modify_mapr(|_, w| w.tim9_remap().clear_bit());
300    }
301}
302#[cfg(feature = "xl")]
303impl RemapMode<TIM9> for RemapFull<TIM9> {
304    fn remap(afio: &mut Afio) {
305        afio.mapr2.modify_mapr(|_, w| w.tim9_remap().set_bit());
306    }
307}
stm32f1_hal/afio/timer_remap.rs

stm32f1_hal/afio/
timer_remap.rs
