stm32f1_hal/common/uart/
uart_it.rs

1//! UART interrupt implementation
2
3use super::*;
4use crate::common::os::*;
5use crate::ringbuf::*;
6use embedded_io::{ErrorType, Read, Write};
7
8// TX -------------------------------------------------------------------------
9
10pub struct UartInterruptTx<U, T> {
11    uart: U,
12    w: Producer<u8>,
13    timeout: T,
14    flush_timeout: T,
15}
16
17impl<U, T> UartInterruptTx<U, T>
18where
19    U: UartPeriph,
20    T: Timeout,
21{
22    pub fn new(
23        uart: [U; 2],
24        buf_size: usize,
25        timeout: T,
26        flush_timeout: T,
27    ) -> (Self, UartInterruptTxHandler<U>) {
28        let [uart, u2] = uart;
29        let (w, r) = RingBuffer::<u8>::new(buf_size);
30        (
31            Self {
32                uart,
33                w,
34                timeout,
35                flush_timeout,
36            },
37            UartInterruptTxHandler::new(u2, r),
38        )
39    }
40}
41
42impl<U: UartPeriph, T: Timeout> ErrorType for UartInterruptTx<U, T> {
43    type Error = Error;
44}
45
46impl<U: UartPeriph, T: Timeout> Write for UartInterruptTx<U, T> {
47    fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
48        if buf.is_empty() {
49            return Err(Error::Other);
50        }
51
52        let mut t = self.timeout.start();
53        loop {
54            if let n @ 1.. = self.w.push_slice(buf) {
55                self.uart.set_interrupt(UartEvent::TxEmpty, true);
56                return Ok(n);
57            } else if !self.uart.is_interrupt_enable(UartEvent::TxEmpty) {
58                self.uart.set_interrupt(UartEvent::TxEmpty, true);
59            }
60
61            if t.timeout() {
62                break;
63            }
64            t.interval();
65        }
66        Err(Error::Busy)
67    }
68
69    fn flush(&mut self) -> Result<(), Self::Error> {
70        let mut t = self.flush_timeout.start();
71        loop {
72            if self.uart.is_tx_empty()
73                && self.uart.is_tx_complete()
74                && self.w.slots() == self.w.buffer().capacity()
75            {
76                return Ok(());
77            } else {
78                if t.timeout() {
79                    break;
80                } else if !self.uart.is_interrupt_enable(UartEvent::TxEmpty) {
81                    self.uart.set_interrupt(UartEvent::TxEmpty, true);
82                }
83                t.interval();
84            }
85        }
86        Err(Error::Other)
87    }
88}
89
90// TX interrupt -----------------
91
92pub struct UartInterruptTxHandler<U> {
93    uart: U,
94    r: Consumer<u8>,
95}
96
97impl<U> UartInterruptTxHandler<U>
98where
99    U: UartPeriph,
100{
101    pub fn new(uart: U, r: Consumer<u8>) -> Self {
102        Self { uart, r }
103    }
104}
105
106impl<U> UartInterruptTxHandler<U>
107where
108    U: UartPeriph,
109{
110    pub fn handler(&mut self) {
111        if let Ok(data) = self.r.peek() {
112            if self.uart.write(*data as u16).is_ok() {
113                self.r.pop().ok();
114            }
115        } else if self.uart.is_interrupt_enable(UartEvent::TxEmpty) {
116            self.uart.set_interrupt(UartEvent::TxEmpty, false);
117        }
118    }
119}
120
121// RX -------------------------------------------------------------------------
122
123pub struct UartInterruptRx<U, T> {
124    uart: U,
125    r: Consumer<u8>,
126    timeout: T,
127}
128
129impl<U, T> UartInterruptRx<U, T>
130where
131    U: UartPeriph,
132    T: Timeout,
133{
134    pub fn new(uart: [U; 2], buf_size: usize, timeout: T) -> (Self, UartInterruptRxHandler<U>) {
135        let [uart, u2] = uart;
136        let (w, r) = RingBuffer::<u8>::new(buf_size);
137        (
138            Self { uart, r, timeout },
139            UartInterruptRxHandler::new(u2, w),
140        )
141    }
142}
143
144impl<U: UartPeriph, T: Timeout> ErrorType for UartInterruptRx<U, T> {
145    type Error = Error;
146}
147
148impl<U, T> Read for UartInterruptRx<U, T>
149where
150    U: UartPeriph,
151    T: Timeout,
152{
153    fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
154        if buf.is_empty() {
155            return Err(Error::Other);
156        }
157
158        let mut t = self.timeout.start();
159        loop {
160            if let n @ 1.. = self.r.pop_slice(buf) {
161                return Ok(n);
162            } else if !self.uart.is_interrupt_enable(UartEvent::RxNotEmpty) {
163                self.uart.set_interrupt(UartEvent::RxNotEmpty, true);
164            }
165
166            if t.timeout() {
167                break;
168            }
169            t.interval();
170        }
171        Err(Error::Other)
172    }
173}
174
175// RX interrupt -----------------
176
177pub struct UartInterruptRxHandler<U> {
178    uart: U,
179    w: Producer<u8>,
180    // count: [u32; 10],
181}
182
183impl<U> UartInterruptRxHandler<U>
184where
185    U: UartPeriph,
186{
187    pub fn new(mut uart: U, w: Producer<u8>) -> Self {
188        uart.set_interrupt(UartEvent::RxNotEmpty, true);
189        Self {
190            uart,
191            w,
192            // count: [0; 10],
193        }
194    }
195
196    pub fn handler(&mut self) {
197        if let Ok(data) = self.uart.read() {
198            self.w.push(data as u8).ok();
199        }
200
201        // match self.uart.read() {
202        //     Ok(data) => match self.w.push(data as u8) {
203        //         Ok(()) => self.count[0] = self.count[0].saturating_add(1),
204        //         Err(_) => self.count[1] = self.count[1].saturating_add(1),
205        //     },
206        //     Err(nb::Error::WouldBlock) => self.count[2] = self.count[2].saturating_add(1),
207        //     Err(nb::Error::Other(e)) => match e {
208        //         Error::Overrun => self.count[3] = self.count[3].saturating_add(1),
209        //         Error::Other => self.count[4] = self.count[4].saturating_add(1),
210        //         Error::Noise => self.count[5] = self.count[5].saturating_add(1),
211        //         Error::FrameFormat => self.count[6] = self.count[6].saturating_add(1),
212        //         Error::Parity => self.count[7] = self.count[7].saturating_add(1),
213        //         Error::Busy => self.count[8] = self.count[8].saturating_add(1),
214        //     },
215        // }
216    }
217}
stm32f1_hal/common/uart/uart_it.rs

stm32f1_hal/common/uart/
uart_it.rs
