stm32f1_hal/common/timer/
mod.rs

1pub mod pwm;
2pub use pwm::*;
3pub mod counter;
4pub use counter::*;
5pub mod fix_timer;
6pub use fix_timer::*;
7pub mod delay;
8pub use delay::*;
9
10use crate::time::Hertz;
11
12pub trait PwmChannel: embedded_hal::pwm::SetDutyCycle {
13    fn config(&mut self, mode: PwmMode, polarity: PwmPolarity);
14    fn set_enable(&mut self, en: bool);
15}
16
17// ----------------------------------------------------------------------------
18
19pub trait GeneralTimer {
20    fn reset_config(&mut self);
21    fn enable_counter(&mut self);
22    fn disable_counter(&mut self);
23    fn is_counter_enabled(&self) -> bool;
24    fn reset_counter(&mut self);
25    fn enable_preload(&mut self, b: bool);
26    fn max_auto_reload() -> u32;
27    unsafe fn set_auto_reload_unchecked(&mut self, arr: u32);
28    fn set_auto_reload(&mut self, arr: u32) -> Result<(), Error>;
29    fn read_auto_reload(&self) -> u32;
30    fn set_prescaler(&mut self, psc: u16);
31    fn read_prescaler(&self) -> u16;
32    fn read_count(&self) -> u32;
33    fn trigger_update(&mut self);
34    fn stop_in_debug(&mut self, state: bool);
35    fn config_freq(&mut self, clock: Hertz, update_freq: Hertz);
36
37    fn clear_interrupt_flag(&mut self, event: Event);
38    fn listen_interrupt(&mut self, event: Event, b: bool);
39    fn get_interrupt_flag(&self) -> Event;
40    fn start_one_pulse(&mut self);
41}
42
43pub trait TimerDirection: GeneralTimer {
44    fn set_count_direction(&mut self, dir: CountDirection);
45}
46
47pub trait MasterTimer: GeneralTimer {
48    fn master_mode(&mut self, mode: MasterMode);
49}
50
51pub trait TimerWithPwm: GeneralTimer {
52    fn start_pwm(&mut self);
53    fn stop_pwm(&mut self);
54
55    fn preload_output_channel_in_mode(&mut self, channel: Channel, mode: PwmMode);
56    fn set_polarity(&mut self, channel: Channel, polarity: PwmPolarity);
57}
58
59pub trait TimerWithPwm1Ch: TimerWithPwm {
60    fn enable_ch1(&mut self, en: bool);
61    fn set_ch1_cc_value(&mut self, value: u32);
62    fn get_ch1_cc_value(&self) -> u32;
63}
64
65pub trait TimerWithPwm2Ch: TimerWithPwm1Ch {
66    fn enable_ch2(&mut self, en: bool);
67    fn set_ch2_cc_value(&mut self, value: u32);
68    fn get_ch2_cc_value(&self) -> u32;
69}
70
71pub trait TimerWithPwm3Ch: TimerWithPwm2Ch {
72    fn enable_ch3(&mut self, en: bool);
73    fn set_ch3_cc_value(&mut self, value: u32);
74    fn get_ch3_cc_value(&self) -> u32;
75}
76
77pub trait TimerWithPwm4Ch: TimerWithPwm3Ch {
78    fn enable_ch4(&mut self, en: bool);
79    fn set_ch4_cc_value(&mut self, value: u32);
80    fn get_ch4_cc_value(&self) -> u32;
81}
82
83// Enumerate ------------------------------------------------------------------
84
85#[derive(Clone, Copy, PartialEq, Eq)]
86pub enum Channel {
87    C1,
88    C2,
89    C3,
90    C4,
91}
92
93#[derive(Clone, Copy, Debug, PartialEq, Eq)]
94pub enum CountDirection {
95    Up,
96    Down,
97}
98
99#[derive(Clone, Copy, Debug, PartialEq, Eq)]
100pub enum PwmMode {
101    Mode1,
102    Mode2,
103}
104
105#[derive(Clone, Copy, Debug, PartialEq, Eq)]
106pub enum PwmPolarity {
107    ActiveHigh,
108    ActiveLow,
109}
110
111#[derive(Debug, Eq, PartialEq, Copy, Clone)]
112pub enum Error {
113    /// Timer is disabled
114    Disabled,
115    WrongAutoReload,
116}
117
118/// Interrupt events
119#[derive(Clone, Copy, PartialEq, Eq)]
120pub enum SysEvent {
121    /// [Timer] timed out / count down ended
122    Update,
123}
124
125bitflags::bitflags! {
126    pub struct Event: u32 {
127        const Update  = 1 << 0;
128        const C1 = 1 << 1;
129        const C2 = 1 << 2;
130        const C3 = 1 << 3;
131        const C4 = 1 << 4;
132    }
133}
134
135#[derive(Clone, Copy, Debug, PartialEq, Eq)]
136pub enum MasterMode {
137    ///0: The UG bit from the TIMx_EGR register is used as trigger output
138    Reset,
139    ///1: The counter enable signal, CNT_EN, is used as trigger output
140    Enable,
141    ///2: The update event is selected as trigger output
142    Update,
143    ///3: The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred
144    ComparePulse,
145    ///4: OC1REF signal is used as trigger output
146    CompareOc1,
147    ///5: OC2REF signal is used as trigger output
148    CompareOc2,
149    ///6: OC3REF signal is used as trigger output
150    CompareOc3,
151    ///7: OC4REF signal is used as trigger output
152    CompareOc4,
153}
stm32f1_hal/common/timer/mod.rs

stm32f1_hal/common/timer/
mod.rs
