stm32f1_hal/uart/
mod.rs

1#[cfg(any(all(feature = "stm32f103", feature = "high"), feature = "connectivity"))]
2pub mod uart4;
3#[cfg(any(all(feature = "stm32f103", feature = "high"), feature = "connectivity"))]
4pub mod uart5;
5pub mod usart1;
6pub mod usart2;
7pub mod usart3;
8pub use crate::common::uart::*;
9
10use crate::{
11    Steal,
12    afio::{RemapMode, uart_remap::*},
13    rcc::{BusClock, Enable, Reset},
14};
15
16use crate::Mcu;
17
18pub trait UartInit<U> {
19    fn constrain(self) -> Uart<U>;
20}
21
22pub trait UartPeriphExt: UartPeriph + BusClock + Enable + Reset {
23    fn config(&mut self, config: Config, mcu: &mut Mcu);
24    fn enable_comm(&mut self, tx: bool, rx: bool);
25    fn set_stop_bits(&mut self, bits: StopBits);
26}
27
28// wrapper
29pub struct Uart<U> {
30    uart: U,
31}
32
33#[allow(private_bounds)]
34impl<U: UartPeriphExt + Steal> Uart<U> {
35    pub fn into_tx_rx<REMAP: RemapMode<U>>(
36        mut self,
37        pins: (Option<impl UartTxPin<REMAP>>, Option<impl UartRxPin<REMAP>>),
38        config: Config,
39        mcu: &mut Mcu,
40    ) -> (Option<Tx<U>>, Option<Rx<U>>) {
41        REMAP::remap(&mut mcu.afio);
42        self.uart.config(config, mcu);
43        self.uart.enable_comm(pins.0.is_some(), pins.1.is_some());
44        unsafe {
45            (
46                pins.0
47                    .map(|_| Tx::new([self.uart.steal(), self.uart.steal()])),
48                pins.1
49                    .map(|_| Rx::new([self.uart.steal(), self.uart.steal()])),
50            )
51        }
52    }
53
54    pub fn get_idle_interrupt_handler(&self) -> UartIdleInterrupt<U> {
55        UartIdleInterrupt::new(unsafe { self.uart.steal() })
56    }
57}
stm32f1_hal/uart/mod.rs

stm32f1_hal/uart/
mod.rs
