stm32f1_hal/common/uart/
uart_it.rs

1//! UART interrupt implementation
2
3use super::*;
4use crate::os;
5use crate::ringbuf::*;
6use embedded_io::{ErrorType, Read, Write};
7
8// TX -------------------------------------------------------------------------
9
10pub struct UartInterruptTx<U> {
11    uart: U,
12    w: Producer<u8>,
13    transmit_retry_times: u32,
14    flush_retry_times: u32,
15}
16
17impl<U> UartInterruptTx<U>
18where
19    U: UartPeriph,
20{
21    pub(super) fn new(
22        uart: U,
23        w: Producer<u8>,
24        transmit_retry_times: u32,
25        flush_retry_times: u32,
26    ) -> Self {
27        Self {
28            uart,
29            w,
30            transmit_retry_times,
31            flush_retry_times,
32        }
33    }
34}
35
36impl<U: UartPeriph> ErrorType for UartInterruptTx<U> {
37    type Error = Error;
38}
39
40impl<U: UartPeriph> Write for UartInterruptTx<U> {
41    fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
42        if buf.len() == 0 {
43            return Err(Error::Other);
44        }
45
46        for _ in 0..=self.transmit_retry_times {
47            if let Some(n) = self.w.push_slice(buf) {
48                self.uart.set_interrupt(UartEvent::TxEmpty, true);
49                return Ok(n);
50            } else if !self.uart.is_interrupt_enable(UartEvent::TxEmpty) {
51                self.uart.set_interrupt(UartEvent::TxEmpty, true);
52            }
53            os::yield_cpu();
54        }
55        return Err(Error::Busy);
56    }
57
58    fn flush(&mut self) -> Result<(), Self::Error> {
59        let mut retry = 0;
60        let mut rest = 0;
61        loop {
62            if self.uart.is_tx_empty() && self.uart.is_tx_complete() {
63                return Ok(());
64            } else {
65                let tmp = self.w.slots();
66                if rest != tmp {
67                    rest = tmp;
68                    retry = 0;
69                } else {
70                    // unchanged
71                    retry += 1;
72                    if retry > self.flush_retry_times {
73                        return Err(Error::Other);
74                    } else if !self.uart.is_interrupt_enable(UartEvent::TxEmpty) {
75                        self.uart.set_interrupt(UartEvent::TxEmpty, true);
76                    }
77                }
78                os::yield_cpu();
79            }
80        }
81    }
82}
83
84// TX interrupt -----------------
85
86pub struct UartInterruptTxHandler<U> {
87    uart: U,
88    r: Consumer<u8>,
89}
90
91impl<U> UartInterruptTxHandler<U>
92where
93    U: UartPeriph,
94{
95    pub(super) fn new(uart: U, r: Consumer<u8>) -> Self {
96        Self { uart, r }
97    }
98}
99
100impl<U> UartInterruptTxHandler<U>
101where
102    U: UartPeriph,
103{
104    pub fn handler(&mut self) {
105        if let Ok(data) = self.r.peek() {
106            if self.uart.write(*data as u16).is_ok() {
107                self.r.pop().ok();
108            }
109        } else if self.uart.is_interrupt_enable(UartEvent::TxEmpty) {
110            self.uart.set_interrupt(UartEvent::TxEmpty, false);
111        }
112    }
113}
114
115// RX -------------------------------------------------------------------------
116
117pub struct UartInterruptRx<U> {
118    uart: U,
119    r: Consumer<u8>,
120    retry_times: u32,
121}
122
123impl<U> UartInterruptRx<U>
124where
125    U: UartPeriph,
126{
127    pub(super) fn new(uart: U, r: Consumer<u8>, retry_times: u32) -> Self {
128        Self {
129            uart,
130            r,
131            retry_times,
132        }
133    }
134}
135
136impl<U: UartPeriph> ErrorType for UartInterruptRx<U> {
137    type Error = Error;
138}
139
140impl<U> Read for UartInterruptRx<U>
141where
142    U: UartPeriph,
143{
144    fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
145        if buf.len() == 0 {
146            return Err(Error::Other);
147        }
148
149        for _ in 0..=self.retry_times {
150            if let Some(n) = self.r.pop_slice(buf) {
151                return Ok(n);
152            } else if !self.uart.is_interrupt_enable(UartEvent::RxNotEmpty) {
153                self.uart.set_interrupt(UartEvent::RxNotEmpty, true);
154            }
155            os::yield_cpu();
156        }
157        Err(Error::Other)
158    }
159}
160
161// RX interrupt -----------------
162
163pub struct UartInterruptRxHandler<U> {
164    uart: U,
165    w: Producer<u8>,
166    // count: [u32; 10],
167}
168
169impl<U> UartInterruptRxHandler<U>
170where
171    U: UartPeriph,
172{
173    pub(super) fn new(mut uart: U, w: Producer<u8>) -> Self {
174        uart.set_interrupt(UartEvent::RxNotEmpty, true);
175        Self {
176            uart,
177            w,
178            // count: [0; 10],
179        }
180    }
181
182    pub fn handler(&mut self) {
183        if let Ok(data) = self.uart.read() {
184            self.w.push(data as u8).ok();
185        }
186
187        // match self.uart.read() {
188        //     Ok(data) => match self.w.push(data as u8) {
189        //         Ok(()) => self.count[0] = self.count[0].saturating_add(1),
190        //         Err(_) => self.count[1] = self.count[1].saturating_add(1),
191        //     },
192        //     Err(nb::Error::WouldBlock) => self.count[2] = self.count[2].saturating_add(1),
193        //     Err(nb::Error::Other(e)) => match e {
194        //         Error::Overrun => self.count[3] = self.count[3].saturating_add(1),
195        //         Error::Other => self.count[4] = self.count[4].saturating_add(1),
196        //         Error::Noise => self.count[5] = self.count[5].saturating_add(1),
197        //         Error::FrameFormat => self.count[6] = self.count[6].saturating_add(1),
198        //         Error::Parity => self.count[7] = self.count[7].saturating_add(1),
199        //         Error::Busy => self.count[8] = self.count[8].saturating_add(1),
200        //     },
201        // }
202    }
203}
stm32f1_hal/common/uart/uart_it.rs

stm32f1_hal/common/uart/
uart_it.rs
