stm32f1_hal/timer/
timer7.rs

1type TimerX = pac::TIM7;
2type Width = u16;
3
4// Do NOT manually modify the code between begin and end!
5// It's synced by scripts/sync_code.py.
6// sync begin
7
8use super::*;
9use crate::{Mcu, pac};
10
11impl Instance for TimerX {}
12
13impl TimerInit<TimerX> for TimerX {
14    fn constrain(self, mcu: &mut Mcu) -> Timer<TimerX> {
15        Timer::new(self, mcu)
16    }
17}
18
19impl GeneralTimer for TimerX {
20    #[inline(always)]
21    fn reset_config(&mut self) {
22        self.cr1().reset();
23    }
24
25    #[inline(always)]
26    fn enable_counter(&mut self) {
27        self.cr1().modify(|_, w| w.cen().set_bit());
28    }
29
30    #[inline(always)]
31    fn disable_counter(&mut self) {
32        self.cr1().modify(|_, w| w.cen().clear_bit());
33    }
34
35    #[inline(always)]
36    fn is_counter_enabled(&self) -> bool {
37        self.cr1().read().cen().is_enabled()
38    }
39
40    #[inline(always)]
41    fn reset_counter(&mut self) {
42        self.cnt().reset();
43    }
44
45    #[inline(always)]
46    fn max_auto_reload() -> u32 {
47        Width::MAX as u32
48    }
49
50    #[inline(always)]
51    unsafe fn set_auto_reload_unchecked(&mut self, arr: u32) {
52        unsafe {
53            self.arr().write(|w| w.bits(arr));
54        }
55    }
56
57    #[inline(always)]
58    fn set_auto_reload(&mut self, arr: u32) -> Result<(), Error> {
59        // Note: Make it impossible to set the ARR value to 0, since this
60        // would cause an infinite loop.
61        if arr > 0 && arr <= Self::max_auto_reload() {
62            Ok(unsafe { self.set_auto_reload_unchecked(arr) })
63        } else {
64            Err(Error::WrongAutoReload)
65        }
66    }
67
68    #[inline(always)]
69    fn read_auto_reload(&self) -> u32 {
70        self.arr().read().bits()
71    }
72
73    #[inline(always)]
74    fn set_prescaler(&mut self, psc: u16) {
75        self.psc().write(|w| w.psc().set(psc));
76    }
77
78    #[inline(always)]
79    fn read_prescaler(&self) -> u16 {
80        self.psc().read().psc().bits()
81    }
82
83    #[inline(always)]
84    fn read_count(&self) -> u32 {
85        self.cnt().read().bits() as u32
86    }
87
88    #[inline(always)]
89    fn trigger_update(&mut self) {
90        // Sets the URS bit to prevent an interrupt from being triggered by
91        // the UG bit
92        self.cr1().modify(|_, w| w.urs().set_bit());
93        self.egr().write(|w| w.ug().set_bit());
94        self.cr1().modify(|_, w| w.urs().clear_bit());
95    }
96
97    #[inline]
98    fn config_freq(&mut self, clock: Hertz, count_freq: Hertz, update_freq: Hertz) {
99        let (prescaler, arr) = freq_to_presc_arr(clock.raw(), count_freq.raw(), update_freq.raw());
100        self.set_prescaler(prescaler as u16);
101        self.set_auto_reload(arr).unwrap();
102        // Trigger update event to load the registers
103        self.trigger_update();
104    }
105
106    #[inline(always)]
107    fn clear_interrupt_flag(&mut self, event: Event) {
108        self.sr()
109            .write(|w| unsafe { w.bits(0xffff & !event.bits()) });
110    }
111
112    #[inline(always)]
113    fn listen_interrupt(&mut self, event: Event, b: bool) {
114        self.dier().modify(|r, w| unsafe {
115            w.bits(if b {
116                r.bits() | event.bits()
117            } else {
118                r.bits() & !event.bits()
119            })
120        });
121    }
122
123    #[inline(always)]
124    fn get_interrupt_flag(&self) -> Event {
125        Event::from_bits_truncate(self.sr().read().bits())
126    }
127
128    #[inline(always)]
129    fn start_one_pulse(&mut self) {
130        self.cr1().modify(|_, w| w.opm().set_bit().cen().set_bit());
131    }
132
133    #[inline(always)]
134    fn stop_in_debug(&mut self, state: bool) {
135        let dbg = unsafe { DBG::steal() };
136        // sync dbg_t7
137        dbg.cr().modify(|_, w| w.dbg_tim7_stop().bit(state));
138        // sync dbg_end
139    }
140}
141
142impl GeneralTimerExt for TimerX {
143    #[inline(always)]
144    fn enable_preload(&mut self, b: bool) {
145        self.cr1().modify(|_, w| w.arpe().bit(b));
146    }
147}
148
149// sync master_type_t6
150type Mms = pac::tim6::cr2::MMS;
151// sync master
152impl MasterTimer for TimerX {
153    type Mms = Mms;
154    #[inline(always)]
155    fn master_mode(&mut self, mode: Self::Mms) {
156        self.cr2().modify(|_, w| w.mms().variant(mode));
157    }
158}
159
160// sync end
stm32f1_hal/timer/timer7.rs

stm32f1_hal/timer/
timer7.rs
