stm32f1_hal/timer/
timer11.rs

1#![allow(unused_variables)]
2type TimerX = pac::TIM11;
3type Width = u16;
4
5// sync begin
6
7use super::*;
8use crate::{Mcu, pac};
9
10impl Instance for TimerX {}
11
12impl TimerInit<TimerX> for TimerX {
13    fn constrain(self, mcu: &mut Mcu) -> Timer<TimerX> {
14        Timer::new(self, mcu)
15    }
16}
17
18impl GeneralTimer for TimerX {
19    #[inline(always)]
20    fn reset_config(&mut self) {
21        self.cr1().reset();
22    }
23
24    #[inline(always)]
25    fn enable_counter(&mut self) {
26        self.cr1().modify(|_, w| w.cen().set_bit());
27    }
28
29    #[inline(always)]
30    fn disable_counter(&mut self) {
31        self.cr1().modify(|_, w| w.cen().clear_bit());
32    }
33
34    #[inline(always)]
35    fn is_counter_enabled(&self) -> bool {
36        self.cr1().read().cen().is_enabled()
37    }
38
39    #[inline(always)]
40    fn reset_counter(&mut self) {
41        self.cnt().reset();
42    }
43
44    #[inline(always)]
45    fn max_auto_reload() -> u32 {
46        Width::MAX as u32
47    }
48
49    #[inline(always)]
50    unsafe fn set_auto_reload_unchecked(&mut self, arr: u32) {
51        unsafe {
52            self.arr().write(|w| w.bits(arr));
53        }
54    }
55
56    #[inline(always)]
57    fn set_auto_reload(&mut self, arr: u32) -> Result<(), Error> {
58        // Note: Make it impossible to set the ARR value to 0, since this
59        // would cause an infinite loop.
60        if arr > 0 && arr <= Self::max_auto_reload() {
61            Ok(unsafe { self.set_auto_reload_unchecked(arr) })
62        } else {
63            Err(Error::WrongAutoReload)
64        }
65    }
66
67    #[inline(always)]
68    fn read_auto_reload(&self) -> u32 {
69        self.arr().read().bits()
70    }
71
72    #[inline(always)]
73    fn set_prescaler(&mut self, psc: u16) {
74        self.psc().write(|w| w.psc().set(psc));
75    }
76
77    #[inline(always)]
78    fn read_prescaler(&self) -> u16 {
79        self.psc().read().psc().bits()
80    }
81
82    #[inline(always)]
83    fn read_count(&self) -> u32 {
84        self.cnt().read().bits() as u32
85    }
86
87    #[inline(always)]
88    fn trigger_update(&mut self) {
89        // Sets the URS bit to prevent an interrupt from being triggered by
90        // the UG bit
91        self.cr1().modify(|_, w| w.urs().set_bit());
92        self.egr().write(|w| w.ug().set_bit());
93        self.cr1().modify(|_, w| w.urs().clear_bit());
94    }
95
96    #[inline]
97    fn config_freq(&mut self, clock: Hertz, count_freq: Hertz, update_freq: Hertz) {
98        let (prescaler, arr) = freq_to_presc_arr(clock.raw(), count_freq.raw(), update_freq.raw());
99        self.set_prescaler(prescaler as u16);
100        self.set_auto_reload(arr).unwrap();
101        // Trigger update event to load the registers
102        self.trigger_update();
103    }
104
105    #[inline(always)]
106    fn clear_interrupt_flag(&mut self, event: Event) {
107        self.sr()
108            .write(|w| unsafe { w.bits(0xffff & !event.bits()) });
109    }
110
111    #[inline(always)]
112    fn listen_interrupt(&mut self, event: Event, b: bool) {
113        self.dier().modify(|r, w| unsafe {
114            w.bits(if b {
115                r.bits() | event.bits()
116            } else {
117                r.bits() & !event.bits()
118            })
119        });
120    }
121
122    #[inline(always)]
123    fn get_interrupt_flag(&self) -> Event {
124        Event::from_bits_truncate(self.sr().read().bits())
125    }
126
127    #[inline(always)]
128    fn start_one_pulse(&mut self) {
129        self.cr1().modify(|_, w| w.opm().set_bit().cen().set_bit());
130    }
131
132    #[inline(always)]
133    fn stop_in_debug(&mut self, state: bool) {
134        let dbg = unsafe { DBG::steal() };
135        // sync dbg_t11
136        // dbg.cr().modify(|_, w| w.dbg_tim11_stop().bit(state));
137        // sync dbg_end
138    }
139}
140
141impl GeneralTimerExt for TimerX {
142    #[inline(always)]
143    fn enable_preload(&mut self, b: bool) {
144        self.cr1().modify(|_, w| w.arpe().bit(b));
145    }
146}
147
148// sync pwm
149// PWM ------------------------------------------------------------------------
150
151impl TimerWithPwm for TimerX {
152    fn stop_pwm(&mut self) {
153        self.disable_counter();
154    }
155
156    // sync start_pwm
157
158    #[inline(always)]
159    fn start_pwm(&mut self) {
160        self.reset_counter();
161        self.enable_counter();
162    }
163
164    // sync pwm_cfg_1
165
166    #[inline(always)]
167    fn preload_output_channel_in_mode(&mut self, channel: Channel, mode: PwmMode) {
168        let mode = Ocm::from(mode);
169        match channel {
170            Channel::C1 => {
171                self.ccmr1_output()
172                    .modify(|_, w| w.oc1pe().set_bit().oc1m().set(mode as _));
173            }
174            _ => (),
175        }
176    }
177
178    fn set_polarity(&mut self, channel: Channel, polarity: PwmPolarity) {
179        match channel {
180            Channel::C1 => {
181                self.ccer()
182                    .modify(|_, w| w.cc1p().bit(polarity == PwmPolarity::ActiveLow));
183            }
184            _ => (),
185        }
186    }
187}
188
189// sync pwm_ch1
190// PWM Channels ---------------------------------------------------------------
191
192impl TimerWithPwm1Ch for TimerX {
193    #[inline(always)]
194    fn enable_ch1(&mut self, en: bool) {
195        self.ccer().modify(|_, w| w.cc1e().bit(en));
196    }
197
198    #[inline(always)]
199    fn set_ch1_cc_value(&mut self, value: u32) {
200        unsafe { self.ccr1().write(|w| w.bits(value)) };
201    }
202
203    #[inline(always)]
204    fn get_ch1_cc_value(&self) -> u32 {
205        self.ccr1().read().bits()
206    }
207}
208
209// sync end
stm32f1_hal/timer/timer11.rs

stm32f1_hal/timer/
timer11.rs
