Struct stm32f0xx_hal::stm32::tim3::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub cr1: Reg<CR1_SPEC>,
    pub cr2: Reg<CR2_SPEC>,
    pub smcr: Reg<SMCR_SPEC>,
    pub dier: Reg<DIER_SPEC>,
    pub sr: Reg<SR_SPEC>,
    pub egr: Reg<EGR_SPEC>,
    pub ccer: Reg<CCER_SPEC>,
    pub cnt: Reg<CNT_SPEC>,
    pub psc: Reg<PSC_SPEC>,
    pub arr: Reg<ARR_SPEC>,
    pub ccr1: Reg<CCR_SPEC>,
    pub ccr2: Reg<CCR_SPEC>,
    pub ccr3: Reg<CCR_SPEC>,
    pub ccr4: Reg<CCR_SPEC>,
    pub dcr: Reg<DCR_SPEC>,
    pub dmar: Reg<DMAR_SPEC>,
    // some fields omitted
}

Register block

Fields

cr1: Reg<CR1_SPEC>

0x00 - control register 1

cr2: Reg<CR2_SPEC>

0x04 - control register 2

smcr: Reg<SMCR_SPEC>

0x08 - slave mode control register

dier: Reg<DIER_SPEC>

0x0c - DMA/Interrupt enable register

sr: Reg<SR_SPEC>

0x10 - status register

egr: Reg<EGR_SPEC>

0x14 - event generation register

ccer: Reg<CCER_SPEC>

0x20 - capture/compare enable register

cnt: Reg<CNT_SPEC>

0x24 - counter

psc: Reg<PSC_SPEC>

0x28 - prescaler

arr: Reg<ARR_SPEC>

0x2c - auto-reload register

ccr1: Reg<CCR_SPEC>

0x34 - capture/compare register

ccr2: Reg<CCR_SPEC>

0x38 - capture/compare register

ccr3: Reg<CCR_SPEC>

0x3c - capture/compare register

ccr4: Reg<CCR_SPEC>

0x40 - capture/compare register

dcr: Reg<DCR_SPEC>

0x48 - DMA control register

dmar: Reg<DMAR_SPEC>

0x4c - DMA address for full transfer

Implementations

impl RegisterBlock

pub fn ccmr1_input(&self) -> &Reg<CCMR1_INPUT_SPEC>

0x18 - capture/compare mode register 1 (input mode)

pub fn ccmr1_output(&self) -> &Reg<CCMR1_OUTPUT_SPEC>

0x18 - capture/compare mode register 1 (output mode)

pub fn ccmr2_input(&self) -> &Reg<CCMR2_INPUT_SPEC>

0x1c - capture/compare mode register 2 (input mode)

pub fn ccmr2_output(&self) -> &Reg<CCMR2_OUTPUT_SPEC>

0x1c - capture/compare mode register 2 (output mode)