Enum stm32f0xx_hal::stm32::rcc::cfgr::PLLSRC_A [−][src]
#[repr(u8)]
pub enum PLLSRC_A {
HSI48_DIV_PREDIV,
HSI_DIV2,
HSI_DIV_PREDIV,
HSE_DIV_PREDIV,
}
Expand description
PLL input clock source
Value on reset: 0
Variants
3: HSI48 divided by PREDIV selected as PLL input clock
0: HSI divided by 2 selected as PLL input clock
1: HSI divided by PREDIV selected as PLL input clock
2: HSE divided by PREDIV selected as PLL input clock