Struct stm32f0xx_hal::pac::rcc::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 14 fields
pub cr: Reg<CR_SPEC>,
pub cfgr: Reg<CFGR_SPEC>,
pub cir: Reg<CIR_SPEC>,
pub apb2rstr: Reg<APB2RSTR_SPEC>,
pub apb1rstr: Reg<APB1RSTR_SPEC>,
pub ahbenr: Reg<AHBENR_SPEC>,
pub apb2enr: Reg<APB2ENR_SPEC>,
pub apb1enr: Reg<APB1ENR_SPEC>,
pub bdcr: Reg<BDCR_SPEC>,
pub csr: Reg<CSR_SPEC>,
pub ahbrstr: Reg<AHBRSTR_SPEC>,
pub cfgr2: Reg<CFGR2_SPEC>,
pub cfgr3: Reg<CFGR3_SPEC>,
pub cr2: Reg<CR2_SPEC>,
}
Expand description
Register block
Fields
cr: Reg<CR_SPEC>
0x00 - Clock control register
cfgr: Reg<CFGR_SPEC>
0x04 - Clock configuration register (RCC_CFGR)
cir: Reg<CIR_SPEC>
0x08 - Clock interrupt register (RCC_CIR)
apb2rstr: Reg<APB2RSTR_SPEC>
0x0c - APB2 peripheral reset register (RCC_APB2RSTR)
apb1rstr: Reg<APB1RSTR_SPEC>
0x10 - APB1 peripheral reset register (RCC_APB1RSTR)
ahbenr: Reg<AHBENR_SPEC>
0x14 - AHB Peripheral Clock enable register (RCC_AHBENR)
apb2enr: Reg<APB2ENR_SPEC>
0x18 - APB2 peripheral clock enable register (RCC_APB2ENR)
apb1enr: Reg<APB1ENR_SPEC>
0x1c - APB1 peripheral clock enable register (RCC_APB1ENR)
bdcr: Reg<BDCR_SPEC>
0x20 - Backup domain control register (RCC_BDCR)
csr: Reg<CSR_SPEC>
0x24 - Control/status register (RCC_CSR)
ahbrstr: Reg<AHBRSTR_SPEC>
0x28 - AHB peripheral reset register
cfgr2: Reg<CFGR2_SPEC>
0x2c - Clock configuration register 2
cfgr3: Reg<CFGR3_SPEC>
0x30 - Clock configuration register 3
cr2: Reg<CR2_SPEC>
0x34 - Clock control register 2