[][src]Enum stm32f0xx_hal::stm32::tim1::cr1::URS_A

pub enum URS_A {
    ANYEVENT,
    COUNTERONLY,
}

Update request source

Value on reset: 0

Variants

ANYEVENT

0: Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request

COUNTERONLY

1: Only counter overflow/underflow generates an update interrupt or DMA request

Trait Implementations

impl Clone for URS_A[src]

impl Copy for URS_A[src]

impl Debug for URS_A[src]

impl PartialEq<URS_A> for URS_A[src]

Auto Trait Implementations

impl Send for URS_A

impl Sync for URS_A

impl Unpin for URS_A

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized
[src]

impl<T> Borrow<T> for T where
    T: ?Sized
[src]

impl<T> BorrowMut<T> for T where
    T: ?Sized
[src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, 
[src]

impl<T> Same<T> for T

type Output = T

Should always be Self

impl<T, U> TryFrom<U> for T where
    U: Into<T>, 
[src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, 
[src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.