Struct stm32f0xx_hal::stm32::rcc::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub cr: Reg<u32, _CR>,
    pub cfgr: Reg<u32, _CFGR>,
    pub cir: Reg<u32, _CIR>,
    pub apb2rstr: Reg<u32, _APB2RSTR>,
    pub apb1rstr: Reg<u32, _APB1RSTR>,
    pub ahbenr: Reg<u32, _AHBENR>,
    pub apb2enr: Reg<u32, _APB2ENR>,
    pub apb1enr: Reg<u32, _APB1ENR>,
    pub bdcr: Reg<u32, _BDCR>,
    pub csr: Reg<u32, _CSR>,
    pub ahbrstr: Reg<u32, _AHBRSTR>,
    pub cfgr2: Reg<u32, _CFGR2>,
    pub cfgr3: Reg<u32, _CFGR3>,
    pub cr2: Reg<u32, _CR2>,
}

Register block

Fields

cr: Reg<u32, _CR>

0x00 - Clock control register

cfgr: Reg<u32, _CFGR>

0x04 - Clock configuration register (RCC_CFGR)

cir: Reg<u32, _CIR>

0x08 - Clock interrupt register (RCC_CIR)

apb2rstr: Reg<u32, _APB2RSTR>

0x0c - APB2 peripheral reset register (RCC_APB2RSTR)

apb1rstr: Reg<u32, _APB1RSTR>

0x10 - APB1 peripheral reset register (RCC_APB1RSTR)

ahbenr: Reg<u32, _AHBENR>

0x14 - AHB Peripheral Clock enable register (RCC_AHBENR)

apb2enr: Reg<u32, _APB2ENR>

0x18 - APB2 peripheral clock enable register (RCC_APB2ENR)

apb1enr: Reg<u32, _APB1ENR>

0x1c - APB1 peripheral clock enable register (RCC_APB1ENR)

bdcr: Reg<u32, _BDCR>

0x20 - Backup domain control register (RCC_BDCR)

csr: Reg<u32, _CSR>

0x24 - Control/status register (RCC_CSR)

ahbrstr: Reg<u32, _AHBRSTR>

0x28 - AHB peripheral reset register

cfgr2: Reg<u32, _CFGR2>

0x2c - Clock configuration register 2

cfgr3: Reg<u32, _CFGR3>

0x30 - Clock configuration register 3

cr2: Reg<u32, _CR2>

0x34 - Clock control register 2