[−][src]Struct stm32f0xx_hal::stm32::dac::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub cr: Reg<u32, _CR>,
    pub swtrigr: Reg<u32, _SWTRIGR>,
    pub dhr12r1: Reg<u32, _DHR12R1>,
    pub dhr12l1: Reg<u32, _DHR12L1>,
    pub dhr8r1: Reg<u32, _DHR8R1>,
    pub dhr12r2: Reg<u32, _DHR12R2>,
    pub dhr12l2: Reg<u32, _DHR12L2>,
    pub dhr8r2: Reg<u32, _DHR8R2>,
    pub dhr12rd: Reg<u32, _DHR12RD>,
    pub dhr12ld: Reg<u32, _DHR12LD>,
    pub dhr8rd: Reg<u32, _DHR8RD>,
    pub dor1: Reg<u32, _DOR1>,
    pub dor2: Reg<u32, _DOR2>,
    pub sr: Reg<u32, _SR>,
}

Register block

Fields

cr: Reg<u32, _CR>

0x00 - control register

swtrigr: Reg<u32, _SWTRIGR>

0x04 - software trigger register

dhr12r1: Reg<u32, _DHR12R1>

0x08 - channel1 12-bit right-aligned data holding register

dhr12l1: Reg<u32, _DHR12L1>

0x0c - channel1 12-bit left aligned data holding register

dhr8r1: Reg<u32, _DHR8R1>

0x10 - channel1 8-bit right aligned data holding register

dhr12r2: Reg<u32, _DHR12R2>

0x14 - DAC channel2 12-bit right-aligned data holding register

dhr12l2: Reg<u32, _DHR12L2>

0x18 - DAC channel2 12-bit left-aligned data holding register

dhr8r2: Reg<u32, _DHR8R2>

0x1c - DAC channel2 8-bit right-aligned data holding register

dhr12rd: Reg<u32, _DHR12RD>

0x20 - DHR12RD

dhr12ld: Reg<u32, _DHR12LD>

0x24 - Dual DAC 12-bit left-aligned data holding register

dhr8rd: Reg<u32, _DHR8RD>

0x28 - Dual DAC 8-bit right-aligned data holding register

dor1: Reg<u32, _DOR1>

0x2c - channel1 data output register

dor2: Reg<u32, _DOR2>

0x30 - DAC channel2 data output register

sr: Reg<u32, _SR>

0x34 - status register

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