1# ! [ doc = "Serial peripheral interface" ]
2# [ doc = r" Register block" ]
3# [ repr ( C ) ]
4pub struct Spi {
5 # [ doc = "0x00 - control register 1" ]
6 pub cr1: Cr1,
7 # [ doc = "0x04 - control register 2" ]
8 pub cr2: Cr2,
9 # [ doc = "0x08 - status register" ]
10 pub sr: Sr,
11 # [ doc = "0x0c - data register" ]
12 pub dr: Dr,
13 # [ doc = "0x10 - CRC polynomial register" ]
14 pub crcpr: Crcpr,
15 # [ doc = "0x14 - RX CRC register" ]
16 pub rxcrcr: Rxcrcr,
17 # [ doc = "0x18 - TX CRC register" ]
18 pub txcrcr: Txcrcr,
19 # [ doc = "0x1c - I2S configuration register" ]
20 pub i2scfgr: I2scfgr,
21 # [ doc = "0x20 - I2S prescaler register" ]
22 pub i2spr: I2spr,
23}
24
25# [ doc = "control register 1" ]
26# [ repr ( C ) ]
27pub struct Cr1 {
28 register: ::volatile_register::RW<u32>,
29}
30
31# [ doc = "control register 1" ]
32pub mod cr1 {
33 # [ doc = r" Value read from the register" ]
34 pub struct R {
35 bits: u32,
36 }
37 # [ doc = r" Value to write to the register" ]
38 pub struct W {
39 bits: u32,
40 }
41 impl super::Cr1 {
42 # [ doc = r" Modifies the contents of the register" ]
43 pub fn modify<F>(&mut self, f: F)
44 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
45 {
46 let bits = self.register.read();
47 let r = R { bits: bits };
48 let mut w = W { bits: bits };
49 f(&r, &mut w);
50 self.register.write(w.bits);
51 }
52 # [ doc = r" Reads the contents of the register" ]
53 pub fn read(&self) -> R {
54 R { bits: self.register.read() }
55 }
56 # [ doc = r" Writes to the register" ]
57 pub fn write<F>(&mut self, f: F)
58 where F: FnOnce(&mut W) -> &mut W
59 {
60 let mut w = W::reset_value();
61 f(&mut w);
62 self.register.write(w.bits);
63 }
64 }
65 # [ doc = "Value of the field BIDIMODE" ]
66 pub struct BidimodeR {
67 bits: u8,
68 }
69 impl BidimodeR {
70 # [ doc = r" Value of the field as raw bits" ]
71 pub fn bits(&self) -> u8 {
72 self.bits
73 }
74 }
75 # [ doc = "Value of the field BIDIOE" ]
76 pub struct BidioeR {
77 bits: u8,
78 }
79 impl BidioeR {
80 # [ doc = r" Value of the field as raw bits" ]
81 pub fn bits(&self) -> u8 {
82 self.bits
83 }
84 }
85 # [ doc = "Value of the field CRCEN" ]
86 pub struct CrcenR {
87 bits: u8,
88 }
89 impl CrcenR {
90 # [ doc = r" Value of the field as raw bits" ]
91 pub fn bits(&self) -> u8 {
92 self.bits
93 }
94 }
95 # [ doc = "Value of the field CRCNEXT" ]
96 pub struct CrcnextR {
97 bits: u8,
98 }
99 impl CrcnextR {
100 # [ doc = r" Value of the field as raw bits" ]
101 pub fn bits(&self) -> u8 {
102 self.bits
103 }
104 }
105 # [ doc = "Value of the field DFF" ]
106 pub struct DffR {
107 bits: u8,
108 }
109 impl DffR {
110 # [ doc = r" Value of the field as raw bits" ]
111 pub fn bits(&self) -> u8 {
112 self.bits
113 }
114 }
115 # [ doc = "Value of the field RXONLY" ]
116 pub struct RxonlyR {
117 bits: u8,
118 }
119 impl RxonlyR {
120 # [ doc = r" Value of the field as raw bits" ]
121 pub fn bits(&self) -> u8 {
122 self.bits
123 }
124 }
125 # [ doc = "Value of the field SSM" ]
126 pub struct SsmR {
127 bits: u8,
128 }
129 impl SsmR {
130 # [ doc = r" Value of the field as raw bits" ]
131 pub fn bits(&self) -> u8 {
132 self.bits
133 }
134 }
135 # [ doc = "Value of the field SSI" ]
136 pub struct SsiR {
137 bits: u8,
138 }
139 impl SsiR {
140 # [ doc = r" Value of the field as raw bits" ]
141 pub fn bits(&self) -> u8 {
142 self.bits
143 }
144 }
145 # [ doc = "Value of the field LSBFIRST" ]
146 pub struct LsbfirstR {
147 bits: u8,
148 }
149 impl LsbfirstR {
150 # [ doc = r" Value of the field as raw bits" ]
151 pub fn bits(&self) -> u8 {
152 self.bits
153 }
154 }
155 # [ doc = "Value of the field SPE" ]
156 pub struct SpeR {
157 bits: u8,
158 }
159 impl SpeR {
160 # [ doc = r" Value of the field as raw bits" ]
161 pub fn bits(&self) -> u8 {
162 self.bits
163 }
164 }
165 # [ doc = "Value of the field BR" ]
166 pub struct BrR {
167 bits: u8,
168 }
169 impl BrR {
170 # [ doc = r" Value of the field as raw bits" ]
171 pub fn bits(&self) -> u8 {
172 self.bits
173 }
174 }
175 # [ doc = "Value of the field MSTR" ]
176 pub struct MstrR {
177 bits: u8,
178 }
179 impl MstrR {
180 # [ doc = r" Value of the field as raw bits" ]
181 pub fn bits(&self) -> u8 {
182 self.bits
183 }
184 }
185 # [ doc = "Value of the field CPOL" ]
186 pub struct CpolR {
187 bits: u8,
188 }
189 impl CpolR {
190 # [ doc = r" Value of the field as raw bits" ]
191 pub fn bits(&self) -> u8 {
192 self.bits
193 }
194 }
195 # [ doc = "Value of the field CPHA" ]
196 pub struct CphaR {
197 bits: u8,
198 }
199 impl CphaR {
200 # [ doc = r" Value of the field as raw bits" ]
201 pub fn bits(&self) -> u8 {
202 self.bits
203 }
204 }
205 # [ doc = r" Proxy" ]
206 pub struct _BidimodeW<'a> {
207 register: &'a mut W,
208 }
209 impl<'a> _BidimodeW<'a> {
210 # [ doc = r" Writes raw `bits` to the field" ]
211 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
212 const MASK: u8 = 1;
213 const OFFSET: u8 = 15;
214 self.register.bits &= !((MASK as u32) << OFFSET);
215 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
216 self.register
217 }
218 }
219 # [ doc = r" Proxy" ]
220 pub struct _BidioeW<'a> {
221 register: &'a mut W,
222 }
223 impl<'a> _BidioeW<'a> {
224 # [ doc = r" Writes raw `bits` to the field" ]
225 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
226 const MASK: u8 = 1;
227 const OFFSET: u8 = 14;
228 self.register.bits &= !((MASK as u32) << OFFSET);
229 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
230 self.register
231 }
232 }
233 # [ doc = r" Proxy" ]
234 pub struct _CrcenW<'a> {
235 register: &'a mut W,
236 }
237 impl<'a> _CrcenW<'a> {
238 # [ doc = r" Writes raw `bits` to the field" ]
239 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
240 const MASK: u8 = 1;
241 const OFFSET: u8 = 13;
242 self.register.bits &= !((MASK as u32) << OFFSET);
243 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
244 self.register
245 }
246 }
247 # [ doc = r" Proxy" ]
248 pub struct _CrcnextW<'a> {
249 register: &'a mut W,
250 }
251 impl<'a> _CrcnextW<'a> {
252 # [ doc = r" Writes raw `bits` to the field" ]
253 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
254 const MASK: u8 = 1;
255 const OFFSET: u8 = 12;
256 self.register.bits &= !((MASK as u32) << OFFSET);
257 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
258 self.register
259 }
260 }
261 # [ doc = r" Proxy" ]
262 pub struct _DffW<'a> {
263 register: &'a mut W,
264 }
265 impl<'a> _DffW<'a> {
266 # [ doc = r" Writes raw `bits` to the field" ]
267 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
268 const MASK: u8 = 1;
269 const OFFSET: u8 = 11;
270 self.register.bits &= !((MASK as u32) << OFFSET);
271 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
272 self.register
273 }
274 }
275 # [ doc = r" Proxy" ]
276 pub struct _RxonlyW<'a> {
277 register: &'a mut W,
278 }
279 impl<'a> _RxonlyW<'a> {
280 # [ doc = r" Writes raw `bits` to the field" ]
281 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
282 const MASK: u8 = 1;
283 const OFFSET: u8 = 10;
284 self.register.bits &= !((MASK as u32) << OFFSET);
285 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
286 self.register
287 }
288 }
289 # [ doc = r" Proxy" ]
290 pub struct _SsmW<'a> {
291 register: &'a mut W,
292 }
293 impl<'a> _SsmW<'a> {
294 # [ doc = r" Writes raw `bits` to the field" ]
295 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
296 const MASK: u8 = 1;
297 const OFFSET: u8 = 9;
298 self.register.bits &= !((MASK as u32) << OFFSET);
299 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
300 self.register
301 }
302 }
303 # [ doc = r" Proxy" ]
304 pub struct _SsiW<'a> {
305 register: &'a mut W,
306 }
307 impl<'a> _SsiW<'a> {
308 # [ doc = r" Writes raw `bits` to the field" ]
309 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
310 const MASK: u8 = 1;
311 const OFFSET: u8 = 8;
312 self.register.bits &= !((MASK as u32) << OFFSET);
313 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
314 self.register
315 }
316 }
317 # [ doc = r" Proxy" ]
318 pub struct _LsbfirstW<'a> {
319 register: &'a mut W,
320 }
321 impl<'a> _LsbfirstW<'a> {
322 # [ doc = r" Writes raw `bits` to the field" ]
323 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
324 const MASK: u8 = 1;
325 const OFFSET: u8 = 7;
326 self.register.bits &= !((MASK as u32) << OFFSET);
327 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
328 self.register
329 }
330 }
331 # [ doc = r" Proxy" ]
332 pub struct _SpeW<'a> {
333 register: &'a mut W,
334 }
335 impl<'a> _SpeW<'a> {
336 # [ doc = r" Writes raw `bits` to the field" ]
337 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
338 const MASK: u8 = 1;
339 const OFFSET: u8 = 6;
340 self.register.bits &= !((MASK as u32) << OFFSET);
341 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
342 self.register
343 }
344 }
345 # [ doc = r" Proxy" ]
346 pub struct _BrW<'a> {
347 register: &'a mut W,
348 }
349 impl<'a> _BrW<'a> {
350 # [ doc = r" Writes raw `bits` to the field" ]
351 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
352 const MASK: u8 = 7;
353 const OFFSET: u8 = 3;
354 self.register.bits &= !((MASK as u32) << OFFSET);
355 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
356 self.register
357 }
358 }
359 # [ doc = r" Proxy" ]
360 pub struct _MstrW<'a> {
361 register: &'a mut W,
362 }
363 impl<'a> _MstrW<'a> {
364 # [ doc = r" Writes raw `bits` to the field" ]
365 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
366 const MASK: u8 = 1;
367 const OFFSET: u8 = 2;
368 self.register.bits &= !((MASK as u32) << OFFSET);
369 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
370 self.register
371 }
372 }
373 # [ doc = r" Proxy" ]
374 pub struct _CpolW<'a> {
375 register: &'a mut W,
376 }
377 impl<'a> _CpolW<'a> {
378 # [ doc = r" Writes raw `bits` to the field" ]
379 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
380 const MASK: u8 = 1;
381 const OFFSET: u8 = 1;
382 self.register.bits &= !((MASK as u32) << OFFSET);
383 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
384 self.register
385 }
386 }
387 # [ doc = r" Proxy" ]
388 pub struct _CphaW<'a> {
389 register: &'a mut W,
390 }
391 impl<'a> _CphaW<'a> {
392 # [ doc = r" Writes raw `bits` to the field" ]
393 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
394 const MASK: u8 = 1;
395 const OFFSET: u8 = 0;
396 self.register.bits &= !((MASK as u32) << OFFSET);
397 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
398 self.register
399 }
400 }
401 impl R {
402 # [ doc = r" Value of the register as raw bits" ]
403 pub fn bits(&self) -> u32 {
404 self.bits
405 }
406 fn _bidimode(&self) -> u8 {
407 const MASK: u8 = 1;
408 const OFFSET: u8 = 15;
409 ((self.bits >> OFFSET) & MASK as u32) as u8
410 }
411 # [ doc = "Bit 15 - Bidirectional data mode enable" ]
412 pub fn bidimode(&self) -> BidimodeR {
413 BidimodeR { bits: self._bidimode() }
414 }
415 fn _bidioe(&self) -> u8 {
416 const MASK: u8 = 1;
417 const OFFSET: u8 = 14;
418 ((self.bits >> OFFSET) & MASK as u32) as u8
419 }
420 # [ doc = "Bit 14 - Output enable in bidirectional mode" ]
421 pub fn bidioe(&self) -> BidioeR {
422 BidioeR { bits: self._bidioe() }
423 }
424 fn _crcen(&self) -> u8 {
425 const MASK: u8 = 1;
426 const OFFSET: u8 = 13;
427 ((self.bits >> OFFSET) & MASK as u32) as u8
428 }
429 # [ doc = "Bit 13 - Hardware CRC calculation enable" ]
430 pub fn crcen(&self) -> CrcenR {
431 CrcenR { bits: self._crcen() }
432 }
433 fn _crcnext(&self) -> u8 {
434 const MASK: u8 = 1;
435 const OFFSET: u8 = 12;
436 ((self.bits >> OFFSET) & MASK as u32) as u8
437 }
438 # [ doc = "Bit 12 - CRC transfer next" ]
439 pub fn crcnext(&self) -> CrcnextR {
440 CrcnextR { bits: self._crcnext() }
441 }
442 fn _dff(&self) -> u8 {
443 const MASK: u8 = 1;
444 const OFFSET: u8 = 11;
445 ((self.bits >> OFFSET) & MASK as u32) as u8
446 }
447 # [ doc = "Bit 11 - Data frame format" ]
448 pub fn dff(&self) -> DffR {
449 DffR { bits: self._dff() }
450 }
451 fn _rxonly(&self) -> u8 {
452 const MASK: u8 = 1;
453 const OFFSET: u8 = 10;
454 ((self.bits >> OFFSET) & MASK as u32) as u8
455 }
456 # [ doc = "Bit 10 - Receive only" ]
457 pub fn rxonly(&self) -> RxonlyR {
458 RxonlyR { bits: self._rxonly() }
459 }
460 fn _ssm(&self) -> u8 {
461 const MASK: u8 = 1;
462 const OFFSET: u8 = 9;
463 ((self.bits >> OFFSET) & MASK as u32) as u8
464 }
465 # [ doc = "Bit 9 - Software slave management" ]
466 pub fn ssm(&self) -> SsmR {
467 SsmR { bits: self._ssm() }
468 }
469 fn _ssi(&self) -> u8 {
470 const MASK: u8 = 1;
471 const OFFSET: u8 = 8;
472 ((self.bits >> OFFSET) & MASK as u32) as u8
473 }
474 # [ doc = "Bit 8 - Internal slave select" ]
475 pub fn ssi(&self) -> SsiR {
476 SsiR { bits: self._ssi() }
477 }
478 fn _lsbfirst(&self) -> u8 {
479 const MASK: u8 = 1;
480 const OFFSET: u8 = 7;
481 ((self.bits >> OFFSET) & MASK as u32) as u8
482 }
483 # [ doc = "Bit 7 - Frame format" ]
484 pub fn lsbfirst(&self) -> LsbfirstR {
485 LsbfirstR { bits: self._lsbfirst() }
486 }
487 fn _spe(&self) -> u8 {
488 const MASK: u8 = 1;
489 const OFFSET: u8 = 6;
490 ((self.bits >> OFFSET) & MASK as u32) as u8
491 }
492 # [ doc = "Bit 6 - SPI enable" ]
493 pub fn spe(&self) -> SpeR {
494 SpeR { bits: self._spe() }
495 }
496 fn _br(&self) -> u8 {
497 const MASK: u8 = 7;
498 const OFFSET: u8 = 3;
499 ((self.bits >> OFFSET) & MASK as u32) as u8
500 }
501 # [ doc = "Bits 3:5 - Baud rate control" ]
502 pub fn br(&self) -> BrR {
503 BrR { bits: self._br() }
504 }
505 fn _mstr(&self) -> u8 {
506 const MASK: u8 = 1;
507 const OFFSET: u8 = 2;
508 ((self.bits >> OFFSET) & MASK as u32) as u8
509 }
510 # [ doc = "Bit 2 - Master selection" ]
511 pub fn mstr(&self) -> MstrR {
512 MstrR { bits: self._mstr() }
513 }
514 fn _cpol(&self) -> u8 {
515 const MASK: u8 = 1;
516 const OFFSET: u8 = 1;
517 ((self.bits >> OFFSET) & MASK as u32) as u8
518 }
519 # [ doc = "Bit 1 - Clock polarity" ]
520 pub fn cpol(&self) -> CpolR {
521 CpolR { bits: self._cpol() }
522 }
523 fn _cpha(&self) -> u8 {
524 const MASK: u8 = 1;
525 const OFFSET: u8 = 0;
526 ((self.bits >> OFFSET) & MASK as u32) as u8
527 }
528 # [ doc = "Bit 0 - Clock phase" ]
529 pub fn cpha(&self) -> CphaR {
530 CphaR { bits: self._cpha() }
531 }
532 }
533 impl W {
534 # [ doc = r" Reset value of the register" ]
535 pub fn reset_value() -> W {
536 W { bits: 0 }
537 }
538 # [ doc = r" Writes raw `bits` to the register" ]
539 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
540 self.bits = bits;
541 self
542 }
543 # [ doc = "Bit 15 - Bidirectional data mode enable" ]
544 pub fn bidimode(&mut self) -> _BidimodeW {
545 _BidimodeW { register: self }
546 }
547 # [ doc = "Bit 14 - Output enable in bidirectional mode" ]
548 pub fn bidioe(&mut self) -> _BidioeW {
549 _BidioeW { register: self }
550 }
551 # [ doc = "Bit 13 - Hardware CRC calculation enable" ]
552 pub fn crcen(&mut self) -> _CrcenW {
553 _CrcenW { register: self }
554 }
555 # [ doc = "Bit 12 - CRC transfer next" ]
556 pub fn crcnext(&mut self) -> _CrcnextW {
557 _CrcnextW { register: self }
558 }
559 # [ doc = "Bit 11 - Data frame format" ]
560 pub fn dff(&mut self) -> _DffW {
561 _DffW { register: self }
562 }
563 # [ doc = "Bit 10 - Receive only" ]
564 pub fn rxonly(&mut self) -> _RxonlyW {
565 _RxonlyW { register: self }
566 }
567 # [ doc = "Bit 9 - Software slave management" ]
568 pub fn ssm(&mut self) -> _SsmW {
569 _SsmW { register: self }
570 }
571 # [ doc = "Bit 8 - Internal slave select" ]
572 pub fn ssi(&mut self) -> _SsiW {
573 _SsiW { register: self }
574 }
575 # [ doc = "Bit 7 - Frame format" ]
576 pub fn lsbfirst(&mut self) -> _LsbfirstW {
577 _LsbfirstW { register: self }
578 }
579 # [ doc = "Bit 6 - SPI enable" ]
580 pub fn spe(&mut self) -> _SpeW {
581 _SpeW { register: self }
582 }
583 # [ doc = "Bits 3:5 - Baud rate control" ]
584 pub fn br(&mut self) -> _BrW {
585 _BrW { register: self }
586 }
587 # [ doc = "Bit 2 - Master selection" ]
588 pub fn mstr(&mut self) -> _MstrW {
589 _MstrW { register: self }
590 }
591 # [ doc = "Bit 1 - Clock polarity" ]
592 pub fn cpol(&mut self) -> _CpolW {
593 _CpolW { register: self }
594 }
595 # [ doc = "Bit 0 - Clock phase" ]
596 pub fn cpha(&mut self) -> _CphaW {
597 _CphaW { register: self }
598 }
599 }
600}
601
602# [ doc = "control register 2" ]
603# [ repr ( C ) ]
604pub struct Cr2 {
605 register: ::volatile_register::RW<u32>,
606}
607
608# [ doc = "control register 2" ]
609pub mod cr2 {
610 # [ doc = r" Value read from the register" ]
611 pub struct R {
612 bits: u32,
613 }
614 # [ doc = r" Value to write to the register" ]
615 pub struct W {
616 bits: u32,
617 }
618 impl super::Cr2 {
619 # [ doc = r" Modifies the contents of the register" ]
620 pub fn modify<F>(&mut self, f: F)
621 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
622 {
623 let bits = self.register.read();
624 let r = R { bits: bits };
625 let mut w = W { bits: bits };
626 f(&r, &mut w);
627 self.register.write(w.bits);
628 }
629 # [ doc = r" Reads the contents of the register" ]
630 pub fn read(&self) -> R {
631 R { bits: self.register.read() }
632 }
633 # [ doc = r" Writes to the register" ]
634 pub fn write<F>(&mut self, f: F)
635 where F: FnOnce(&mut W) -> &mut W
636 {
637 let mut w = W::reset_value();
638 f(&mut w);
639 self.register.write(w.bits);
640 }
641 }
642 # [ doc = "Value of the field RXDMAEN" ]
643 pub struct RxdmaenR {
644 bits: u8,
645 }
646 impl RxdmaenR {
647 # [ doc = r" Value of the field as raw bits" ]
648 pub fn bits(&self) -> u8 {
649 self.bits
650 }
651 }
652 # [ doc = "Value of the field TXDMAEN" ]
653 pub struct TxdmaenR {
654 bits: u8,
655 }
656 impl TxdmaenR {
657 # [ doc = r" Value of the field as raw bits" ]
658 pub fn bits(&self) -> u8 {
659 self.bits
660 }
661 }
662 # [ doc = "Value of the field SSOE" ]
663 pub struct SsoeR {
664 bits: u8,
665 }
666 impl SsoeR {
667 # [ doc = r" Value of the field as raw bits" ]
668 pub fn bits(&self) -> u8 {
669 self.bits
670 }
671 }
672 # [ doc = "Value of the field NSSP" ]
673 pub struct NsspR {
674 bits: u8,
675 }
676 impl NsspR {
677 # [ doc = r" Value of the field as raw bits" ]
678 pub fn bits(&self) -> u8 {
679 self.bits
680 }
681 }
682 # [ doc = "Value of the field FRF" ]
683 pub struct FrfR {
684 bits: u8,
685 }
686 impl FrfR {
687 # [ doc = r" Value of the field as raw bits" ]
688 pub fn bits(&self) -> u8 {
689 self.bits
690 }
691 }
692 # [ doc = "Value of the field ERRIE" ]
693 pub struct ErrieR {
694 bits: u8,
695 }
696 impl ErrieR {
697 # [ doc = r" Value of the field as raw bits" ]
698 pub fn bits(&self) -> u8 {
699 self.bits
700 }
701 }
702 # [ doc = "Value of the field RXNEIE" ]
703 pub struct RxneieR {
704 bits: u8,
705 }
706 impl RxneieR {
707 # [ doc = r" Value of the field as raw bits" ]
708 pub fn bits(&self) -> u8 {
709 self.bits
710 }
711 }
712 # [ doc = "Value of the field TXEIE" ]
713 pub struct TxeieR {
714 bits: u8,
715 }
716 impl TxeieR {
717 # [ doc = r" Value of the field as raw bits" ]
718 pub fn bits(&self) -> u8 {
719 self.bits
720 }
721 }
722 # [ doc = "Value of the field DS" ]
723 pub struct DsR {
724 bits: u8,
725 }
726 impl DsR {
727 # [ doc = r" Value of the field as raw bits" ]
728 pub fn bits(&self) -> u8 {
729 self.bits
730 }
731 }
732 # [ doc = "Value of the field FRXTH" ]
733 pub struct FrxthR {
734 bits: u8,
735 }
736 impl FrxthR {
737 # [ doc = r" Value of the field as raw bits" ]
738 pub fn bits(&self) -> u8 {
739 self.bits
740 }
741 }
742 # [ doc = "Value of the field LDMA_RX" ]
743 pub struct LdmaRxR {
744 bits: u8,
745 }
746 impl LdmaRxR {
747 # [ doc = r" Value of the field as raw bits" ]
748 pub fn bits(&self) -> u8 {
749 self.bits
750 }
751 }
752 # [ doc = "Value of the field LDMA_TX" ]
753 pub struct LdmaTxR {
754 bits: u8,
755 }
756 impl LdmaTxR {
757 # [ doc = r" Value of the field as raw bits" ]
758 pub fn bits(&self) -> u8 {
759 self.bits
760 }
761 }
762 # [ doc = r" Proxy" ]
763 pub struct _RxdmaenW<'a> {
764 register: &'a mut W,
765 }
766 impl<'a> _RxdmaenW<'a> {
767 # [ doc = r" Writes raw `bits` to the field" ]
768 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
769 const MASK: u8 = 1;
770 const OFFSET: u8 = 0;
771 self.register.bits &= !((MASK as u32) << OFFSET);
772 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
773 self.register
774 }
775 }
776 # [ doc = r" Proxy" ]
777 pub struct _TxdmaenW<'a> {
778 register: &'a mut W,
779 }
780 impl<'a> _TxdmaenW<'a> {
781 # [ doc = r" Writes raw `bits` to the field" ]
782 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
783 const MASK: u8 = 1;
784 const OFFSET: u8 = 1;
785 self.register.bits &= !((MASK as u32) << OFFSET);
786 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
787 self.register
788 }
789 }
790 # [ doc = r" Proxy" ]
791 pub struct _SsoeW<'a> {
792 register: &'a mut W,
793 }
794 impl<'a> _SsoeW<'a> {
795 # [ doc = r" Writes raw `bits` to the field" ]
796 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
797 const MASK: u8 = 1;
798 const OFFSET: u8 = 2;
799 self.register.bits &= !((MASK as u32) << OFFSET);
800 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
801 self.register
802 }
803 }
804 # [ doc = r" Proxy" ]
805 pub struct _NsspW<'a> {
806 register: &'a mut W,
807 }
808 impl<'a> _NsspW<'a> {
809 # [ doc = r" Writes raw `bits` to the field" ]
810 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
811 const MASK: u8 = 1;
812 const OFFSET: u8 = 3;
813 self.register.bits &= !((MASK as u32) << OFFSET);
814 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
815 self.register
816 }
817 }
818 # [ doc = r" Proxy" ]
819 pub struct _FrfW<'a> {
820 register: &'a mut W,
821 }
822 impl<'a> _FrfW<'a> {
823 # [ doc = r" Writes raw `bits` to the field" ]
824 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
825 const MASK: u8 = 1;
826 const OFFSET: u8 = 4;
827 self.register.bits &= !((MASK as u32) << OFFSET);
828 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
829 self.register
830 }
831 }
832 # [ doc = r" Proxy" ]
833 pub struct _ErrieW<'a> {
834 register: &'a mut W,
835 }
836 impl<'a> _ErrieW<'a> {
837 # [ doc = r" Writes raw `bits` to the field" ]
838 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
839 const MASK: u8 = 1;
840 const OFFSET: u8 = 5;
841 self.register.bits &= !((MASK as u32) << OFFSET);
842 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
843 self.register
844 }
845 }
846 # [ doc = r" Proxy" ]
847 pub struct _RxneieW<'a> {
848 register: &'a mut W,
849 }
850 impl<'a> _RxneieW<'a> {
851 # [ doc = r" Writes raw `bits` to the field" ]
852 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
853 const MASK: u8 = 1;
854 const OFFSET: u8 = 6;
855 self.register.bits &= !((MASK as u32) << OFFSET);
856 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
857 self.register
858 }
859 }
860 # [ doc = r" Proxy" ]
861 pub struct _TxeieW<'a> {
862 register: &'a mut W,
863 }
864 impl<'a> _TxeieW<'a> {
865 # [ doc = r" Writes raw `bits` to the field" ]
866 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
867 const MASK: u8 = 1;
868 const OFFSET: u8 = 7;
869 self.register.bits &= !((MASK as u32) << OFFSET);
870 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
871 self.register
872 }
873 }
874 # [ doc = r" Proxy" ]
875 pub struct _DsW<'a> {
876 register: &'a mut W,
877 }
878 impl<'a> _DsW<'a> {
879 # [ doc = r" Writes raw `bits` to the field" ]
880 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
881 const MASK: u8 = 15;
882 const OFFSET: u8 = 8;
883 self.register.bits &= !((MASK as u32) << OFFSET);
884 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
885 self.register
886 }
887 }
888 # [ doc = r" Proxy" ]
889 pub struct _FrxthW<'a> {
890 register: &'a mut W,
891 }
892 impl<'a> _FrxthW<'a> {
893 # [ doc = r" Writes raw `bits` to the field" ]
894 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
895 const MASK: u8 = 1;
896 const OFFSET: u8 = 12;
897 self.register.bits &= !((MASK as u32) << OFFSET);
898 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
899 self.register
900 }
901 }
902 # [ doc = r" Proxy" ]
903 pub struct _LdmaRxW<'a> {
904 register: &'a mut W,
905 }
906 impl<'a> _LdmaRxW<'a> {
907 # [ doc = r" Writes raw `bits` to the field" ]
908 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
909 const MASK: u8 = 1;
910 const OFFSET: u8 = 13;
911 self.register.bits &= !((MASK as u32) << OFFSET);
912 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
913 self.register
914 }
915 }
916 # [ doc = r" Proxy" ]
917 pub struct _LdmaTxW<'a> {
918 register: &'a mut W,
919 }
920 impl<'a> _LdmaTxW<'a> {
921 # [ doc = r" Writes raw `bits` to the field" ]
922 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
923 const MASK: u8 = 1;
924 const OFFSET: u8 = 14;
925 self.register.bits &= !((MASK as u32) << OFFSET);
926 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
927 self.register
928 }
929 }
930 impl R {
931 # [ doc = r" Value of the register as raw bits" ]
932 pub fn bits(&self) -> u32 {
933 self.bits
934 }
935 fn _rxdmaen(&self) -> u8 {
936 const MASK: u8 = 1;
937 const OFFSET: u8 = 0;
938 ((self.bits >> OFFSET) & MASK as u32) as u8
939 }
940 # [ doc = "Bit 0 - Rx buffer DMA enable" ]
941 pub fn rxdmaen(&self) -> RxdmaenR {
942 RxdmaenR { bits: self._rxdmaen() }
943 }
944 fn _txdmaen(&self) -> u8 {
945 const MASK: u8 = 1;
946 const OFFSET: u8 = 1;
947 ((self.bits >> OFFSET) & MASK as u32) as u8
948 }
949 # [ doc = "Bit 1 - Tx buffer DMA enable" ]
950 pub fn txdmaen(&self) -> TxdmaenR {
951 TxdmaenR { bits: self._txdmaen() }
952 }
953 fn _ssoe(&self) -> u8 {
954 const MASK: u8 = 1;
955 const OFFSET: u8 = 2;
956 ((self.bits >> OFFSET) & MASK as u32) as u8
957 }
958 # [ doc = "Bit 2 - SS output enable" ]
959 pub fn ssoe(&self) -> SsoeR {
960 SsoeR { bits: self._ssoe() }
961 }
962 fn _nssp(&self) -> u8 {
963 const MASK: u8 = 1;
964 const OFFSET: u8 = 3;
965 ((self.bits >> OFFSET) & MASK as u32) as u8
966 }
967 # [ doc = "Bit 3 - NSS pulse management" ]
968 pub fn nssp(&self) -> NsspR {
969 NsspR { bits: self._nssp() }
970 }
971 fn _frf(&self) -> u8 {
972 const MASK: u8 = 1;
973 const OFFSET: u8 = 4;
974 ((self.bits >> OFFSET) & MASK as u32) as u8
975 }
976 # [ doc = "Bit 4 - Frame format" ]
977 pub fn frf(&self) -> FrfR {
978 FrfR { bits: self._frf() }
979 }
980 fn _errie(&self) -> u8 {
981 const MASK: u8 = 1;
982 const OFFSET: u8 = 5;
983 ((self.bits >> OFFSET) & MASK as u32) as u8
984 }
985 # [ doc = "Bit 5 - Error interrupt enable" ]
986 pub fn errie(&self) -> ErrieR {
987 ErrieR { bits: self._errie() }
988 }
989 fn _rxneie(&self) -> u8 {
990 const MASK: u8 = 1;
991 const OFFSET: u8 = 6;
992 ((self.bits >> OFFSET) & MASK as u32) as u8
993 }
994 # [ doc = "Bit 6 - RX buffer not empty interrupt enable" ]
995 pub fn rxneie(&self) -> RxneieR {
996 RxneieR { bits: self._rxneie() }
997 }
998 fn _txeie(&self) -> u8 {
999 const MASK: u8 = 1;
1000 const OFFSET: u8 = 7;
1001 ((self.bits >> OFFSET) & MASK as u32) as u8
1002 }
1003 # [ doc = "Bit 7 - Tx buffer empty interrupt enable" ]
1004 pub fn txeie(&self) -> TxeieR {
1005 TxeieR { bits: self._txeie() }
1006 }
1007 fn _ds(&self) -> u8 {
1008 const MASK: u8 = 15;
1009 const OFFSET: u8 = 8;
1010 ((self.bits >> OFFSET) & MASK as u32) as u8
1011 }
1012 # [ doc = "Bits 8:11 - Data size" ]
1013 pub fn ds(&self) -> DsR {
1014 DsR { bits: self._ds() }
1015 }
1016 fn _frxth(&self) -> u8 {
1017 const MASK: u8 = 1;
1018 const OFFSET: u8 = 12;
1019 ((self.bits >> OFFSET) & MASK as u32) as u8
1020 }
1021 # [ doc = "Bit 12 - FIFO reception threshold" ]
1022 pub fn frxth(&self) -> FrxthR {
1023 FrxthR { bits: self._frxth() }
1024 }
1025 fn _ldma_rx(&self) -> u8 {
1026 const MASK: u8 = 1;
1027 const OFFSET: u8 = 13;
1028 ((self.bits >> OFFSET) & MASK as u32) as u8
1029 }
1030 # [ doc = "Bit 13 - Last DMA transfer for reception" ]
1031 pub fn ldma_rx(&self) -> LdmaRxR {
1032 LdmaRxR { bits: self._ldma_rx() }
1033 }
1034 fn _ldma_tx(&self) -> u8 {
1035 const MASK: u8 = 1;
1036 const OFFSET: u8 = 14;
1037 ((self.bits >> OFFSET) & MASK as u32) as u8
1038 }
1039 # [ doc = "Bit 14 - Last DMA transfer for transmission" ]
1040 pub fn ldma_tx(&self) -> LdmaTxR {
1041 LdmaTxR { bits: self._ldma_tx() }
1042 }
1043 }
1044 impl W {
1045 # [ doc = r" Reset value of the register" ]
1046 pub fn reset_value() -> W {
1047 W { bits: 0 }
1048 }
1049 # [ doc = r" Writes raw `bits` to the register" ]
1050 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1051 self.bits = bits;
1052 self
1053 }
1054 # [ doc = "Bit 0 - Rx buffer DMA enable" ]
1055 pub fn rxdmaen(&mut self) -> _RxdmaenW {
1056 _RxdmaenW { register: self }
1057 }
1058 # [ doc = "Bit 1 - Tx buffer DMA enable" ]
1059 pub fn txdmaen(&mut self) -> _TxdmaenW {
1060 _TxdmaenW { register: self }
1061 }
1062 # [ doc = "Bit 2 - SS output enable" ]
1063 pub fn ssoe(&mut self) -> _SsoeW {
1064 _SsoeW { register: self }
1065 }
1066 # [ doc = "Bit 3 - NSS pulse management" ]
1067 pub fn nssp(&mut self) -> _NsspW {
1068 _NsspW { register: self }
1069 }
1070 # [ doc = "Bit 4 - Frame format" ]
1071 pub fn frf(&mut self) -> _FrfW {
1072 _FrfW { register: self }
1073 }
1074 # [ doc = "Bit 5 - Error interrupt enable" ]
1075 pub fn errie(&mut self) -> _ErrieW {
1076 _ErrieW { register: self }
1077 }
1078 # [ doc = "Bit 6 - RX buffer not empty interrupt enable" ]
1079 pub fn rxneie(&mut self) -> _RxneieW {
1080 _RxneieW { register: self }
1081 }
1082 # [ doc = "Bit 7 - Tx buffer empty interrupt enable" ]
1083 pub fn txeie(&mut self) -> _TxeieW {
1084 _TxeieW { register: self }
1085 }
1086 # [ doc = "Bits 8:11 - Data size" ]
1087 pub fn ds(&mut self) -> _DsW {
1088 _DsW { register: self }
1089 }
1090 # [ doc = "Bit 12 - FIFO reception threshold" ]
1091 pub fn frxth(&mut self) -> _FrxthW {
1092 _FrxthW { register: self }
1093 }
1094 # [ doc = "Bit 13 - Last DMA transfer for reception" ]
1095 pub fn ldma_rx(&mut self) -> _LdmaRxW {
1096 _LdmaRxW { register: self }
1097 }
1098 # [ doc = "Bit 14 - Last DMA transfer for transmission" ]
1099 pub fn ldma_tx(&mut self) -> _LdmaTxW {
1100 _LdmaTxW { register: self }
1101 }
1102 }
1103}
1104
1105# [ doc = "status register" ]
1106# [ repr ( C ) ]
1107pub struct Sr {
1108 register: ::volatile_register::RW<u32>,
1109}
1110
1111# [ doc = "status register" ]
1112pub mod sr {
1113 # [ doc = r" Value read from the register" ]
1114 pub struct R {
1115 bits: u32,
1116 }
1117 # [ doc = r" Value to write to the register" ]
1118 pub struct W {
1119 bits: u32,
1120 }
1121 impl super::Sr {
1122 # [ doc = r" Modifies the contents of the register" ]
1123 pub fn modify<F>(&mut self, f: F)
1124 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
1125 {
1126 let bits = self.register.read();
1127 let r = R { bits: bits };
1128 let mut w = W { bits: bits };
1129 f(&r, &mut w);
1130 self.register.write(w.bits);
1131 }
1132 # [ doc = r" Reads the contents of the register" ]
1133 pub fn read(&self) -> R {
1134 R { bits: self.register.read() }
1135 }
1136 # [ doc = r" Writes to the register" ]
1137 pub fn write<F>(&mut self, f: F)
1138 where F: FnOnce(&mut W) -> &mut W
1139 {
1140 let mut w = W::reset_value();
1141 f(&mut w);
1142 self.register.write(w.bits);
1143 }
1144 }
1145 # [ doc = "Value of the field RXNE" ]
1146 pub struct RxneR {
1147 bits: u8,
1148 }
1149 impl RxneR {
1150 # [ doc = r" Value of the field as raw bits" ]
1151 pub fn bits(&self) -> u8 {
1152 self.bits
1153 }
1154 }
1155 # [ doc = "Value of the field TXE" ]
1156 pub struct TxeR {
1157 bits: u8,
1158 }
1159 impl TxeR {
1160 # [ doc = r" Value of the field as raw bits" ]
1161 pub fn bits(&self) -> u8 {
1162 self.bits
1163 }
1164 }
1165 # [ doc = "Value of the field CHSIDE" ]
1166 pub struct ChsideR {
1167 bits: u8,
1168 }
1169 impl ChsideR {
1170 # [ doc = r" Value of the field as raw bits" ]
1171 pub fn bits(&self) -> u8 {
1172 self.bits
1173 }
1174 }
1175 # [ doc = "Value of the field UDR" ]
1176 pub struct UdrR {
1177 bits: u8,
1178 }
1179 impl UdrR {
1180 # [ doc = r" Value of the field as raw bits" ]
1181 pub fn bits(&self) -> u8 {
1182 self.bits
1183 }
1184 }
1185 # [ doc = "Value of the field CRCERR" ]
1186 pub struct CrcerrR {
1187 bits: u8,
1188 }
1189 impl CrcerrR {
1190 # [ doc = r" Value of the field as raw bits" ]
1191 pub fn bits(&self) -> u8 {
1192 self.bits
1193 }
1194 }
1195 # [ doc = "Value of the field MODF" ]
1196 pub struct ModfR {
1197 bits: u8,
1198 }
1199 impl ModfR {
1200 # [ doc = r" Value of the field as raw bits" ]
1201 pub fn bits(&self) -> u8 {
1202 self.bits
1203 }
1204 }
1205 # [ doc = "Value of the field OVR" ]
1206 pub struct OvrR {
1207 bits: u8,
1208 }
1209 impl OvrR {
1210 # [ doc = r" Value of the field as raw bits" ]
1211 pub fn bits(&self) -> u8 {
1212 self.bits
1213 }
1214 }
1215 # [ doc = "Value of the field BSY" ]
1216 pub struct BsyR {
1217 bits: u8,
1218 }
1219 impl BsyR {
1220 # [ doc = r" Value of the field as raw bits" ]
1221 pub fn bits(&self) -> u8 {
1222 self.bits
1223 }
1224 }
1225 # [ doc = "Value of the field TIFRFE" ]
1226 pub struct TifrfeR {
1227 bits: u8,
1228 }
1229 impl TifrfeR {
1230 # [ doc = r" Value of the field as raw bits" ]
1231 pub fn bits(&self) -> u8 {
1232 self.bits
1233 }
1234 }
1235 # [ doc = "Value of the field FRLVL" ]
1236 pub struct FrlvlR {
1237 bits: u8,
1238 }
1239 impl FrlvlR {
1240 # [ doc = r" Value of the field as raw bits" ]
1241 pub fn bits(&self) -> u8 {
1242 self.bits
1243 }
1244 }
1245 # [ doc = "Value of the field FTLVL" ]
1246 pub struct FtlvlR {
1247 bits: u8,
1248 }
1249 impl FtlvlR {
1250 # [ doc = r" Value of the field as raw bits" ]
1251 pub fn bits(&self) -> u8 {
1252 self.bits
1253 }
1254 }
1255 # [ doc = r" Proxy" ]
1256 pub struct _CrcerrW<'a> {
1257 register: &'a mut W,
1258 }
1259 impl<'a> _CrcerrW<'a> {
1260 # [ doc = r" Writes raw `bits` to the field" ]
1261 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1262 const MASK: u8 = 1;
1263 const OFFSET: u8 = 4;
1264 self.register.bits &= !((MASK as u32) << OFFSET);
1265 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1266 self.register
1267 }
1268 }
1269 impl R {
1270 # [ doc = r" Value of the register as raw bits" ]
1271 pub fn bits(&self) -> u32 {
1272 self.bits
1273 }
1274 fn _rxne(&self) -> u8 {
1275 const MASK: u8 = 1;
1276 const OFFSET: u8 = 0;
1277 ((self.bits >> OFFSET) & MASK as u32) as u8
1278 }
1279 # [ doc = "Bit 0 - Receive buffer not empty" ]
1280 pub fn rxne(&self) -> RxneR {
1281 RxneR { bits: self._rxne() }
1282 }
1283 fn _txe(&self) -> u8 {
1284 const MASK: u8 = 1;
1285 const OFFSET: u8 = 1;
1286 ((self.bits >> OFFSET) & MASK as u32) as u8
1287 }
1288 # [ doc = "Bit 1 - Transmit buffer empty" ]
1289 pub fn txe(&self) -> TxeR {
1290 TxeR { bits: self._txe() }
1291 }
1292 fn _chside(&self) -> u8 {
1293 const MASK: u8 = 1;
1294 const OFFSET: u8 = 2;
1295 ((self.bits >> OFFSET) & MASK as u32) as u8
1296 }
1297 # [ doc = "Bit 2 - Channel side" ]
1298 pub fn chside(&self) -> ChsideR {
1299 ChsideR { bits: self._chside() }
1300 }
1301 fn _udr(&self) -> u8 {
1302 const MASK: u8 = 1;
1303 const OFFSET: u8 = 3;
1304 ((self.bits >> OFFSET) & MASK as u32) as u8
1305 }
1306 # [ doc = "Bit 3 - Underrun flag" ]
1307 pub fn udr(&self) -> UdrR {
1308 UdrR { bits: self._udr() }
1309 }
1310 fn _crcerr(&self) -> u8 {
1311 const MASK: u8 = 1;
1312 const OFFSET: u8 = 4;
1313 ((self.bits >> OFFSET) & MASK as u32) as u8
1314 }
1315 # [ doc = "Bit 4 - CRC error flag" ]
1316 pub fn crcerr(&self) -> CrcerrR {
1317 CrcerrR { bits: self._crcerr() }
1318 }
1319 fn _modf(&self) -> u8 {
1320 const MASK: u8 = 1;
1321 const OFFSET: u8 = 5;
1322 ((self.bits >> OFFSET) & MASK as u32) as u8
1323 }
1324 # [ doc = "Bit 5 - Mode fault" ]
1325 pub fn modf(&self) -> ModfR {
1326 ModfR { bits: self._modf() }
1327 }
1328 fn _ovr(&self) -> u8 {
1329 const MASK: u8 = 1;
1330 const OFFSET: u8 = 6;
1331 ((self.bits >> OFFSET) & MASK as u32) as u8
1332 }
1333 # [ doc = "Bit 6 - Overrun flag" ]
1334 pub fn ovr(&self) -> OvrR {
1335 OvrR { bits: self._ovr() }
1336 }
1337 fn _bsy(&self) -> u8 {
1338 const MASK: u8 = 1;
1339 const OFFSET: u8 = 7;
1340 ((self.bits >> OFFSET) & MASK as u32) as u8
1341 }
1342 # [ doc = "Bit 7 - Busy flag" ]
1343 pub fn bsy(&self) -> BsyR {
1344 BsyR { bits: self._bsy() }
1345 }
1346 fn _tifrfe(&self) -> u8 {
1347 const MASK: u8 = 1;
1348 const OFFSET: u8 = 8;
1349 ((self.bits >> OFFSET) & MASK as u32) as u8
1350 }
1351 # [ doc = "Bit 8 - TI frame format error" ]
1352 pub fn tifrfe(&self) -> TifrfeR {
1353 TifrfeR { bits: self._tifrfe() }
1354 }
1355 fn _frlvl(&self) -> u8 {
1356 const MASK: u8 = 3;
1357 const OFFSET: u8 = 9;
1358 ((self.bits >> OFFSET) & MASK as u32) as u8
1359 }
1360 # [ doc = "Bits 9:10 - FIFO reception level" ]
1361 pub fn frlvl(&self) -> FrlvlR {
1362 FrlvlR { bits: self._frlvl() }
1363 }
1364 fn _ftlvl(&self) -> u8 {
1365 const MASK: u8 = 3;
1366 const OFFSET: u8 = 11;
1367 ((self.bits >> OFFSET) & MASK as u32) as u8
1368 }
1369 # [ doc = "Bits 11:12 - FIFO transmission level" ]
1370 pub fn ftlvl(&self) -> FtlvlR {
1371 FtlvlR { bits: self._ftlvl() }
1372 }
1373 }
1374 impl W {
1375 # [ doc = r" Reset value of the register" ]
1376 pub fn reset_value() -> W {
1377 W { bits: 2 }
1378 }
1379 # [ doc = r" Writes raw `bits` to the register" ]
1380 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1381 self.bits = bits;
1382 self
1383 }
1384 # [ doc = "Bit 4 - CRC error flag" ]
1385 pub fn crcerr(&mut self) -> _CrcerrW {
1386 _CrcerrW { register: self }
1387 }
1388 }
1389}
1390
1391# [ doc = "data register" ]
1392# [ repr ( C ) ]
1393pub struct Dr {
1394 register: ::volatile_register::RW<u32>,
1395}
1396
1397# [ doc = "data register" ]
1398pub mod dr {
1399 # [ doc = r" Value read from the register" ]
1400 pub struct R {
1401 bits: u32,
1402 }
1403 # [ doc = r" Value to write to the register" ]
1404 pub struct W {
1405 bits: u32,
1406 }
1407 impl super::Dr {
1408 # [ doc = r" Modifies the contents of the register" ]
1409 pub fn modify<F>(&mut self, f: F)
1410 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
1411 {
1412 let bits = self.register.read();
1413 let r = R { bits: bits };
1414 let mut w = W { bits: bits };
1415 f(&r, &mut w);
1416 self.register.write(w.bits);
1417 }
1418 # [ doc = r" Reads the contents of the register" ]
1419 pub fn read(&self) -> R {
1420 R { bits: self.register.read() }
1421 }
1422 # [ doc = r" Writes to the register" ]
1423 pub fn write<F>(&mut self, f: F)
1424 where F: FnOnce(&mut W) -> &mut W
1425 {
1426 let mut w = W::reset_value();
1427 f(&mut w);
1428 self.register.write(w.bits);
1429 }
1430 }
1431 # [ doc = "Value of the field DR" ]
1432 pub struct DrR {
1433 bits: u16,
1434 }
1435 impl DrR {
1436 # [ doc = r" Value of the field as raw bits" ]
1437 pub fn bits(&self) -> u16 {
1438 self.bits
1439 }
1440 }
1441 # [ doc = r" Proxy" ]
1442 pub struct _DrW<'a> {
1443 register: &'a mut W,
1444 }
1445 impl<'a> _DrW<'a> {
1446 # [ doc = r" Writes raw `bits` to the field" ]
1447 pub unsafe fn bits(self, bits: u16) -> &'a mut W {
1448 const MASK: u16 = 65535;
1449 const OFFSET: u8 = 0;
1450 self.register.bits &= !((MASK as u32) << OFFSET);
1451 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1452 self.register
1453 }
1454 }
1455 impl R {
1456 # [ doc = r" Value of the register as raw bits" ]
1457 pub fn bits(&self) -> u32 {
1458 self.bits
1459 }
1460 fn _dr(&self) -> u16 {
1461 const MASK: u16 = 65535;
1462 const OFFSET: u8 = 0;
1463 ((self.bits >> OFFSET) & MASK as u32) as u16
1464 }
1465 # [ doc = "Bits 0:15 - Data register" ]
1466 pub fn dr(&self) -> DrR {
1467 DrR { bits: self._dr() }
1468 }
1469 }
1470 impl W {
1471 # [ doc = r" Reset value of the register" ]
1472 pub fn reset_value() -> W {
1473 W { bits: 0 }
1474 }
1475 # [ doc = r" Writes raw `bits` to the register" ]
1476 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1477 self.bits = bits;
1478 self
1479 }
1480 # [ doc = "Bits 0:15 - Data register" ]
1481 pub fn dr(&mut self) -> _DrW {
1482 _DrW { register: self }
1483 }
1484 }
1485}
1486
1487# [ doc = "CRC polynomial register" ]
1488# [ repr ( C ) ]
1489pub struct Crcpr {
1490 register: ::volatile_register::RW<u32>,
1491}
1492
1493# [ doc = "CRC polynomial register" ]
1494pub mod crcpr {
1495 # [ doc = r" Value read from the register" ]
1496 pub struct R {
1497 bits: u32,
1498 }
1499 # [ doc = r" Value to write to the register" ]
1500 pub struct W {
1501 bits: u32,
1502 }
1503 impl super::Crcpr {
1504 # [ doc = r" Modifies the contents of the register" ]
1505 pub fn modify<F>(&mut self, f: F)
1506 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
1507 {
1508 let bits = self.register.read();
1509 let r = R { bits: bits };
1510 let mut w = W { bits: bits };
1511 f(&r, &mut w);
1512 self.register.write(w.bits);
1513 }
1514 # [ doc = r" Reads the contents of the register" ]
1515 pub fn read(&self) -> R {
1516 R { bits: self.register.read() }
1517 }
1518 # [ doc = r" Writes to the register" ]
1519 pub fn write<F>(&mut self, f: F)
1520 where F: FnOnce(&mut W) -> &mut W
1521 {
1522 let mut w = W::reset_value();
1523 f(&mut w);
1524 self.register.write(w.bits);
1525 }
1526 }
1527 # [ doc = "Value of the field CRCPOLY" ]
1528 pub struct CrcpolyR {
1529 bits: u16,
1530 }
1531 impl CrcpolyR {
1532 # [ doc = r" Value of the field as raw bits" ]
1533 pub fn bits(&self) -> u16 {
1534 self.bits
1535 }
1536 }
1537 # [ doc = r" Proxy" ]
1538 pub struct _CrcpolyW<'a> {
1539 register: &'a mut W,
1540 }
1541 impl<'a> _CrcpolyW<'a> {
1542 # [ doc = r" Writes raw `bits` to the field" ]
1543 pub unsafe fn bits(self, bits: u16) -> &'a mut W {
1544 const MASK: u16 = 65535;
1545 const OFFSET: u8 = 0;
1546 self.register.bits &= !((MASK as u32) << OFFSET);
1547 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1548 self.register
1549 }
1550 }
1551 impl R {
1552 # [ doc = r" Value of the register as raw bits" ]
1553 pub fn bits(&self) -> u32 {
1554 self.bits
1555 }
1556 fn _crcpoly(&self) -> u16 {
1557 const MASK: u16 = 65535;
1558 const OFFSET: u8 = 0;
1559 ((self.bits >> OFFSET) & MASK as u32) as u16
1560 }
1561 # [ doc = "Bits 0:15 - CRC polynomial register" ]
1562 pub fn crcpoly(&self) -> CrcpolyR {
1563 CrcpolyR { bits: self._crcpoly() }
1564 }
1565 }
1566 impl W {
1567 # [ doc = r" Reset value of the register" ]
1568 pub fn reset_value() -> W {
1569 W { bits: 7 }
1570 }
1571 # [ doc = r" Writes raw `bits` to the register" ]
1572 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1573 self.bits = bits;
1574 self
1575 }
1576 # [ doc = "Bits 0:15 - CRC polynomial register" ]
1577 pub fn crcpoly(&mut self) -> _CrcpolyW {
1578 _CrcpolyW { register: self }
1579 }
1580 }
1581}
1582
1583# [ doc = "RX CRC register" ]
1584# [ repr ( C ) ]
1585pub struct Rxcrcr {
1586 register: ::volatile_register::RO<u32>,
1587}
1588
1589# [ doc = "RX CRC register" ]
1590pub mod rxcrcr {
1591 # [ doc = r" Value read from the register" ]
1592 pub struct R {
1593 bits: u32,
1594 }
1595 impl super::Rxcrcr {
1596 # [ doc = r" Reads the contents of the register" ]
1597 pub fn read(&self) -> R {
1598 R { bits: self.register.read() }
1599 }
1600 }
1601 # [ doc = "Value of the field RxCRC" ]
1602 pub struct RxCrcR {
1603 bits: u16,
1604 }
1605 impl RxCrcR {
1606 # [ doc = r" Value of the field as raw bits" ]
1607 pub fn bits(&self) -> u16 {
1608 self.bits
1609 }
1610 }
1611 impl R {
1612 # [ doc = r" Value of the register as raw bits" ]
1613 pub fn bits(&self) -> u32 {
1614 self.bits
1615 }
1616 fn _rx_crc(&self) -> u16 {
1617 const MASK: u16 = 65535;
1618 const OFFSET: u8 = 0;
1619 ((self.bits >> OFFSET) & MASK as u32) as u16
1620 }
1621 # [ doc = "Bits 0:15 - Rx CRC register" ]
1622 pub fn rx_crc(&self) -> RxCrcR {
1623 RxCrcR { bits: self._rx_crc() }
1624 }
1625 }
1626}
1627
1628# [ doc = "TX CRC register" ]
1629# [ repr ( C ) ]
1630pub struct Txcrcr {
1631 register: ::volatile_register::RO<u32>,
1632}
1633
1634# [ doc = "TX CRC register" ]
1635pub mod txcrcr {
1636 # [ doc = r" Value read from the register" ]
1637 pub struct R {
1638 bits: u32,
1639 }
1640 impl super::Txcrcr {
1641 # [ doc = r" Reads the contents of the register" ]
1642 pub fn read(&self) -> R {
1643 R { bits: self.register.read() }
1644 }
1645 }
1646 # [ doc = "Value of the field TxCRC" ]
1647 pub struct TxCrcR {
1648 bits: u16,
1649 }
1650 impl TxCrcR {
1651 # [ doc = r" Value of the field as raw bits" ]
1652 pub fn bits(&self) -> u16 {
1653 self.bits
1654 }
1655 }
1656 impl R {
1657 # [ doc = r" Value of the register as raw bits" ]
1658 pub fn bits(&self) -> u32 {
1659 self.bits
1660 }
1661 fn _tx_crc(&self) -> u16 {
1662 const MASK: u16 = 65535;
1663 const OFFSET: u8 = 0;
1664 ((self.bits >> OFFSET) & MASK as u32) as u16
1665 }
1666 # [ doc = "Bits 0:15 - Tx CRC register" ]
1667 pub fn tx_crc(&self) -> TxCrcR {
1668 TxCrcR { bits: self._tx_crc() }
1669 }
1670 }
1671}
1672
1673# [ doc = "I2S configuration register" ]
1674# [ repr ( C ) ]
1675pub struct I2scfgr {
1676 register: ::volatile_register::RW<u32>,
1677}
1678
1679# [ doc = "I2S configuration register" ]
1680pub mod i2scfgr {
1681 # [ doc = r" Value read from the register" ]
1682 pub struct R {
1683 bits: u32,
1684 }
1685 # [ doc = r" Value to write to the register" ]
1686 pub struct W {
1687 bits: u32,
1688 }
1689 impl super::I2scfgr {
1690 # [ doc = r" Modifies the contents of the register" ]
1691 pub fn modify<F>(&mut self, f: F)
1692 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
1693 {
1694 let bits = self.register.read();
1695 let r = R { bits: bits };
1696 let mut w = W { bits: bits };
1697 f(&r, &mut w);
1698 self.register.write(w.bits);
1699 }
1700 # [ doc = r" Reads the contents of the register" ]
1701 pub fn read(&self) -> R {
1702 R { bits: self.register.read() }
1703 }
1704 # [ doc = r" Writes to the register" ]
1705 pub fn write<F>(&mut self, f: F)
1706 where F: FnOnce(&mut W) -> &mut W
1707 {
1708 let mut w = W::reset_value();
1709 f(&mut w);
1710 self.register.write(w.bits);
1711 }
1712 }
1713 # [ doc = "Value of the field I2SMOD" ]
1714 pub struct I2smodR {
1715 bits: u8,
1716 }
1717 impl I2smodR {
1718 # [ doc = r" Value of the field as raw bits" ]
1719 pub fn bits(&self) -> u8 {
1720 self.bits
1721 }
1722 }
1723 # [ doc = "Value of the field I2SE" ]
1724 pub struct I2seR {
1725 bits: u8,
1726 }
1727 impl I2seR {
1728 # [ doc = r" Value of the field as raw bits" ]
1729 pub fn bits(&self) -> u8 {
1730 self.bits
1731 }
1732 }
1733 # [ doc = "Value of the field I2SCFG" ]
1734 pub struct I2scfgR {
1735 bits: u8,
1736 }
1737 impl I2scfgR {
1738 # [ doc = r" Value of the field as raw bits" ]
1739 pub fn bits(&self) -> u8 {
1740 self.bits
1741 }
1742 }
1743 # [ doc = "Value of the field PCMSYNC" ]
1744 pub struct PcmsyncR {
1745 bits: u8,
1746 }
1747 impl PcmsyncR {
1748 # [ doc = r" Value of the field as raw bits" ]
1749 pub fn bits(&self) -> u8 {
1750 self.bits
1751 }
1752 }
1753 # [ doc = "Value of the field I2SSTD" ]
1754 pub struct I2sstdR {
1755 bits: u8,
1756 }
1757 impl I2sstdR {
1758 # [ doc = r" Value of the field as raw bits" ]
1759 pub fn bits(&self) -> u8 {
1760 self.bits
1761 }
1762 }
1763 # [ doc = "Value of the field CKPOL" ]
1764 pub struct CkpolR {
1765 bits: u8,
1766 }
1767 impl CkpolR {
1768 # [ doc = r" Value of the field as raw bits" ]
1769 pub fn bits(&self) -> u8 {
1770 self.bits
1771 }
1772 }
1773 # [ doc = "Value of the field DATLEN" ]
1774 pub struct DatlenR {
1775 bits: u8,
1776 }
1777 impl DatlenR {
1778 # [ doc = r" Value of the field as raw bits" ]
1779 pub fn bits(&self) -> u8 {
1780 self.bits
1781 }
1782 }
1783 # [ doc = "Value of the field CHLEN" ]
1784 pub struct ChlenR {
1785 bits: u8,
1786 }
1787 impl ChlenR {
1788 # [ doc = r" Value of the field as raw bits" ]
1789 pub fn bits(&self) -> u8 {
1790 self.bits
1791 }
1792 }
1793 # [ doc = r" Proxy" ]
1794 pub struct _I2smodW<'a> {
1795 register: &'a mut W,
1796 }
1797 impl<'a> _I2smodW<'a> {
1798 # [ doc = r" Writes raw `bits` to the field" ]
1799 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1800 const MASK: u8 = 1;
1801 const OFFSET: u8 = 11;
1802 self.register.bits &= !((MASK as u32) << OFFSET);
1803 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1804 self.register
1805 }
1806 }
1807 # [ doc = r" Proxy" ]
1808 pub struct _I2seW<'a> {
1809 register: &'a mut W,
1810 }
1811 impl<'a> _I2seW<'a> {
1812 # [ doc = r" Writes raw `bits` to the field" ]
1813 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1814 const MASK: u8 = 1;
1815 const OFFSET: u8 = 10;
1816 self.register.bits &= !((MASK as u32) << OFFSET);
1817 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1818 self.register
1819 }
1820 }
1821 # [ doc = r" Proxy" ]
1822 pub struct _I2scfgW<'a> {
1823 register: &'a mut W,
1824 }
1825 impl<'a> _I2scfgW<'a> {
1826 # [ doc = r" Writes raw `bits` to the field" ]
1827 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1828 const MASK: u8 = 3;
1829 const OFFSET: u8 = 8;
1830 self.register.bits &= !((MASK as u32) << OFFSET);
1831 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1832 self.register
1833 }
1834 }
1835 # [ doc = r" Proxy" ]
1836 pub struct _PcmsyncW<'a> {
1837 register: &'a mut W,
1838 }
1839 impl<'a> _PcmsyncW<'a> {
1840 # [ doc = r" Writes raw `bits` to the field" ]
1841 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1842 const MASK: u8 = 1;
1843 const OFFSET: u8 = 7;
1844 self.register.bits &= !((MASK as u32) << OFFSET);
1845 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1846 self.register
1847 }
1848 }
1849 # [ doc = r" Proxy" ]
1850 pub struct _I2sstdW<'a> {
1851 register: &'a mut W,
1852 }
1853 impl<'a> _I2sstdW<'a> {
1854 # [ doc = r" Writes raw `bits` to the field" ]
1855 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1856 const MASK: u8 = 3;
1857 const OFFSET: u8 = 4;
1858 self.register.bits &= !((MASK as u32) << OFFSET);
1859 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1860 self.register
1861 }
1862 }
1863 # [ doc = r" Proxy" ]
1864 pub struct _CkpolW<'a> {
1865 register: &'a mut W,
1866 }
1867 impl<'a> _CkpolW<'a> {
1868 # [ doc = r" Writes raw `bits` to the field" ]
1869 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1870 const MASK: u8 = 1;
1871 const OFFSET: u8 = 3;
1872 self.register.bits &= !((MASK as u32) << OFFSET);
1873 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1874 self.register
1875 }
1876 }
1877 # [ doc = r" Proxy" ]
1878 pub struct _DatlenW<'a> {
1879 register: &'a mut W,
1880 }
1881 impl<'a> _DatlenW<'a> {
1882 # [ doc = r" Writes raw `bits` to the field" ]
1883 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1884 const MASK: u8 = 3;
1885 const OFFSET: u8 = 1;
1886 self.register.bits &= !((MASK as u32) << OFFSET);
1887 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1888 self.register
1889 }
1890 }
1891 # [ doc = r" Proxy" ]
1892 pub struct _ChlenW<'a> {
1893 register: &'a mut W,
1894 }
1895 impl<'a> _ChlenW<'a> {
1896 # [ doc = r" Writes raw `bits` to the field" ]
1897 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1898 const MASK: u8 = 1;
1899 const OFFSET: u8 = 0;
1900 self.register.bits &= !((MASK as u32) << OFFSET);
1901 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1902 self.register
1903 }
1904 }
1905 impl R {
1906 # [ doc = r" Value of the register as raw bits" ]
1907 pub fn bits(&self) -> u32 {
1908 self.bits
1909 }
1910 fn _i2smod(&self) -> u8 {
1911 const MASK: u8 = 1;
1912 const OFFSET: u8 = 11;
1913 ((self.bits >> OFFSET) & MASK as u32) as u8
1914 }
1915 # [ doc = "Bit 11 - I2S mode selection" ]
1916 pub fn i2smod(&self) -> I2smodR {
1917 I2smodR { bits: self._i2smod() }
1918 }
1919 fn _i2se(&self) -> u8 {
1920 const MASK: u8 = 1;
1921 const OFFSET: u8 = 10;
1922 ((self.bits >> OFFSET) & MASK as u32) as u8
1923 }
1924 # [ doc = "Bit 10 - I2S Enable" ]
1925 pub fn i2se(&self) -> I2seR {
1926 I2seR { bits: self._i2se() }
1927 }
1928 fn _i2scfg(&self) -> u8 {
1929 const MASK: u8 = 3;
1930 const OFFSET: u8 = 8;
1931 ((self.bits >> OFFSET) & MASK as u32) as u8
1932 }
1933 # [ doc = "Bits 8:9 - I2S configuration mode" ]
1934 pub fn i2scfg(&self) -> I2scfgR {
1935 I2scfgR { bits: self._i2scfg() }
1936 }
1937 fn _pcmsync(&self) -> u8 {
1938 const MASK: u8 = 1;
1939 const OFFSET: u8 = 7;
1940 ((self.bits >> OFFSET) & MASK as u32) as u8
1941 }
1942 # [ doc = "Bit 7 - PCM frame synchronization" ]
1943 pub fn pcmsync(&self) -> PcmsyncR {
1944 PcmsyncR { bits: self._pcmsync() }
1945 }
1946 fn _i2sstd(&self) -> u8 {
1947 const MASK: u8 = 3;
1948 const OFFSET: u8 = 4;
1949 ((self.bits >> OFFSET) & MASK as u32) as u8
1950 }
1951 # [ doc = "Bits 4:5 - I2S standard selection" ]
1952 pub fn i2sstd(&self) -> I2sstdR {
1953 I2sstdR { bits: self._i2sstd() }
1954 }
1955 fn _ckpol(&self) -> u8 {
1956 const MASK: u8 = 1;
1957 const OFFSET: u8 = 3;
1958 ((self.bits >> OFFSET) & MASK as u32) as u8
1959 }
1960 # [ doc = "Bit 3 - Steady state clock polarity" ]
1961 pub fn ckpol(&self) -> CkpolR {
1962 CkpolR { bits: self._ckpol() }
1963 }
1964 fn _datlen(&self) -> u8 {
1965 const MASK: u8 = 3;
1966 const OFFSET: u8 = 1;
1967 ((self.bits >> OFFSET) & MASK as u32) as u8
1968 }
1969 # [ doc = "Bits 1:2 - Data length to be transferred" ]
1970 pub fn datlen(&self) -> DatlenR {
1971 DatlenR { bits: self._datlen() }
1972 }
1973 fn _chlen(&self) -> u8 {
1974 const MASK: u8 = 1;
1975 const OFFSET: u8 = 0;
1976 ((self.bits >> OFFSET) & MASK as u32) as u8
1977 }
1978 # [ doc = "Bit 0 - Channel length (number of bits per audio channel)" ]
1979 pub fn chlen(&self) -> ChlenR {
1980 ChlenR { bits: self._chlen() }
1981 }
1982 }
1983 impl W {
1984 # [ doc = r" Reset value of the register" ]
1985 pub fn reset_value() -> W {
1986 W { bits: 0 }
1987 }
1988 # [ doc = r" Writes raw `bits` to the register" ]
1989 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1990 self.bits = bits;
1991 self
1992 }
1993 # [ doc = "Bit 11 - I2S mode selection" ]
1994 pub fn i2smod(&mut self) -> _I2smodW {
1995 _I2smodW { register: self }
1996 }
1997 # [ doc = "Bit 10 - I2S Enable" ]
1998 pub fn i2se(&mut self) -> _I2seW {
1999 _I2seW { register: self }
2000 }
2001 # [ doc = "Bits 8:9 - I2S configuration mode" ]
2002 pub fn i2scfg(&mut self) -> _I2scfgW {
2003 _I2scfgW { register: self }
2004 }
2005 # [ doc = "Bit 7 - PCM frame synchronization" ]
2006 pub fn pcmsync(&mut self) -> _PcmsyncW {
2007 _PcmsyncW { register: self }
2008 }
2009 # [ doc = "Bits 4:5 - I2S standard selection" ]
2010 pub fn i2sstd(&mut self) -> _I2sstdW {
2011 _I2sstdW { register: self }
2012 }
2013 # [ doc = "Bit 3 - Steady state clock polarity" ]
2014 pub fn ckpol(&mut self) -> _CkpolW {
2015 _CkpolW { register: self }
2016 }
2017 # [ doc = "Bits 1:2 - Data length to be transferred" ]
2018 pub fn datlen(&mut self) -> _DatlenW {
2019 _DatlenW { register: self }
2020 }
2021 # [ doc = "Bit 0 - Channel length (number of bits per audio channel)" ]
2022 pub fn chlen(&mut self) -> _ChlenW {
2023 _ChlenW { register: self }
2024 }
2025 }
2026}
2027
2028# [ doc = "I2S prescaler register" ]
2029# [ repr ( C ) ]
2030pub struct I2spr {
2031 register: ::volatile_register::RW<u32>,
2032}
2033
2034# [ doc = "I2S prescaler register" ]
2035pub mod i2spr {
2036 # [ doc = r" Value read from the register" ]
2037 pub struct R {
2038 bits: u32,
2039 }
2040 # [ doc = r" Value to write to the register" ]
2041 pub struct W {
2042 bits: u32,
2043 }
2044 impl super::I2spr {
2045 # [ doc = r" Modifies the contents of the register" ]
2046 pub fn modify<F>(&mut self, f: F)
2047 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
2048 {
2049 let bits = self.register.read();
2050 let r = R { bits: bits };
2051 let mut w = W { bits: bits };
2052 f(&r, &mut w);
2053 self.register.write(w.bits);
2054 }
2055 # [ doc = r" Reads the contents of the register" ]
2056 pub fn read(&self) -> R {
2057 R { bits: self.register.read() }
2058 }
2059 # [ doc = r" Writes to the register" ]
2060 pub fn write<F>(&mut self, f: F)
2061 where F: FnOnce(&mut W) -> &mut W
2062 {
2063 let mut w = W::reset_value();
2064 f(&mut w);
2065 self.register.write(w.bits);
2066 }
2067 }
2068 # [ doc = "Value of the field MCKOE" ]
2069 pub struct MckoeR {
2070 bits: u8,
2071 }
2072 impl MckoeR {
2073 # [ doc = r" Value of the field as raw bits" ]
2074 pub fn bits(&self) -> u8 {
2075 self.bits
2076 }
2077 }
2078 # [ doc = "Value of the field ODD" ]
2079 pub struct OddR {
2080 bits: u8,
2081 }
2082 impl OddR {
2083 # [ doc = r" Value of the field as raw bits" ]
2084 pub fn bits(&self) -> u8 {
2085 self.bits
2086 }
2087 }
2088 # [ doc = "Value of the field I2SDIV" ]
2089 pub struct I2sdivR {
2090 bits: u8,
2091 }
2092 impl I2sdivR {
2093 # [ doc = r" Value of the field as raw bits" ]
2094 pub fn bits(&self) -> u8 {
2095 self.bits
2096 }
2097 }
2098 # [ doc = r" Proxy" ]
2099 pub struct _MckoeW<'a> {
2100 register: &'a mut W,
2101 }
2102 impl<'a> _MckoeW<'a> {
2103 # [ doc = r" Writes raw `bits` to the field" ]
2104 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2105 const MASK: u8 = 1;
2106 const OFFSET: u8 = 9;
2107 self.register.bits &= !((MASK as u32) << OFFSET);
2108 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2109 self.register
2110 }
2111 }
2112 # [ doc = r" Proxy" ]
2113 pub struct _OddW<'a> {
2114 register: &'a mut W,
2115 }
2116 impl<'a> _OddW<'a> {
2117 # [ doc = r" Writes raw `bits` to the field" ]
2118 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2119 const MASK: u8 = 1;
2120 const OFFSET: u8 = 8;
2121 self.register.bits &= !((MASK as u32) << OFFSET);
2122 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2123 self.register
2124 }
2125 }
2126 # [ doc = r" Proxy" ]
2127 pub struct _I2sdivW<'a> {
2128 register: &'a mut W,
2129 }
2130 impl<'a> _I2sdivW<'a> {
2131 # [ doc = r" Writes raw `bits` to the field" ]
2132 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2133 const MASK: u8 = 255;
2134 const OFFSET: u8 = 0;
2135 self.register.bits &= !((MASK as u32) << OFFSET);
2136 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2137 self.register
2138 }
2139 }
2140 impl R {
2141 # [ doc = r" Value of the register as raw bits" ]
2142 pub fn bits(&self) -> u32 {
2143 self.bits
2144 }
2145 fn _mckoe(&self) -> u8 {
2146 const MASK: u8 = 1;
2147 const OFFSET: u8 = 9;
2148 ((self.bits >> OFFSET) & MASK as u32) as u8
2149 }
2150 # [ doc = "Bit 9 - Master clock output enable" ]
2151 pub fn mckoe(&self) -> MckoeR {
2152 MckoeR { bits: self._mckoe() }
2153 }
2154 fn _odd(&self) -> u8 {
2155 const MASK: u8 = 1;
2156 const OFFSET: u8 = 8;
2157 ((self.bits >> OFFSET) & MASK as u32) as u8
2158 }
2159 # [ doc = "Bit 8 - Odd factor for the prescaler" ]
2160 pub fn odd(&self) -> OddR {
2161 OddR { bits: self._odd() }
2162 }
2163 fn _i2sdiv(&self) -> u8 {
2164 const MASK: u8 = 255;
2165 const OFFSET: u8 = 0;
2166 ((self.bits >> OFFSET) & MASK as u32) as u8
2167 }
2168 # [ doc = "Bits 0:7 - I2S Linear prescaler" ]
2169 pub fn i2sdiv(&self) -> I2sdivR {
2170 I2sdivR { bits: self._i2sdiv() }
2171 }
2172 }
2173 impl W {
2174 # [ doc = r" Reset value of the register" ]
2175 pub fn reset_value() -> W {
2176 W { bits: 16 }
2177 }
2178 # [ doc = r" Writes raw `bits` to the register" ]
2179 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
2180 self.bits = bits;
2181 self
2182 }
2183 # [ doc = "Bit 9 - Master clock output enable" ]
2184 pub fn mckoe(&mut self) -> _MckoeW {
2185 _MckoeW { register: self }
2186 }
2187 # [ doc = "Bit 8 - Odd factor for the prescaler" ]
2188 pub fn odd(&mut self) -> _OddW {
2189 _OddW { register: self }
2190 }
2191 # [ doc = "Bits 0:7 - I2S Linear prescaler" ]
2192 pub fn i2sdiv(&mut self) -> _I2sdivW {
2193 _I2sdivW { register: self }
2194 }
2195 }
2196}