1# ! [ doc = "Reset and clock control" ]
2# [ doc = r" Register block" ]
3# [ repr ( C ) ]
4pub struct Rcc {
5 # [ doc = "0x00 - Clock control register" ]
6 pub cr: Cr,
7 # [ doc = "0x04 - Clock configuration register (RCC_CFGR)" ]
8 pub cfgr: Cfgr,
9 # [ doc = "0x08 - Clock interrupt register (RCC_CIR)" ]
10 pub cir: Cir,
11 # [ doc = "0x0c - APB2 peripheral reset register (RCC_APB2RSTR)" ]
12 pub apb2rstr: Apb2rstr,
13 # [ doc = "0x10 - APB1 peripheral reset register (RCC_APB1RSTR)" ]
14 pub apb1rstr: Apb1rstr,
15 # [ doc = "0x14 - AHB Peripheral Clock enable register (RCC_AHBENR)" ]
16 pub ahbenr: Ahbenr,
17 # [ doc = "0x18 - APB2 peripheral clock enable register (RCC_APB2ENR)" ]
18 pub apb2enr: Apb2enr,
19 # [ doc = "0x1c - APB1 peripheral clock enable register (RCC_APB1ENR)" ]
20 pub apb1enr: Apb1enr,
21 # [ doc = "0x20 - Backup domain control register (RCC_BDCR)" ]
22 pub bdcr: Bdcr,
23 # [ doc = "0x24 - Control/status register (RCC_CSR)" ]
24 pub csr: Csr,
25 # [ doc = "0x28 - AHB peripheral reset register" ]
26 pub ahbrstr: Ahbrstr,
27 # [ doc = "0x2c - Clock configuration register 2" ]
28 pub cfgr2: Cfgr2,
29 # [ doc = "0x30 - Clock configuration register 3" ]
30 pub cfgr3: Cfgr3,
31 # [ doc = "0x34 - Clock control register 2" ]
32 pub cr2: Cr2,
33}
34
35# [ doc = "Clock control register" ]
36# [ repr ( C ) ]
37pub struct Cr {
38 register: ::volatile_register::RW<u32>,
39}
40
41# [ doc = "Clock control register" ]
42pub mod cr {
43 # [ doc = r" Value read from the register" ]
44 pub struct R {
45 bits: u32,
46 }
47 # [ doc = r" Value to write to the register" ]
48 pub struct W {
49 bits: u32,
50 }
51 impl super::Cr {
52 # [ doc = r" Modifies the contents of the register" ]
53 pub fn modify<F>(&mut self, f: F)
54 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
55 {
56 let bits = self.register.read();
57 let r = R { bits: bits };
58 let mut w = W { bits: bits };
59 f(&r, &mut w);
60 self.register.write(w.bits);
61 }
62 # [ doc = r" Reads the contents of the register" ]
63 pub fn read(&self) -> R {
64 R { bits: self.register.read() }
65 }
66 # [ doc = r" Writes to the register" ]
67 pub fn write<F>(&mut self, f: F)
68 where F: FnOnce(&mut W) -> &mut W
69 {
70 let mut w = W::reset_value();
71 f(&mut w);
72 self.register.write(w.bits);
73 }
74 }
75 # [ doc = "Value of the field HSION" ]
76 pub struct HsionR {
77 bits: u8,
78 }
79 impl HsionR {
80 # [ doc = r" Value of the field as raw bits" ]
81 pub fn bits(&self) -> u8 {
82 self.bits
83 }
84 }
85 # [ doc = "Value of the field HSIRDY" ]
86 pub struct HsirdyR {
87 bits: u8,
88 }
89 impl HsirdyR {
90 # [ doc = r" Value of the field as raw bits" ]
91 pub fn bits(&self) -> u8 {
92 self.bits
93 }
94 }
95 # [ doc = "Value of the field HSITRIM" ]
96 pub struct HsitrimR {
97 bits: u8,
98 }
99 impl HsitrimR {
100 # [ doc = r" Value of the field as raw bits" ]
101 pub fn bits(&self) -> u8 {
102 self.bits
103 }
104 }
105 # [ doc = "Value of the field HSICAL" ]
106 pub struct HsicalR {
107 bits: u8,
108 }
109 impl HsicalR {
110 # [ doc = r" Value of the field as raw bits" ]
111 pub fn bits(&self) -> u8 {
112 self.bits
113 }
114 }
115 # [ doc = "Value of the field HSEON" ]
116 pub struct HseonR {
117 bits: u8,
118 }
119 impl HseonR {
120 # [ doc = r" Value of the field as raw bits" ]
121 pub fn bits(&self) -> u8 {
122 self.bits
123 }
124 }
125 # [ doc = "Value of the field HSERDY" ]
126 pub struct HserdyR {
127 bits: u8,
128 }
129 impl HserdyR {
130 # [ doc = r" Value of the field as raw bits" ]
131 pub fn bits(&self) -> u8 {
132 self.bits
133 }
134 }
135 # [ doc = "Value of the field HSEBYP" ]
136 pub struct HsebypR {
137 bits: u8,
138 }
139 impl HsebypR {
140 # [ doc = r" Value of the field as raw bits" ]
141 pub fn bits(&self) -> u8 {
142 self.bits
143 }
144 }
145 # [ doc = "Value of the field CSSON" ]
146 pub struct CssonR {
147 bits: u8,
148 }
149 impl CssonR {
150 # [ doc = r" Value of the field as raw bits" ]
151 pub fn bits(&self) -> u8 {
152 self.bits
153 }
154 }
155 # [ doc = "Value of the field PLLON" ]
156 pub struct PllonR {
157 bits: u8,
158 }
159 impl PllonR {
160 # [ doc = r" Value of the field as raw bits" ]
161 pub fn bits(&self) -> u8 {
162 self.bits
163 }
164 }
165 # [ doc = "Value of the field PLLRDY" ]
166 pub struct PllrdyR {
167 bits: u8,
168 }
169 impl PllrdyR {
170 # [ doc = r" Value of the field as raw bits" ]
171 pub fn bits(&self) -> u8 {
172 self.bits
173 }
174 }
175 # [ doc = r" Proxy" ]
176 pub struct _HsionW<'a> {
177 register: &'a mut W,
178 }
179 impl<'a> _HsionW<'a> {
180 # [ doc = r" Writes raw `bits` to the field" ]
181 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
182 const MASK: u8 = 1;
183 const OFFSET: u8 = 0;
184 self.register.bits &= !((MASK as u32) << OFFSET);
185 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
186 self.register
187 }
188 }
189 # [ doc = r" Proxy" ]
190 pub struct _HsitrimW<'a> {
191 register: &'a mut W,
192 }
193 impl<'a> _HsitrimW<'a> {
194 # [ doc = r" Writes raw `bits` to the field" ]
195 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
196 const MASK: u8 = 31;
197 const OFFSET: u8 = 3;
198 self.register.bits &= !((MASK as u32) << OFFSET);
199 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
200 self.register
201 }
202 }
203 # [ doc = r" Proxy" ]
204 pub struct _HseonW<'a> {
205 register: &'a mut W,
206 }
207 impl<'a> _HseonW<'a> {
208 # [ doc = r" Writes raw `bits` to the field" ]
209 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
210 const MASK: u8 = 1;
211 const OFFSET: u8 = 16;
212 self.register.bits &= !((MASK as u32) << OFFSET);
213 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
214 self.register
215 }
216 }
217 # [ doc = r" Proxy" ]
218 pub struct _HsebypW<'a> {
219 register: &'a mut W,
220 }
221 impl<'a> _HsebypW<'a> {
222 # [ doc = r" Writes raw `bits` to the field" ]
223 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
224 const MASK: u8 = 1;
225 const OFFSET: u8 = 18;
226 self.register.bits &= !((MASK as u32) << OFFSET);
227 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
228 self.register
229 }
230 }
231 # [ doc = r" Proxy" ]
232 pub struct _CssonW<'a> {
233 register: &'a mut W,
234 }
235 impl<'a> _CssonW<'a> {
236 # [ doc = r" Writes raw `bits` to the field" ]
237 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
238 const MASK: u8 = 1;
239 const OFFSET: u8 = 19;
240 self.register.bits &= !((MASK as u32) << OFFSET);
241 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
242 self.register
243 }
244 }
245 # [ doc = r" Proxy" ]
246 pub struct _PllonW<'a> {
247 register: &'a mut W,
248 }
249 impl<'a> _PllonW<'a> {
250 # [ doc = r" Writes raw `bits` to the field" ]
251 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
252 const MASK: u8 = 1;
253 const OFFSET: u8 = 24;
254 self.register.bits &= !((MASK as u32) << OFFSET);
255 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
256 self.register
257 }
258 }
259 impl R {
260 # [ doc = r" Value of the register as raw bits" ]
261 pub fn bits(&self) -> u32 {
262 self.bits
263 }
264 fn _hsion(&self) -> u8 {
265 const MASK: u8 = 1;
266 const OFFSET: u8 = 0;
267 ((self.bits >> OFFSET) & MASK as u32) as u8
268 }
269 # [ doc = "Bit 0 - Internal High Speed clock enable" ]
270 pub fn hsion(&self) -> HsionR {
271 HsionR { bits: self._hsion() }
272 }
273 fn _hsirdy(&self) -> u8 {
274 const MASK: u8 = 1;
275 const OFFSET: u8 = 1;
276 ((self.bits >> OFFSET) & MASK as u32) as u8
277 }
278 # [ doc = "Bit 1 - Internal High Speed clock ready flag" ]
279 pub fn hsirdy(&self) -> HsirdyR {
280 HsirdyR { bits: self._hsirdy() }
281 }
282 fn _hsitrim(&self) -> u8 {
283 const MASK: u8 = 31;
284 const OFFSET: u8 = 3;
285 ((self.bits >> OFFSET) & MASK as u32) as u8
286 }
287 # [ doc = "Bits 3:7 - Internal High Speed clock trimming" ]
288 pub fn hsitrim(&self) -> HsitrimR {
289 HsitrimR { bits: self._hsitrim() }
290 }
291 fn _hsical(&self) -> u8 {
292 const MASK: u8 = 255;
293 const OFFSET: u8 = 8;
294 ((self.bits >> OFFSET) & MASK as u32) as u8
295 }
296 # [ doc = "Bits 8:15 - Internal High Speed clock Calibration" ]
297 pub fn hsical(&self) -> HsicalR {
298 HsicalR { bits: self._hsical() }
299 }
300 fn _hseon(&self) -> u8 {
301 const MASK: u8 = 1;
302 const OFFSET: u8 = 16;
303 ((self.bits >> OFFSET) & MASK as u32) as u8
304 }
305 # [ doc = "Bit 16 - External High Speed clock enable" ]
306 pub fn hseon(&self) -> HseonR {
307 HseonR { bits: self._hseon() }
308 }
309 fn _hserdy(&self) -> u8 {
310 const MASK: u8 = 1;
311 const OFFSET: u8 = 17;
312 ((self.bits >> OFFSET) & MASK as u32) as u8
313 }
314 # [ doc = "Bit 17 - External High Speed clock ready flag" ]
315 pub fn hserdy(&self) -> HserdyR {
316 HserdyR { bits: self._hserdy() }
317 }
318 fn _hsebyp(&self) -> u8 {
319 const MASK: u8 = 1;
320 const OFFSET: u8 = 18;
321 ((self.bits >> OFFSET) & MASK as u32) as u8
322 }
323 # [ doc = "Bit 18 - External High Speed clock Bypass" ]
324 pub fn hsebyp(&self) -> HsebypR {
325 HsebypR { bits: self._hsebyp() }
326 }
327 fn _csson(&self) -> u8 {
328 const MASK: u8 = 1;
329 const OFFSET: u8 = 19;
330 ((self.bits >> OFFSET) & MASK as u32) as u8
331 }
332 # [ doc = "Bit 19 - Clock Security System enable" ]
333 pub fn csson(&self) -> CssonR {
334 CssonR { bits: self._csson() }
335 }
336 fn _pllon(&self) -> u8 {
337 const MASK: u8 = 1;
338 const OFFSET: u8 = 24;
339 ((self.bits >> OFFSET) & MASK as u32) as u8
340 }
341 # [ doc = "Bit 24 - PLL enable" ]
342 pub fn pllon(&self) -> PllonR {
343 PllonR { bits: self._pllon() }
344 }
345 fn _pllrdy(&self) -> u8 {
346 const MASK: u8 = 1;
347 const OFFSET: u8 = 25;
348 ((self.bits >> OFFSET) & MASK as u32) as u8
349 }
350 # [ doc = "Bit 25 - PLL clock ready flag" ]
351 pub fn pllrdy(&self) -> PllrdyR {
352 PllrdyR { bits: self._pllrdy() }
353 }
354 }
355 impl W {
356 # [ doc = r" Reset value of the register" ]
357 pub fn reset_value() -> W {
358 W { bits: 131 }
359 }
360 # [ doc = r" Writes raw `bits` to the register" ]
361 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
362 self.bits = bits;
363 self
364 }
365 # [ doc = "Bit 0 - Internal High Speed clock enable" ]
366 pub fn hsion(&mut self) -> _HsionW {
367 _HsionW { register: self }
368 }
369 # [ doc = "Bits 3:7 - Internal High Speed clock trimming" ]
370 pub fn hsitrim(&mut self) -> _HsitrimW {
371 _HsitrimW { register: self }
372 }
373 # [ doc = "Bit 16 - External High Speed clock enable" ]
374 pub fn hseon(&mut self) -> _HseonW {
375 _HseonW { register: self }
376 }
377 # [ doc = "Bit 18 - External High Speed clock Bypass" ]
378 pub fn hsebyp(&mut self) -> _HsebypW {
379 _HsebypW { register: self }
380 }
381 # [ doc = "Bit 19 - Clock Security System enable" ]
382 pub fn csson(&mut self) -> _CssonW {
383 _CssonW { register: self }
384 }
385 # [ doc = "Bit 24 - PLL enable" ]
386 pub fn pllon(&mut self) -> _PllonW {
387 _PllonW { register: self }
388 }
389 }
390}
391
392# [ doc = "Clock configuration register (RCC_CFGR)" ]
393# [ repr ( C ) ]
394pub struct Cfgr {
395 register: ::volatile_register::RW<u32>,
396}
397
398# [ doc = "Clock configuration register (RCC_CFGR)" ]
399pub mod cfgr {
400 # [ doc = r" Value read from the register" ]
401 pub struct R {
402 bits: u32,
403 }
404 # [ doc = r" Value to write to the register" ]
405 pub struct W {
406 bits: u32,
407 }
408 impl super::Cfgr {
409 # [ doc = r" Modifies the contents of the register" ]
410 pub fn modify<F>(&mut self, f: F)
411 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
412 {
413 let bits = self.register.read();
414 let r = R { bits: bits };
415 let mut w = W { bits: bits };
416 f(&r, &mut w);
417 self.register.write(w.bits);
418 }
419 # [ doc = r" Reads the contents of the register" ]
420 pub fn read(&self) -> R {
421 R { bits: self.register.read() }
422 }
423 # [ doc = r" Writes to the register" ]
424 pub fn write<F>(&mut self, f: F)
425 where F: FnOnce(&mut W) -> &mut W
426 {
427 let mut w = W::reset_value();
428 f(&mut w);
429 self.register.write(w.bits);
430 }
431 }
432 # [ doc = "Value of the field SW" ]
433 pub struct SwR {
434 bits: u8,
435 }
436 impl SwR {
437 # [ doc = r" Value of the field as raw bits" ]
438 pub fn bits(&self) -> u8 {
439 self.bits
440 }
441 }
442 # [ doc = "Value of the field SWS" ]
443 pub struct SwsR {
444 bits: u8,
445 }
446 impl SwsR {
447 # [ doc = r" Value of the field as raw bits" ]
448 pub fn bits(&self) -> u8 {
449 self.bits
450 }
451 }
452 # [ doc = "Value of the field HPRE" ]
453 pub struct HpreR {
454 bits: u8,
455 }
456 impl HpreR {
457 # [ doc = r" Value of the field as raw bits" ]
458 pub fn bits(&self) -> u8 {
459 self.bits
460 }
461 }
462 # [ doc = "Value of the field PPRE" ]
463 pub struct PpreR {
464 bits: u8,
465 }
466 impl PpreR {
467 # [ doc = r" Value of the field as raw bits" ]
468 pub fn bits(&self) -> u8 {
469 self.bits
470 }
471 }
472 # [ doc = "Value of the field ADCPRE" ]
473 pub struct AdcpreR {
474 bits: u8,
475 }
476 impl AdcpreR {
477 # [ doc = r" Value of the field as raw bits" ]
478 pub fn bits(&self) -> u8 {
479 self.bits
480 }
481 }
482 # [ doc = "Value of the field PLLSRC" ]
483 pub struct PllsrcR {
484 bits: u8,
485 }
486 impl PllsrcR {
487 # [ doc = r" Value of the field as raw bits" ]
488 pub fn bits(&self) -> u8 {
489 self.bits
490 }
491 }
492 # [ doc = "Value of the field PLLXTPRE" ]
493 pub struct PllxtpreR {
494 bits: u8,
495 }
496 impl PllxtpreR {
497 # [ doc = r" Value of the field as raw bits" ]
498 pub fn bits(&self) -> u8 {
499 self.bits
500 }
501 }
502 # [ doc = "Value of the field PLLMUL" ]
503 pub struct PllmulR {
504 bits: u8,
505 }
506 impl PllmulR {
507 # [ doc = r" Value of the field as raw bits" ]
508 pub fn bits(&self) -> u8 {
509 self.bits
510 }
511 }
512 # [ doc = "Value of the field MCO" ]
513 pub struct McoR {
514 bits: u8,
515 }
516 impl McoR {
517 # [ doc = r" Value of the field as raw bits" ]
518 pub fn bits(&self) -> u8 {
519 self.bits
520 }
521 }
522 # [ doc = "Value of the field MCOPRE" ]
523 pub struct McopreR {
524 bits: u8,
525 }
526 impl McopreR {
527 # [ doc = r" Value of the field as raw bits" ]
528 pub fn bits(&self) -> u8 {
529 self.bits
530 }
531 }
532 # [ doc = "Value of the field PLLNODIV" ]
533 pub struct PllnodivR {
534 bits: u8,
535 }
536 impl PllnodivR {
537 # [ doc = r" Value of the field as raw bits" ]
538 pub fn bits(&self) -> u8 {
539 self.bits
540 }
541 }
542 # [ doc = r" Proxy" ]
543 pub struct _SwW<'a> {
544 register: &'a mut W,
545 }
546 impl<'a> _SwW<'a> {
547 # [ doc = r" Writes raw `bits` to the field" ]
548 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
549 const MASK: u8 = 3;
550 const OFFSET: u8 = 0;
551 self.register.bits &= !((MASK as u32) << OFFSET);
552 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
553 self.register
554 }
555 }
556 # [ doc = r" Proxy" ]
557 pub struct _HpreW<'a> {
558 register: &'a mut W,
559 }
560 impl<'a> _HpreW<'a> {
561 # [ doc = r" Writes raw `bits` to the field" ]
562 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
563 const MASK: u8 = 15;
564 const OFFSET: u8 = 4;
565 self.register.bits &= !((MASK as u32) << OFFSET);
566 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
567 self.register
568 }
569 }
570 # [ doc = r" Proxy" ]
571 pub struct _PpreW<'a> {
572 register: &'a mut W,
573 }
574 impl<'a> _PpreW<'a> {
575 # [ doc = r" Writes raw `bits` to the field" ]
576 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
577 const MASK: u8 = 7;
578 const OFFSET: u8 = 8;
579 self.register.bits &= !((MASK as u32) << OFFSET);
580 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
581 self.register
582 }
583 }
584 # [ doc = r" Proxy" ]
585 pub struct _AdcpreW<'a> {
586 register: &'a mut W,
587 }
588 impl<'a> _AdcpreW<'a> {
589 # [ doc = r" Writes raw `bits` to the field" ]
590 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
591 const MASK: u8 = 1;
592 const OFFSET: u8 = 14;
593 self.register.bits &= !((MASK as u32) << OFFSET);
594 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
595 self.register
596 }
597 }
598 # [ doc = r" Proxy" ]
599 pub struct _PllsrcW<'a> {
600 register: &'a mut W,
601 }
602 impl<'a> _PllsrcW<'a> {
603 # [ doc = r" Writes raw `bits` to the field" ]
604 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
605 const MASK: u8 = 3;
606 const OFFSET: u8 = 15;
607 self.register.bits &= !((MASK as u32) << OFFSET);
608 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
609 self.register
610 }
611 }
612 # [ doc = r" Proxy" ]
613 pub struct _PllxtpreW<'a> {
614 register: &'a mut W,
615 }
616 impl<'a> _PllxtpreW<'a> {
617 # [ doc = r" Writes raw `bits` to the field" ]
618 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
619 const MASK: u8 = 1;
620 const OFFSET: u8 = 17;
621 self.register.bits &= !((MASK as u32) << OFFSET);
622 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
623 self.register
624 }
625 }
626 # [ doc = r" Proxy" ]
627 pub struct _PllmulW<'a> {
628 register: &'a mut W,
629 }
630 impl<'a> _PllmulW<'a> {
631 # [ doc = r" Writes raw `bits` to the field" ]
632 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
633 const MASK: u8 = 15;
634 const OFFSET: u8 = 18;
635 self.register.bits &= !((MASK as u32) << OFFSET);
636 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
637 self.register
638 }
639 }
640 # [ doc = r" Proxy" ]
641 pub struct _McoW<'a> {
642 register: &'a mut W,
643 }
644 impl<'a> _McoW<'a> {
645 # [ doc = r" Writes raw `bits` to the field" ]
646 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
647 const MASK: u8 = 7;
648 const OFFSET: u8 = 24;
649 self.register.bits &= !((MASK as u32) << OFFSET);
650 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
651 self.register
652 }
653 }
654 # [ doc = r" Proxy" ]
655 pub struct _McopreW<'a> {
656 register: &'a mut W,
657 }
658 impl<'a> _McopreW<'a> {
659 # [ doc = r" Writes raw `bits` to the field" ]
660 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
661 const MASK: u8 = 7;
662 const OFFSET: u8 = 28;
663 self.register.bits &= !((MASK as u32) << OFFSET);
664 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
665 self.register
666 }
667 }
668 # [ doc = r" Proxy" ]
669 pub struct _PllnodivW<'a> {
670 register: &'a mut W,
671 }
672 impl<'a> _PllnodivW<'a> {
673 # [ doc = r" Writes raw `bits` to the field" ]
674 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
675 const MASK: u8 = 1;
676 const OFFSET: u8 = 31;
677 self.register.bits &= !((MASK as u32) << OFFSET);
678 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
679 self.register
680 }
681 }
682 impl R {
683 # [ doc = r" Value of the register as raw bits" ]
684 pub fn bits(&self) -> u32 {
685 self.bits
686 }
687 fn _sw(&self) -> u8 {
688 const MASK: u8 = 3;
689 const OFFSET: u8 = 0;
690 ((self.bits >> OFFSET) & MASK as u32) as u8
691 }
692 # [ doc = "Bits 0:1 - System clock Switch" ]
693 pub fn sw(&self) -> SwR {
694 SwR { bits: self._sw() }
695 }
696 fn _sws(&self) -> u8 {
697 const MASK: u8 = 3;
698 const OFFSET: u8 = 2;
699 ((self.bits >> OFFSET) & MASK as u32) as u8
700 }
701 # [ doc = "Bits 2:3 - System Clock Switch Status" ]
702 pub fn sws(&self) -> SwsR {
703 SwsR { bits: self._sws() }
704 }
705 fn _hpre(&self) -> u8 {
706 const MASK: u8 = 15;
707 const OFFSET: u8 = 4;
708 ((self.bits >> OFFSET) & MASK as u32) as u8
709 }
710 # [ doc = "Bits 4:7 - AHB prescaler" ]
711 pub fn hpre(&self) -> HpreR {
712 HpreR { bits: self._hpre() }
713 }
714 fn _ppre(&self) -> u8 {
715 const MASK: u8 = 7;
716 const OFFSET: u8 = 8;
717 ((self.bits >> OFFSET) & MASK as u32) as u8
718 }
719 # [ doc = "Bits 8:10 - APB Low speed prescaler (APB1)" ]
720 pub fn ppre(&self) -> PpreR {
721 PpreR { bits: self._ppre() }
722 }
723 fn _adcpre(&self) -> u8 {
724 const MASK: u8 = 1;
725 const OFFSET: u8 = 14;
726 ((self.bits >> OFFSET) & MASK as u32) as u8
727 }
728 # [ doc = "Bit 14 - ADC prescaler" ]
729 pub fn adcpre(&self) -> AdcpreR {
730 AdcpreR { bits: self._adcpre() }
731 }
732 fn _pllsrc(&self) -> u8 {
733 const MASK: u8 = 3;
734 const OFFSET: u8 = 15;
735 ((self.bits >> OFFSET) & MASK as u32) as u8
736 }
737 # [ doc = "Bits 15:16 - PLL input clock source" ]
738 pub fn pllsrc(&self) -> PllsrcR {
739 PllsrcR { bits: self._pllsrc() }
740 }
741 fn _pllxtpre(&self) -> u8 {
742 const MASK: u8 = 1;
743 const OFFSET: u8 = 17;
744 ((self.bits >> OFFSET) & MASK as u32) as u8
745 }
746 # [ doc = "Bit 17 - HSE divider for PLL entry" ]
747 pub fn pllxtpre(&self) -> PllxtpreR {
748 PllxtpreR { bits: self._pllxtpre() }
749 }
750 fn _pllmul(&self) -> u8 {
751 const MASK: u8 = 15;
752 const OFFSET: u8 = 18;
753 ((self.bits >> OFFSET) & MASK as u32) as u8
754 }
755 # [ doc = "Bits 18:21 - PLL Multiplication Factor" ]
756 pub fn pllmul(&self) -> PllmulR {
757 PllmulR { bits: self._pllmul() }
758 }
759 fn _mco(&self) -> u8 {
760 const MASK: u8 = 7;
761 const OFFSET: u8 = 24;
762 ((self.bits >> OFFSET) & MASK as u32) as u8
763 }
764 # [ doc = "Bits 24:26 - Microcontroller clock output" ]
765 pub fn mco(&self) -> McoR {
766 McoR { bits: self._mco() }
767 }
768 fn _mcopre(&self) -> u8 {
769 const MASK: u8 = 7;
770 const OFFSET: u8 = 28;
771 ((self.bits >> OFFSET) & MASK as u32) as u8
772 }
773 # [ doc = "Bits 28:30 - Microcontroller Clock Output Prescaler" ]
774 pub fn mcopre(&self) -> McopreR {
775 McopreR { bits: self._mcopre() }
776 }
777 fn _pllnodiv(&self) -> u8 {
778 const MASK: u8 = 1;
779 const OFFSET: u8 = 31;
780 ((self.bits >> OFFSET) & MASK as u32) as u8
781 }
782 # [ doc = "Bit 31 - PLL clock not divided for MCO" ]
783 pub fn pllnodiv(&self) -> PllnodivR {
784 PllnodivR { bits: self._pllnodiv() }
785 }
786 }
787 impl W {
788 # [ doc = r" Reset value of the register" ]
789 pub fn reset_value() -> W {
790 W { bits: 0 }
791 }
792 # [ doc = r" Writes raw `bits` to the register" ]
793 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
794 self.bits = bits;
795 self
796 }
797 # [ doc = "Bits 0:1 - System clock Switch" ]
798 pub fn sw(&mut self) -> _SwW {
799 _SwW { register: self }
800 }
801 # [ doc = "Bits 4:7 - AHB prescaler" ]
802 pub fn hpre(&mut self) -> _HpreW {
803 _HpreW { register: self }
804 }
805 # [ doc = "Bits 8:10 - APB Low speed prescaler (APB1)" ]
806 pub fn ppre(&mut self) -> _PpreW {
807 _PpreW { register: self }
808 }
809 # [ doc = "Bit 14 - ADC prescaler" ]
810 pub fn adcpre(&mut self) -> _AdcpreW {
811 _AdcpreW { register: self }
812 }
813 # [ doc = "Bits 15:16 - PLL input clock source" ]
814 pub fn pllsrc(&mut self) -> _PllsrcW {
815 _PllsrcW { register: self }
816 }
817 # [ doc = "Bit 17 - HSE divider for PLL entry" ]
818 pub fn pllxtpre(&mut self) -> _PllxtpreW {
819 _PllxtpreW { register: self }
820 }
821 # [ doc = "Bits 18:21 - PLL Multiplication Factor" ]
822 pub fn pllmul(&mut self) -> _PllmulW {
823 _PllmulW { register: self }
824 }
825 # [ doc = "Bits 24:26 - Microcontroller clock output" ]
826 pub fn mco(&mut self) -> _McoW {
827 _McoW { register: self }
828 }
829 # [ doc = "Bits 28:30 - Microcontroller Clock Output Prescaler" ]
830 pub fn mcopre(&mut self) -> _McopreW {
831 _McopreW { register: self }
832 }
833 # [ doc = "Bit 31 - PLL clock not divided for MCO" ]
834 pub fn pllnodiv(&mut self) -> _PllnodivW {
835 _PllnodivW { register: self }
836 }
837 }
838}
839
840# [ doc = "Clock interrupt register (RCC_CIR)" ]
841# [ repr ( C ) ]
842pub struct Cir {
843 register: ::volatile_register::RW<u32>,
844}
845
846# [ doc = "Clock interrupt register (RCC_CIR)" ]
847pub mod cir {
848 # [ doc = r" Value read from the register" ]
849 pub struct R {
850 bits: u32,
851 }
852 # [ doc = r" Value to write to the register" ]
853 pub struct W {
854 bits: u32,
855 }
856 impl super::Cir {
857 # [ doc = r" Modifies the contents of the register" ]
858 pub fn modify<F>(&mut self, f: F)
859 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
860 {
861 let bits = self.register.read();
862 let r = R { bits: bits };
863 let mut w = W { bits: bits };
864 f(&r, &mut w);
865 self.register.write(w.bits);
866 }
867 # [ doc = r" Reads the contents of the register" ]
868 pub fn read(&self) -> R {
869 R { bits: self.register.read() }
870 }
871 # [ doc = r" Writes to the register" ]
872 pub fn write<F>(&mut self, f: F)
873 where F: FnOnce(&mut W) -> &mut W
874 {
875 let mut w = W::reset_value();
876 f(&mut w);
877 self.register.write(w.bits);
878 }
879 }
880 # [ doc = "Value of the field LSIRDYF" ]
881 pub struct LsirdyfR {
882 bits: u8,
883 }
884 impl LsirdyfR {
885 # [ doc = r" Value of the field as raw bits" ]
886 pub fn bits(&self) -> u8 {
887 self.bits
888 }
889 }
890 # [ doc = "Value of the field LSERDYF" ]
891 pub struct LserdyfR {
892 bits: u8,
893 }
894 impl LserdyfR {
895 # [ doc = r" Value of the field as raw bits" ]
896 pub fn bits(&self) -> u8 {
897 self.bits
898 }
899 }
900 # [ doc = "Value of the field HSIRDYF" ]
901 pub struct HsirdyfR {
902 bits: u8,
903 }
904 impl HsirdyfR {
905 # [ doc = r" Value of the field as raw bits" ]
906 pub fn bits(&self) -> u8 {
907 self.bits
908 }
909 }
910 # [ doc = "Value of the field HSERDYF" ]
911 pub struct HserdyfR {
912 bits: u8,
913 }
914 impl HserdyfR {
915 # [ doc = r" Value of the field as raw bits" ]
916 pub fn bits(&self) -> u8 {
917 self.bits
918 }
919 }
920 # [ doc = "Value of the field PLLRDYF" ]
921 pub struct PllrdyfR {
922 bits: u8,
923 }
924 impl PllrdyfR {
925 # [ doc = r" Value of the field as raw bits" ]
926 pub fn bits(&self) -> u8 {
927 self.bits
928 }
929 }
930 # [ doc = "Value of the field HSI14RDYF" ]
931 pub struct Hsi14rdyfR {
932 bits: u8,
933 }
934 impl Hsi14rdyfR {
935 # [ doc = r" Value of the field as raw bits" ]
936 pub fn bits(&self) -> u8 {
937 self.bits
938 }
939 }
940 # [ doc = "Value of the field HSI48RDYF" ]
941 pub struct Hsi48rdyfR {
942 bits: u8,
943 }
944 impl Hsi48rdyfR {
945 # [ doc = r" Value of the field as raw bits" ]
946 pub fn bits(&self) -> u8 {
947 self.bits
948 }
949 }
950 # [ doc = "Value of the field CSSF" ]
951 pub struct CssfR {
952 bits: u8,
953 }
954 impl CssfR {
955 # [ doc = r" Value of the field as raw bits" ]
956 pub fn bits(&self) -> u8 {
957 self.bits
958 }
959 }
960 # [ doc = "Value of the field LSIRDYIE" ]
961 pub struct LsirdyieR {
962 bits: u8,
963 }
964 impl LsirdyieR {
965 # [ doc = r" Value of the field as raw bits" ]
966 pub fn bits(&self) -> u8 {
967 self.bits
968 }
969 }
970 # [ doc = "Value of the field LSERDYIE" ]
971 pub struct LserdyieR {
972 bits: u8,
973 }
974 impl LserdyieR {
975 # [ doc = r" Value of the field as raw bits" ]
976 pub fn bits(&self) -> u8 {
977 self.bits
978 }
979 }
980 # [ doc = "Value of the field HSIRDYIE" ]
981 pub struct HsirdyieR {
982 bits: u8,
983 }
984 impl HsirdyieR {
985 # [ doc = r" Value of the field as raw bits" ]
986 pub fn bits(&self) -> u8 {
987 self.bits
988 }
989 }
990 # [ doc = "Value of the field HSERDYIE" ]
991 pub struct HserdyieR {
992 bits: u8,
993 }
994 impl HserdyieR {
995 # [ doc = r" Value of the field as raw bits" ]
996 pub fn bits(&self) -> u8 {
997 self.bits
998 }
999 }
1000 # [ doc = "Value of the field PLLRDYIE" ]
1001 pub struct PllrdyieR {
1002 bits: u8,
1003 }
1004 impl PllrdyieR {
1005 # [ doc = r" Value of the field as raw bits" ]
1006 pub fn bits(&self) -> u8 {
1007 self.bits
1008 }
1009 }
1010 # [ doc = "Value of the field HSI14RDYE" ]
1011 pub struct Hsi14rdyeR {
1012 bits: u8,
1013 }
1014 impl Hsi14rdyeR {
1015 # [ doc = r" Value of the field as raw bits" ]
1016 pub fn bits(&self) -> u8 {
1017 self.bits
1018 }
1019 }
1020 # [ doc = "Value of the field HSI48RDYIE" ]
1021 pub struct Hsi48rdyieR {
1022 bits: u8,
1023 }
1024 impl Hsi48rdyieR {
1025 # [ doc = r" Value of the field as raw bits" ]
1026 pub fn bits(&self) -> u8 {
1027 self.bits
1028 }
1029 }
1030 # [ doc = r" Proxy" ]
1031 pub struct _LsirdyieW<'a> {
1032 register: &'a mut W,
1033 }
1034 impl<'a> _LsirdyieW<'a> {
1035 # [ doc = r" Writes raw `bits` to the field" ]
1036 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1037 const MASK: u8 = 1;
1038 const OFFSET: u8 = 8;
1039 self.register.bits &= !((MASK as u32) << OFFSET);
1040 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1041 self.register
1042 }
1043 }
1044 # [ doc = r" Proxy" ]
1045 pub struct _LserdyieW<'a> {
1046 register: &'a mut W,
1047 }
1048 impl<'a> _LserdyieW<'a> {
1049 # [ doc = r" Writes raw `bits` to the field" ]
1050 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1051 const MASK: u8 = 1;
1052 const OFFSET: u8 = 9;
1053 self.register.bits &= !((MASK as u32) << OFFSET);
1054 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1055 self.register
1056 }
1057 }
1058 # [ doc = r" Proxy" ]
1059 pub struct _HsirdyieW<'a> {
1060 register: &'a mut W,
1061 }
1062 impl<'a> _HsirdyieW<'a> {
1063 # [ doc = r" Writes raw `bits` to the field" ]
1064 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1065 const MASK: u8 = 1;
1066 const OFFSET: u8 = 10;
1067 self.register.bits &= !((MASK as u32) << OFFSET);
1068 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1069 self.register
1070 }
1071 }
1072 # [ doc = r" Proxy" ]
1073 pub struct _HserdyieW<'a> {
1074 register: &'a mut W,
1075 }
1076 impl<'a> _HserdyieW<'a> {
1077 # [ doc = r" Writes raw `bits` to the field" ]
1078 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1079 const MASK: u8 = 1;
1080 const OFFSET: u8 = 11;
1081 self.register.bits &= !((MASK as u32) << OFFSET);
1082 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1083 self.register
1084 }
1085 }
1086 # [ doc = r" Proxy" ]
1087 pub struct _PllrdyieW<'a> {
1088 register: &'a mut W,
1089 }
1090 impl<'a> _PllrdyieW<'a> {
1091 # [ doc = r" Writes raw `bits` to the field" ]
1092 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1093 const MASK: u8 = 1;
1094 const OFFSET: u8 = 12;
1095 self.register.bits &= !((MASK as u32) << OFFSET);
1096 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1097 self.register
1098 }
1099 }
1100 # [ doc = r" Proxy" ]
1101 pub struct _Hsi14rdyeW<'a> {
1102 register: &'a mut W,
1103 }
1104 impl<'a> _Hsi14rdyeW<'a> {
1105 # [ doc = r" Writes raw `bits` to the field" ]
1106 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1107 const MASK: u8 = 1;
1108 const OFFSET: u8 = 13;
1109 self.register.bits &= !((MASK as u32) << OFFSET);
1110 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1111 self.register
1112 }
1113 }
1114 # [ doc = r" Proxy" ]
1115 pub struct _Hsi48rdyieW<'a> {
1116 register: &'a mut W,
1117 }
1118 impl<'a> _Hsi48rdyieW<'a> {
1119 # [ doc = r" Writes raw `bits` to the field" ]
1120 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1121 const MASK: u8 = 1;
1122 const OFFSET: u8 = 14;
1123 self.register.bits &= !((MASK as u32) << OFFSET);
1124 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1125 self.register
1126 }
1127 }
1128 # [ doc = r" Proxy" ]
1129 pub struct _LsirdycW<'a> {
1130 register: &'a mut W,
1131 }
1132 impl<'a> _LsirdycW<'a> {
1133 # [ doc = r" Writes raw `bits` to the field" ]
1134 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1135 const MASK: u8 = 1;
1136 const OFFSET: u8 = 16;
1137 self.register.bits &= !((MASK as u32) << OFFSET);
1138 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1139 self.register
1140 }
1141 }
1142 # [ doc = r" Proxy" ]
1143 pub struct _LserdycW<'a> {
1144 register: &'a mut W,
1145 }
1146 impl<'a> _LserdycW<'a> {
1147 # [ doc = r" Writes raw `bits` to the field" ]
1148 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1149 const MASK: u8 = 1;
1150 const OFFSET: u8 = 17;
1151 self.register.bits &= !((MASK as u32) << OFFSET);
1152 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1153 self.register
1154 }
1155 }
1156 # [ doc = r" Proxy" ]
1157 pub struct _HsirdycW<'a> {
1158 register: &'a mut W,
1159 }
1160 impl<'a> _HsirdycW<'a> {
1161 # [ doc = r" Writes raw `bits` to the field" ]
1162 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1163 const MASK: u8 = 1;
1164 const OFFSET: u8 = 18;
1165 self.register.bits &= !((MASK as u32) << OFFSET);
1166 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1167 self.register
1168 }
1169 }
1170 # [ doc = r" Proxy" ]
1171 pub struct _HserdycW<'a> {
1172 register: &'a mut W,
1173 }
1174 impl<'a> _HserdycW<'a> {
1175 # [ doc = r" Writes raw `bits` to the field" ]
1176 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1177 const MASK: u8 = 1;
1178 const OFFSET: u8 = 19;
1179 self.register.bits &= !((MASK as u32) << OFFSET);
1180 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1181 self.register
1182 }
1183 }
1184 # [ doc = r" Proxy" ]
1185 pub struct _PllrdycW<'a> {
1186 register: &'a mut W,
1187 }
1188 impl<'a> _PllrdycW<'a> {
1189 # [ doc = r" Writes raw `bits` to the field" ]
1190 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1191 const MASK: u8 = 1;
1192 const OFFSET: u8 = 20;
1193 self.register.bits &= !((MASK as u32) << OFFSET);
1194 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1195 self.register
1196 }
1197 }
1198 # [ doc = r" Proxy" ]
1199 pub struct _Hsi14rdycW<'a> {
1200 register: &'a mut W,
1201 }
1202 impl<'a> _Hsi14rdycW<'a> {
1203 # [ doc = r" Writes raw `bits` to the field" ]
1204 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1205 const MASK: u8 = 1;
1206 const OFFSET: u8 = 21;
1207 self.register.bits &= !((MASK as u32) << OFFSET);
1208 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1209 self.register
1210 }
1211 }
1212 # [ doc = r" Proxy" ]
1213 pub struct _Hsi48rdycW<'a> {
1214 register: &'a mut W,
1215 }
1216 impl<'a> _Hsi48rdycW<'a> {
1217 # [ doc = r" Writes raw `bits` to the field" ]
1218 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1219 const MASK: u8 = 1;
1220 const OFFSET: u8 = 22;
1221 self.register.bits &= !((MASK as u32) << OFFSET);
1222 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1223 self.register
1224 }
1225 }
1226 # [ doc = r" Proxy" ]
1227 pub struct _CsscW<'a> {
1228 register: &'a mut W,
1229 }
1230 impl<'a> _CsscW<'a> {
1231 # [ doc = r" Writes raw `bits` to the field" ]
1232 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1233 const MASK: u8 = 1;
1234 const OFFSET: u8 = 23;
1235 self.register.bits &= !((MASK as u32) << OFFSET);
1236 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1237 self.register
1238 }
1239 }
1240 impl R {
1241 # [ doc = r" Value of the register as raw bits" ]
1242 pub fn bits(&self) -> u32 {
1243 self.bits
1244 }
1245 fn _lsirdyf(&self) -> u8 {
1246 const MASK: u8 = 1;
1247 const OFFSET: u8 = 0;
1248 ((self.bits >> OFFSET) & MASK as u32) as u8
1249 }
1250 # [ doc = "Bit 0 - LSI Ready Interrupt flag" ]
1251 pub fn lsirdyf(&self) -> LsirdyfR {
1252 LsirdyfR { bits: self._lsirdyf() }
1253 }
1254 fn _lserdyf(&self) -> u8 {
1255 const MASK: u8 = 1;
1256 const OFFSET: u8 = 1;
1257 ((self.bits >> OFFSET) & MASK as u32) as u8
1258 }
1259 # [ doc = "Bit 1 - LSE Ready Interrupt flag" ]
1260 pub fn lserdyf(&self) -> LserdyfR {
1261 LserdyfR { bits: self._lserdyf() }
1262 }
1263 fn _hsirdyf(&self) -> u8 {
1264 const MASK: u8 = 1;
1265 const OFFSET: u8 = 2;
1266 ((self.bits >> OFFSET) & MASK as u32) as u8
1267 }
1268 # [ doc = "Bit 2 - HSI Ready Interrupt flag" ]
1269 pub fn hsirdyf(&self) -> HsirdyfR {
1270 HsirdyfR { bits: self._hsirdyf() }
1271 }
1272 fn _hserdyf(&self) -> u8 {
1273 const MASK: u8 = 1;
1274 const OFFSET: u8 = 3;
1275 ((self.bits >> OFFSET) & MASK as u32) as u8
1276 }
1277 # [ doc = "Bit 3 - HSE Ready Interrupt flag" ]
1278 pub fn hserdyf(&self) -> HserdyfR {
1279 HserdyfR { bits: self._hserdyf() }
1280 }
1281 fn _pllrdyf(&self) -> u8 {
1282 const MASK: u8 = 1;
1283 const OFFSET: u8 = 4;
1284 ((self.bits >> OFFSET) & MASK as u32) as u8
1285 }
1286 # [ doc = "Bit 4 - PLL Ready Interrupt flag" ]
1287 pub fn pllrdyf(&self) -> PllrdyfR {
1288 PllrdyfR { bits: self._pllrdyf() }
1289 }
1290 fn _hsi14rdyf(&self) -> u8 {
1291 const MASK: u8 = 1;
1292 const OFFSET: u8 = 5;
1293 ((self.bits >> OFFSET) & MASK as u32) as u8
1294 }
1295 # [ doc = "Bit 5 - HSI14 ready interrupt flag" ]
1296 pub fn hsi14rdyf(&self) -> Hsi14rdyfR {
1297 Hsi14rdyfR { bits: self._hsi14rdyf() }
1298 }
1299 fn _hsi48rdyf(&self) -> u8 {
1300 const MASK: u8 = 1;
1301 const OFFSET: u8 = 6;
1302 ((self.bits >> OFFSET) & MASK as u32) as u8
1303 }
1304 # [ doc = "Bit 6 - HSI48 ready interrupt flag" ]
1305 pub fn hsi48rdyf(&self) -> Hsi48rdyfR {
1306 Hsi48rdyfR { bits: self._hsi48rdyf() }
1307 }
1308 fn _cssf(&self) -> u8 {
1309 const MASK: u8 = 1;
1310 const OFFSET: u8 = 7;
1311 ((self.bits >> OFFSET) & MASK as u32) as u8
1312 }
1313 # [ doc = "Bit 7 - Clock Security System Interrupt flag" ]
1314 pub fn cssf(&self) -> CssfR {
1315 CssfR { bits: self._cssf() }
1316 }
1317 fn _lsirdyie(&self) -> u8 {
1318 const MASK: u8 = 1;
1319 const OFFSET: u8 = 8;
1320 ((self.bits >> OFFSET) & MASK as u32) as u8
1321 }
1322 # [ doc = "Bit 8 - LSI Ready Interrupt Enable" ]
1323 pub fn lsirdyie(&self) -> LsirdyieR {
1324 LsirdyieR { bits: self._lsirdyie() }
1325 }
1326 fn _lserdyie(&self) -> u8 {
1327 const MASK: u8 = 1;
1328 const OFFSET: u8 = 9;
1329 ((self.bits >> OFFSET) & MASK as u32) as u8
1330 }
1331 # [ doc = "Bit 9 - LSE Ready Interrupt Enable" ]
1332 pub fn lserdyie(&self) -> LserdyieR {
1333 LserdyieR { bits: self._lserdyie() }
1334 }
1335 fn _hsirdyie(&self) -> u8 {
1336 const MASK: u8 = 1;
1337 const OFFSET: u8 = 10;
1338 ((self.bits >> OFFSET) & MASK as u32) as u8
1339 }
1340 # [ doc = "Bit 10 - HSI Ready Interrupt Enable" ]
1341 pub fn hsirdyie(&self) -> HsirdyieR {
1342 HsirdyieR { bits: self._hsirdyie() }
1343 }
1344 fn _hserdyie(&self) -> u8 {
1345 const MASK: u8 = 1;
1346 const OFFSET: u8 = 11;
1347 ((self.bits >> OFFSET) & MASK as u32) as u8
1348 }
1349 # [ doc = "Bit 11 - HSE Ready Interrupt Enable" ]
1350 pub fn hserdyie(&self) -> HserdyieR {
1351 HserdyieR { bits: self._hserdyie() }
1352 }
1353 fn _pllrdyie(&self) -> u8 {
1354 const MASK: u8 = 1;
1355 const OFFSET: u8 = 12;
1356 ((self.bits >> OFFSET) & MASK as u32) as u8
1357 }
1358 # [ doc = "Bit 12 - PLL Ready Interrupt Enable" ]
1359 pub fn pllrdyie(&self) -> PllrdyieR {
1360 PllrdyieR { bits: self._pllrdyie() }
1361 }
1362 fn _hsi14rdye(&self) -> u8 {
1363 const MASK: u8 = 1;
1364 const OFFSET: u8 = 13;
1365 ((self.bits >> OFFSET) & MASK as u32) as u8
1366 }
1367 # [ doc = "Bit 13 - HSI14 ready interrupt enable" ]
1368 pub fn hsi14rdye(&self) -> Hsi14rdyeR {
1369 Hsi14rdyeR { bits: self._hsi14rdye() }
1370 }
1371 fn _hsi48rdyie(&self) -> u8 {
1372 const MASK: u8 = 1;
1373 const OFFSET: u8 = 14;
1374 ((self.bits >> OFFSET) & MASK as u32) as u8
1375 }
1376 # [ doc = "Bit 14 - HSI48 ready interrupt enable" ]
1377 pub fn hsi48rdyie(&self) -> Hsi48rdyieR {
1378 Hsi48rdyieR { bits: self._hsi48rdyie() }
1379 }
1380 }
1381 impl W {
1382 # [ doc = r" Reset value of the register" ]
1383 pub fn reset_value() -> W {
1384 W { bits: 0 }
1385 }
1386 # [ doc = r" Writes raw `bits` to the register" ]
1387 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1388 self.bits = bits;
1389 self
1390 }
1391 # [ doc = "Bit 8 - LSI Ready Interrupt Enable" ]
1392 pub fn lsirdyie(&mut self) -> _LsirdyieW {
1393 _LsirdyieW { register: self }
1394 }
1395 # [ doc = "Bit 9 - LSE Ready Interrupt Enable" ]
1396 pub fn lserdyie(&mut self) -> _LserdyieW {
1397 _LserdyieW { register: self }
1398 }
1399 # [ doc = "Bit 10 - HSI Ready Interrupt Enable" ]
1400 pub fn hsirdyie(&mut self) -> _HsirdyieW {
1401 _HsirdyieW { register: self }
1402 }
1403 # [ doc = "Bit 11 - HSE Ready Interrupt Enable" ]
1404 pub fn hserdyie(&mut self) -> _HserdyieW {
1405 _HserdyieW { register: self }
1406 }
1407 # [ doc = "Bit 12 - PLL Ready Interrupt Enable" ]
1408 pub fn pllrdyie(&mut self) -> _PllrdyieW {
1409 _PllrdyieW { register: self }
1410 }
1411 # [ doc = "Bit 13 - HSI14 ready interrupt enable" ]
1412 pub fn hsi14rdye(&mut self) -> _Hsi14rdyeW {
1413 _Hsi14rdyeW { register: self }
1414 }
1415 # [ doc = "Bit 14 - HSI48 ready interrupt enable" ]
1416 pub fn hsi48rdyie(&mut self) -> _Hsi48rdyieW {
1417 _Hsi48rdyieW { register: self }
1418 }
1419 # [ doc = "Bit 16 - LSI Ready Interrupt Clear" ]
1420 pub fn lsirdyc(&mut self) -> _LsirdycW {
1421 _LsirdycW { register: self }
1422 }
1423 # [ doc = "Bit 17 - LSE Ready Interrupt Clear" ]
1424 pub fn lserdyc(&mut self) -> _LserdycW {
1425 _LserdycW { register: self }
1426 }
1427 # [ doc = "Bit 18 - HSI Ready Interrupt Clear" ]
1428 pub fn hsirdyc(&mut self) -> _HsirdycW {
1429 _HsirdycW { register: self }
1430 }
1431 # [ doc = "Bit 19 - HSE Ready Interrupt Clear" ]
1432 pub fn hserdyc(&mut self) -> _HserdycW {
1433 _HserdycW { register: self }
1434 }
1435 # [ doc = "Bit 20 - PLL Ready Interrupt Clear" ]
1436 pub fn pllrdyc(&mut self) -> _PllrdycW {
1437 _PllrdycW { register: self }
1438 }
1439 # [ doc = "Bit 21 - HSI 14 MHz Ready Interrupt Clear" ]
1440 pub fn hsi14rdyc(&mut self) -> _Hsi14rdycW {
1441 _Hsi14rdycW { register: self }
1442 }
1443 # [ doc = "Bit 22 - HSI48 Ready Interrupt Clear" ]
1444 pub fn hsi48rdyc(&mut self) -> _Hsi48rdycW {
1445 _Hsi48rdycW { register: self }
1446 }
1447 # [ doc = "Bit 23 - Clock security system interrupt clear" ]
1448 pub fn cssc(&mut self) -> _CsscW {
1449 _CsscW { register: self }
1450 }
1451 }
1452}
1453
1454# [ doc = "APB2 peripheral reset register (RCC_APB2RSTR)" ]
1455# [ repr ( C ) ]
1456pub struct Apb2rstr {
1457 register: ::volatile_register::RW<u32>,
1458}
1459
1460# [ doc = "APB2 peripheral reset register (RCC_APB2RSTR)" ]
1461pub mod apb2rstr {
1462 # [ doc = r" Value read from the register" ]
1463 pub struct R {
1464 bits: u32,
1465 }
1466 # [ doc = r" Value to write to the register" ]
1467 pub struct W {
1468 bits: u32,
1469 }
1470 impl super::Apb2rstr {
1471 # [ doc = r" Modifies the contents of the register" ]
1472 pub fn modify<F>(&mut self, f: F)
1473 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
1474 {
1475 let bits = self.register.read();
1476 let r = R { bits: bits };
1477 let mut w = W { bits: bits };
1478 f(&r, &mut w);
1479 self.register.write(w.bits);
1480 }
1481 # [ doc = r" Reads the contents of the register" ]
1482 pub fn read(&self) -> R {
1483 R { bits: self.register.read() }
1484 }
1485 # [ doc = r" Writes to the register" ]
1486 pub fn write<F>(&mut self, f: F)
1487 where F: FnOnce(&mut W) -> &mut W
1488 {
1489 let mut w = W::reset_value();
1490 f(&mut w);
1491 self.register.write(w.bits);
1492 }
1493 }
1494 # [ doc = "Value of the field SYSCFGRST" ]
1495 pub struct SyscfgrstR {
1496 bits: u8,
1497 }
1498 impl SyscfgrstR {
1499 # [ doc = r" Value of the field as raw bits" ]
1500 pub fn bits(&self) -> u8 {
1501 self.bits
1502 }
1503 }
1504 # [ doc = "Value of the field ADCRST" ]
1505 pub struct AdcrstR {
1506 bits: u8,
1507 }
1508 impl AdcrstR {
1509 # [ doc = r" Value of the field as raw bits" ]
1510 pub fn bits(&self) -> u8 {
1511 self.bits
1512 }
1513 }
1514 # [ doc = "Value of the field TIM1RST" ]
1515 pub struct Tim1rstR {
1516 bits: u8,
1517 }
1518 impl Tim1rstR {
1519 # [ doc = r" Value of the field as raw bits" ]
1520 pub fn bits(&self) -> u8 {
1521 self.bits
1522 }
1523 }
1524 # [ doc = "Value of the field SPI1RST" ]
1525 pub struct Spi1rstR {
1526 bits: u8,
1527 }
1528 impl Spi1rstR {
1529 # [ doc = r" Value of the field as raw bits" ]
1530 pub fn bits(&self) -> u8 {
1531 self.bits
1532 }
1533 }
1534 # [ doc = "Value of the field USART1RST" ]
1535 pub struct Usart1rstR {
1536 bits: u8,
1537 }
1538 impl Usart1rstR {
1539 # [ doc = r" Value of the field as raw bits" ]
1540 pub fn bits(&self) -> u8 {
1541 self.bits
1542 }
1543 }
1544 # [ doc = "Value of the field TIM15RST" ]
1545 pub struct Tim15rstR {
1546 bits: u8,
1547 }
1548 impl Tim15rstR {
1549 # [ doc = r" Value of the field as raw bits" ]
1550 pub fn bits(&self) -> u8 {
1551 self.bits
1552 }
1553 }
1554 # [ doc = "Value of the field TIM16RST" ]
1555 pub struct Tim16rstR {
1556 bits: u8,
1557 }
1558 impl Tim16rstR {
1559 # [ doc = r" Value of the field as raw bits" ]
1560 pub fn bits(&self) -> u8 {
1561 self.bits
1562 }
1563 }
1564 # [ doc = "Value of the field TIM17RST" ]
1565 pub struct Tim17rstR {
1566 bits: u8,
1567 }
1568 impl Tim17rstR {
1569 # [ doc = r" Value of the field as raw bits" ]
1570 pub fn bits(&self) -> u8 {
1571 self.bits
1572 }
1573 }
1574 # [ doc = "Value of the field DBGMCURST" ]
1575 pub struct DbgmcurstR {
1576 bits: u8,
1577 }
1578 impl DbgmcurstR {
1579 # [ doc = r" Value of the field as raw bits" ]
1580 pub fn bits(&self) -> u8 {
1581 self.bits
1582 }
1583 }
1584 # [ doc = r" Proxy" ]
1585 pub struct _SyscfgrstW<'a> {
1586 register: &'a mut W,
1587 }
1588 impl<'a> _SyscfgrstW<'a> {
1589 # [ doc = r" Writes raw `bits` to the field" ]
1590 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1591 const MASK: u8 = 1;
1592 const OFFSET: u8 = 0;
1593 self.register.bits &= !((MASK as u32) << OFFSET);
1594 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1595 self.register
1596 }
1597 }
1598 # [ doc = r" Proxy" ]
1599 pub struct _AdcrstW<'a> {
1600 register: &'a mut W,
1601 }
1602 impl<'a> _AdcrstW<'a> {
1603 # [ doc = r" Writes raw `bits` to the field" ]
1604 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1605 const MASK: u8 = 1;
1606 const OFFSET: u8 = 9;
1607 self.register.bits &= !((MASK as u32) << OFFSET);
1608 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1609 self.register
1610 }
1611 }
1612 # [ doc = r" Proxy" ]
1613 pub struct _Tim1rstW<'a> {
1614 register: &'a mut W,
1615 }
1616 impl<'a> _Tim1rstW<'a> {
1617 # [ doc = r" Writes raw `bits` to the field" ]
1618 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1619 const MASK: u8 = 1;
1620 const OFFSET: u8 = 11;
1621 self.register.bits &= !((MASK as u32) << OFFSET);
1622 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1623 self.register
1624 }
1625 }
1626 # [ doc = r" Proxy" ]
1627 pub struct _Spi1rstW<'a> {
1628 register: &'a mut W,
1629 }
1630 impl<'a> _Spi1rstW<'a> {
1631 # [ doc = r" Writes raw `bits` to the field" ]
1632 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1633 const MASK: u8 = 1;
1634 const OFFSET: u8 = 12;
1635 self.register.bits &= !((MASK as u32) << OFFSET);
1636 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1637 self.register
1638 }
1639 }
1640 # [ doc = r" Proxy" ]
1641 pub struct _Usart1rstW<'a> {
1642 register: &'a mut W,
1643 }
1644 impl<'a> _Usart1rstW<'a> {
1645 # [ doc = r" Writes raw `bits` to the field" ]
1646 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1647 const MASK: u8 = 1;
1648 const OFFSET: u8 = 14;
1649 self.register.bits &= !((MASK as u32) << OFFSET);
1650 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1651 self.register
1652 }
1653 }
1654 # [ doc = r" Proxy" ]
1655 pub struct _Tim15rstW<'a> {
1656 register: &'a mut W,
1657 }
1658 impl<'a> _Tim15rstW<'a> {
1659 # [ doc = r" Writes raw `bits` to the field" ]
1660 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1661 const MASK: u8 = 1;
1662 const OFFSET: u8 = 16;
1663 self.register.bits &= !((MASK as u32) << OFFSET);
1664 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1665 self.register
1666 }
1667 }
1668 # [ doc = r" Proxy" ]
1669 pub struct _Tim16rstW<'a> {
1670 register: &'a mut W,
1671 }
1672 impl<'a> _Tim16rstW<'a> {
1673 # [ doc = r" Writes raw `bits` to the field" ]
1674 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1675 const MASK: u8 = 1;
1676 const OFFSET: u8 = 17;
1677 self.register.bits &= !((MASK as u32) << OFFSET);
1678 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1679 self.register
1680 }
1681 }
1682 # [ doc = r" Proxy" ]
1683 pub struct _Tim17rstW<'a> {
1684 register: &'a mut W,
1685 }
1686 impl<'a> _Tim17rstW<'a> {
1687 # [ doc = r" Writes raw `bits` to the field" ]
1688 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1689 const MASK: u8 = 1;
1690 const OFFSET: u8 = 18;
1691 self.register.bits &= !((MASK as u32) << OFFSET);
1692 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1693 self.register
1694 }
1695 }
1696 # [ doc = r" Proxy" ]
1697 pub struct _DbgmcurstW<'a> {
1698 register: &'a mut W,
1699 }
1700 impl<'a> _DbgmcurstW<'a> {
1701 # [ doc = r" Writes raw `bits` to the field" ]
1702 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1703 const MASK: u8 = 1;
1704 const OFFSET: u8 = 22;
1705 self.register.bits &= !((MASK as u32) << OFFSET);
1706 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1707 self.register
1708 }
1709 }
1710 impl R {
1711 # [ doc = r" Value of the register as raw bits" ]
1712 pub fn bits(&self) -> u32 {
1713 self.bits
1714 }
1715 fn _syscfgrst(&self) -> u8 {
1716 const MASK: u8 = 1;
1717 const OFFSET: u8 = 0;
1718 ((self.bits >> OFFSET) & MASK as u32) as u8
1719 }
1720 # [ doc = "Bit 0 - SYSCFG and COMP reset" ]
1721 pub fn syscfgrst(&self) -> SyscfgrstR {
1722 SyscfgrstR { bits: self._syscfgrst() }
1723 }
1724 fn _adcrst(&self) -> u8 {
1725 const MASK: u8 = 1;
1726 const OFFSET: u8 = 9;
1727 ((self.bits >> OFFSET) & MASK as u32) as u8
1728 }
1729 # [ doc = "Bit 9 - ADC interface reset" ]
1730 pub fn adcrst(&self) -> AdcrstR {
1731 AdcrstR { bits: self._adcrst() }
1732 }
1733 fn _tim1rst(&self) -> u8 {
1734 const MASK: u8 = 1;
1735 const OFFSET: u8 = 11;
1736 ((self.bits >> OFFSET) & MASK as u32) as u8
1737 }
1738 # [ doc = "Bit 11 - TIM1 timer reset" ]
1739 pub fn tim1rst(&self) -> Tim1rstR {
1740 Tim1rstR { bits: self._tim1rst() }
1741 }
1742 fn _spi1rst(&self) -> u8 {
1743 const MASK: u8 = 1;
1744 const OFFSET: u8 = 12;
1745 ((self.bits >> OFFSET) & MASK as u32) as u8
1746 }
1747 # [ doc = "Bit 12 - SPI 1 reset" ]
1748 pub fn spi1rst(&self) -> Spi1rstR {
1749 Spi1rstR { bits: self._spi1rst() }
1750 }
1751 fn _usart1rst(&self) -> u8 {
1752 const MASK: u8 = 1;
1753 const OFFSET: u8 = 14;
1754 ((self.bits >> OFFSET) & MASK as u32) as u8
1755 }
1756 # [ doc = "Bit 14 - USART1 reset" ]
1757 pub fn usart1rst(&self) -> Usart1rstR {
1758 Usart1rstR { bits: self._usart1rst() }
1759 }
1760 fn _tim15rst(&self) -> u8 {
1761 const MASK: u8 = 1;
1762 const OFFSET: u8 = 16;
1763 ((self.bits >> OFFSET) & MASK as u32) as u8
1764 }
1765 # [ doc = "Bit 16 - TIM15 timer reset" ]
1766 pub fn tim15rst(&self) -> Tim15rstR {
1767 Tim15rstR { bits: self._tim15rst() }
1768 }
1769 fn _tim16rst(&self) -> u8 {
1770 const MASK: u8 = 1;
1771 const OFFSET: u8 = 17;
1772 ((self.bits >> OFFSET) & MASK as u32) as u8
1773 }
1774 # [ doc = "Bit 17 - TIM16 timer reset" ]
1775 pub fn tim16rst(&self) -> Tim16rstR {
1776 Tim16rstR { bits: self._tim16rst() }
1777 }
1778 fn _tim17rst(&self) -> u8 {
1779 const MASK: u8 = 1;
1780 const OFFSET: u8 = 18;
1781 ((self.bits >> OFFSET) & MASK as u32) as u8
1782 }
1783 # [ doc = "Bit 18 - TIM17 timer reset" ]
1784 pub fn tim17rst(&self) -> Tim17rstR {
1785 Tim17rstR { bits: self._tim17rst() }
1786 }
1787 fn _dbgmcurst(&self) -> u8 {
1788 const MASK: u8 = 1;
1789 const OFFSET: u8 = 22;
1790 ((self.bits >> OFFSET) & MASK as u32) as u8
1791 }
1792 # [ doc = "Bit 22 - Debug MCU reset" ]
1793 pub fn dbgmcurst(&self) -> DbgmcurstR {
1794 DbgmcurstR { bits: self._dbgmcurst() }
1795 }
1796 }
1797 impl W {
1798 # [ doc = r" Reset value of the register" ]
1799 pub fn reset_value() -> W {
1800 W { bits: 0 }
1801 }
1802 # [ doc = r" Writes raw `bits` to the register" ]
1803 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1804 self.bits = bits;
1805 self
1806 }
1807 # [ doc = "Bit 0 - SYSCFG and COMP reset" ]
1808 pub fn syscfgrst(&mut self) -> _SyscfgrstW {
1809 _SyscfgrstW { register: self }
1810 }
1811 # [ doc = "Bit 9 - ADC interface reset" ]
1812 pub fn adcrst(&mut self) -> _AdcrstW {
1813 _AdcrstW { register: self }
1814 }
1815 # [ doc = "Bit 11 - TIM1 timer reset" ]
1816 pub fn tim1rst(&mut self) -> _Tim1rstW {
1817 _Tim1rstW { register: self }
1818 }
1819 # [ doc = "Bit 12 - SPI 1 reset" ]
1820 pub fn spi1rst(&mut self) -> _Spi1rstW {
1821 _Spi1rstW { register: self }
1822 }
1823 # [ doc = "Bit 14 - USART1 reset" ]
1824 pub fn usart1rst(&mut self) -> _Usart1rstW {
1825 _Usart1rstW { register: self }
1826 }
1827 # [ doc = "Bit 16 - TIM15 timer reset" ]
1828 pub fn tim15rst(&mut self) -> _Tim15rstW {
1829 _Tim15rstW { register: self }
1830 }
1831 # [ doc = "Bit 17 - TIM16 timer reset" ]
1832 pub fn tim16rst(&mut self) -> _Tim16rstW {
1833 _Tim16rstW { register: self }
1834 }
1835 # [ doc = "Bit 18 - TIM17 timer reset" ]
1836 pub fn tim17rst(&mut self) -> _Tim17rstW {
1837 _Tim17rstW { register: self }
1838 }
1839 # [ doc = "Bit 22 - Debug MCU reset" ]
1840 pub fn dbgmcurst(&mut self) -> _DbgmcurstW {
1841 _DbgmcurstW { register: self }
1842 }
1843 }
1844}
1845
1846# [ doc = "APB1 peripheral reset register (RCC_APB1RSTR)" ]
1847# [ repr ( C ) ]
1848pub struct Apb1rstr {
1849 register: ::volatile_register::RW<u32>,
1850}
1851
1852# [ doc = "APB1 peripheral reset register (RCC_APB1RSTR)" ]
1853pub mod apb1rstr {
1854 # [ doc = r" Value read from the register" ]
1855 pub struct R {
1856 bits: u32,
1857 }
1858 # [ doc = r" Value to write to the register" ]
1859 pub struct W {
1860 bits: u32,
1861 }
1862 impl super::Apb1rstr {
1863 # [ doc = r" Modifies the contents of the register" ]
1864 pub fn modify<F>(&mut self, f: F)
1865 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
1866 {
1867 let bits = self.register.read();
1868 let r = R { bits: bits };
1869 let mut w = W { bits: bits };
1870 f(&r, &mut w);
1871 self.register.write(w.bits);
1872 }
1873 # [ doc = r" Reads the contents of the register" ]
1874 pub fn read(&self) -> R {
1875 R { bits: self.register.read() }
1876 }
1877 # [ doc = r" Writes to the register" ]
1878 pub fn write<F>(&mut self, f: F)
1879 where F: FnOnce(&mut W) -> &mut W
1880 {
1881 let mut w = W::reset_value();
1882 f(&mut w);
1883 self.register.write(w.bits);
1884 }
1885 }
1886 # [ doc = "Value of the field TIM2RST" ]
1887 pub struct Tim2rstR {
1888 bits: u8,
1889 }
1890 impl Tim2rstR {
1891 # [ doc = r" Value of the field as raw bits" ]
1892 pub fn bits(&self) -> u8 {
1893 self.bits
1894 }
1895 }
1896 # [ doc = "Value of the field TIM3RST" ]
1897 pub struct Tim3rstR {
1898 bits: u8,
1899 }
1900 impl Tim3rstR {
1901 # [ doc = r" Value of the field as raw bits" ]
1902 pub fn bits(&self) -> u8 {
1903 self.bits
1904 }
1905 }
1906 # [ doc = "Value of the field TIM6RST" ]
1907 pub struct Tim6rstR {
1908 bits: u8,
1909 }
1910 impl Tim6rstR {
1911 # [ doc = r" Value of the field as raw bits" ]
1912 pub fn bits(&self) -> u8 {
1913 self.bits
1914 }
1915 }
1916 # [ doc = "Value of the field TIM7RST" ]
1917 pub struct Tim7rstR {
1918 bits: u8,
1919 }
1920 impl Tim7rstR {
1921 # [ doc = r" Value of the field as raw bits" ]
1922 pub fn bits(&self) -> u8 {
1923 self.bits
1924 }
1925 }
1926 # [ doc = "Value of the field TIM14RST" ]
1927 pub struct Tim14rstR {
1928 bits: u8,
1929 }
1930 impl Tim14rstR {
1931 # [ doc = r" Value of the field as raw bits" ]
1932 pub fn bits(&self) -> u8 {
1933 self.bits
1934 }
1935 }
1936 # [ doc = "Value of the field WWDGRST" ]
1937 pub struct WwdgrstR {
1938 bits: u8,
1939 }
1940 impl WwdgrstR {
1941 # [ doc = r" Value of the field as raw bits" ]
1942 pub fn bits(&self) -> u8 {
1943 self.bits
1944 }
1945 }
1946 # [ doc = "Value of the field SPI2RST" ]
1947 pub struct Spi2rstR {
1948 bits: u8,
1949 }
1950 impl Spi2rstR {
1951 # [ doc = r" Value of the field as raw bits" ]
1952 pub fn bits(&self) -> u8 {
1953 self.bits
1954 }
1955 }
1956 # [ doc = "Value of the field USART2RST" ]
1957 pub struct Usart2rstR {
1958 bits: u8,
1959 }
1960 impl Usart2rstR {
1961 # [ doc = r" Value of the field as raw bits" ]
1962 pub fn bits(&self) -> u8 {
1963 self.bits
1964 }
1965 }
1966 # [ doc = "Value of the field USART3RST" ]
1967 pub struct Usart3rstR {
1968 bits: u8,
1969 }
1970 impl Usart3rstR {
1971 # [ doc = r" Value of the field as raw bits" ]
1972 pub fn bits(&self) -> u8 {
1973 self.bits
1974 }
1975 }
1976 # [ doc = "Value of the field USART4RST" ]
1977 pub struct Usart4rstR {
1978 bits: u8,
1979 }
1980 impl Usart4rstR {
1981 # [ doc = r" Value of the field as raw bits" ]
1982 pub fn bits(&self) -> u8 {
1983 self.bits
1984 }
1985 }
1986 # [ doc = "Value of the field I2C1RST" ]
1987 pub struct I2c1rstR {
1988 bits: u8,
1989 }
1990 impl I2c1rstR {
1991 # [ doc = r" Value of the field as raw bits" ]
1992 pub fn bits(&self) -> u8 {
1993 self.bits
1994 }
1995 }
1996 # [ doc = "Value of the field I2C2RST" ]
1997 pub struct I2c2rstR {
1998 bits: u8,
1999 }
2000 impl I2c2rstR {
2001 # [ doc = r" Value of the field as raw bits" ]
2002 pub fn bits(&self) -> u8 {
2003 self.bits
2004 }
2005 }
2006 # [ doc = "Value of the field USBRST" ]
2007 pub struct UsbrstR {
2008 bits: u8,
2009 }
2010 impl UsbrstR {
2011 # [ doc = r" Value of the field as raw bits" ]
2012 pub fn bits(&self) -> u8 {
2013 self.bits
2014 }
2015 }
2016 # [ doc = "Value of the field CANRST" ]
2017 pub struct CanrstR {
2018 bits: u8,
2019 }
2020 impl CanrstR {
2021 # [ doc = r" Value of the field as raw bits" ]
2022 pub fn bits(&self) -> u8 {
2023 self.bits
2024 }
2025 }
2026 # [ doc = "Value of the field CRSRST" ]
2027 pub struct CrsrstR {
2028 bits: u8,
2029 }
2030 impl CrsrstR {
2031 # [ doc = r" Value of the field as raw bits" ]
2032 pub fn bits(&self) -> u8 {
2033 self.bits
2034 }
2035 }
2036 # [ doc = "Value of the field PWRRST" ]
2037 pub struct PwrrstR {
2038 bits: u8,
2039 }
2040 impl PwrrstR {
2041 # [ doc = r" Value of the field as raw bits" ]
2042 pub fn bits(&self) -> u8 {
2043 self.bits
2044 }
2045 }
2046 # [ doc = "Value of the field DACRST" ]
2047 pub struct DacrstR {
2048 bits: u8,
2049 }
2050 impl DacrstR {
2051 # [ doc = r" Value of the field as raw bits" ]
2052 pub fn bits(&self) -> u8 {
2053 self.bits
2054 }
2055 }
2056 # [ doc = "Value of the field CECRST" ]
2057 pub struct CecrstR {
2058 bits: u8,
2059 }
2060 impl CecrstR {
2061 # [ doc = r" Value of the field as raw bits" ]
2062 pub fn bits(&self) -> u8 {
2063 self.bits
2064 }
2065 }
2066 # [ doc = r" Proxy" ]
2067 pub struct _Tim2rstW<'a> {
2068 register: &'a mut W,
2069 }
2070 impl<'a> _Tim2rstW<'a> {
2071 # [ doc = r" Writes raw `bits` to the field" ]
2072 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2073 const MASK: u8 = 1;
2074 const OFFSET: u8 = 0;
2075 self.register.bits &= !((MASK as u32) << OFFSET);
2076 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2077 self.register
2078 }
2079 }
2080 # [ doc = r" Proxy" ]
2081 pub struct _Tim3rstW<'a> {
2082 register: &'a mut W,
2083 }
2084 impl<'a> _Tim3rstW<'a> {
2085 # [ doc = r" Writes raw `bits` to the field" ]
2086 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2087 const MASK: u8 = 1;
2088 const OFFSET: u8 = 1;
2089 self.register.bits &= !((MASK as u32) << OFFSET);
2090 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2091 self.register
2092 }
2093 }
2094 # [ doc = r" Proxy" ]
2095 pub struct _Tim6rstW<'a> {
2096 register: &'a mut W,
2097 }
2098 impl<'a> _Tim6rstW<'a> {
2099 # [ doc = r" Writes raw `bits` to the field" ]
2100 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2101 const MASK: u8 = 1;
2102 const OFFSET: u8 = 4;
2103 self.register.bits &= !((MASK as u32) << OFFSET);
2104 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2105 self.register
2106 }
2107 }
2108 # [ doc = r" Proxy" ]
2109 pub struct _Tim7rstW<'a> {
2110 register: &'a mut W,
2111 }
2112 impl<'a> _Tim7rstW<'a> {
2113 # [ doc = r" Writes raw `bits` to the field" ]
2114 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2115 const MASK: u8 = 1;
2116 const OFFSET: u8 = 5;
2117 self.register.bits &= !((MASK as u32) << OFFSET);
2118 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2119 self.register
2120 }
2121 }
2122 # [ doc = r" Proxy" ]
2123 pub struct _Tim14rstW<'a> {
2124 register: &'a mut W,
2125 }
2126 impl<'a> _Tim14rstW<'a> {
2127 # [ doc = r" Writes raw `bits` to the field" ]
2128 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2129 const MASK: u8 = 1;
2130 const OFFSET: u8 = 8;
2131 self.register.bits &= !((MASK as u32) << OFFSET);
2132 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2133 self.register
2134 }
2135 }
2136 # [ doc = r" Proxy" ]
2137 pub struct _WwdgrstW<'a> {
2138 register: &'a mut W,
2139 }
2140 impl<'a> _WwdgrstW<'a> {
2141 # [ doc = r" Writes raw `bits` to the field" ]
2142 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2143 const MASK: u8 = 1;
2144 const OFFSET: u8 = 11;
2145 self.register.bits &= !((MASK as u32) << OFFSET);
2146 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2147 self.register
2148 }
2149 }
2150 # [ doc = r" Proxy" ]
2151 pub struct _Spi2rstW<'a> {
2152 register: &'a mut W,
2153 }
2154 impl<'a> _Spi2rstW<'a> {
2155 # [ doc = r" Writes raw `bits` to the field" ]
2156 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2157 const MASK: u8 = 1;
2158 const OFFSET: u8 = 14;
2159 self.register.bits &= !((MASK as u32) << OFFSET);
2160 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2161 self.register
2162 }
2163 }
2164 # [ doc = r" Proxy" ]
2165 pub struct _Usart2rstW<'a> {
2166 register: &'a mut W,
2167 }
2168 impl<'a> _Usart2rstW<'a> {
2169 # [ doc = r" Writes raw `bits` to the field" ]
2170 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2171 const MASK: u8 = 1;
2172 const OFFSET: u8 = 17;
2173 self.register.bits &= !((MASK as u32) << OFFSET);
2174 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2175 self.register
2176 }
2177 }
2178 # [ doc = r" Proxy" ]
2179 pub struct _Usart3rstW<'a> {
2180 register: &'a mut W,
2181 }
2182 impl<'a> _Usart3rstW<'a> {
2183 # [ doc = r" Writes raw `bits` to the field" ]
2184 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2185 const MASK: u8 = 1;
2186 const OFFSET: u8 = 18;
2187 self.register.bits &= !((MASK as u32) << OFFSET);
2188 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2189 self.register
2190 }
2191 }
2192 # [ doc = r" Proxy" ]
2193 pub struct _Usart4rstW<'a> {
2194 register: &'a mut W,
2195 }
2196 impl<'a> _Usart4rstW<'a> {
2197 # [ doc = r" Writes raw `bits` to the field" ]
2198 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2199 const MASK: u8 = 1;
2200 const OFFSET: u8 = 19;
2201 self.register.bits &= !((MASK as u32) << OFFSET);
2202 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2203 self.register
2204 }
2205 }
2206 # [ doc = r" Proxy" ]
2207 pub struct _I2c1rstW<'a> {
2208 register: &'a mut W,
2209 }
2210 impl<'a> _I2c1rstW<'a> {
2211 # [ doc = r" Writes raw `bits` to the field" ]
2212 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2213 const MASK: u8 = 1;
2214 const OFFSET: u8 = 21;
2215 self.register.bits &= !((MASK as u32) << OFFSET);
2216 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2217 self.register
2218 }
2219 }
2220 # [ doc = r" Proxy" ]
2221 pub struct _I2c2rstW<'a> {
2222 register: &'a mut W,
2223 }
2224 impl<'a> _I2c2rstW<'a> {
2225 # [ doc = r" Writes raw `bits` to the field" ]
2226 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2227 const MASK: u8 = 1;
2228 const OFFSET: u8 = 22;
2229 self.register.bits &= !((MASK as u32) << OFFSET);
2230 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2231 self.register
2232 }
2233 }
2234 # [ doc = r" Proxy" ]
2235 pub struct _UsbrstW<'a> {
2236 register: &'a mut W,
2237 }
2238 impl<'a> _UsbrstW<'a> {
2239 # [ doc = r" Writes raw `bits` to the field" ]
2240 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2241 const MASK: u8 = 1;
2242 const OFFSET: u8 = 23;
2243 self.register.bits &= !((MASK as u32) << OFFSET);
2244 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2245 self.register
2246 }
2247 }
2248 # [ doc = r" Proxy" ]
2249 pub struct _CanrstW<'a> {
2250 register: &'a mut W,
2251 }
2252 impl<'a> _CanrstW<'a> {
2253 # [ doc = r" Writes raw `bits` to the field" ]
2254 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2255 const MASK: u8 = 1;
2256 const OFFSET: u8 = 25;
2257 self.register.bits &= !((MASK as u32) << OFFSET);
2258 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2259 self.register
2260 }
2261 }
2262 # [ doc = r" Proxy" ]
2263 pub struct _CrsrstW<'a> {
2264 register: &'a mut W,
2265 }
2266 impl<'a> _CrsrstW<'a> {
2267 # [ doc = r" Writes raw `bits` to the field" ]
2268 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2269 const MASK: u8 = 1;
2270 const OFFSET: u8 = 27;
2271 self.register.bits &= !((MASK as u32) << OFFSET);
2272 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2273 self.register
2274 }
2275 }
2276 # [ doc = r" Proxy" ]
2277 pub struct _PwrrstW<'a> {
2278 register: &'a mut W,
2279 }
2280 impl<'a> _PwrrstW<'a> {
2281 # [ doc = r" Writes raw `bits` to the field" ]
2282 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2283 const MASK: u8 = 1;
2284 const OFFSET: u8 = 28;
2285 self.register.bits &= !((MASK as u32) << OFFSET);
2286 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2287 self.register
2288 }
2289 }
2290 # [ doc = r" Proxy" ]
2291 pub struct _DacrstW<'a> {
2292 register: &'a mut W,
2293 }
2294 impl<'a> _DacrstW<'a> {
2295 # [ doc = r" Writes raw `bits` to the field" ]
2296 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2297 const MASK: u8 = 1;
2298 const OFFSET: u8 = 29;
2299 self.register.bits &= !((MASK as u32) << OFFSET);
2300 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2301 self.register
2302 }
2303 }
2304 # [ doc = r" Proxy" ]
2305 pub struct _CecrstW<'a> {
2306 register: &'a mut W,
2307 }
2308 impl<'a> _CecrstW<'a> {
2309 # [ doc = r" Writes raw `bits` to the field" ]
2310 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2311 const MASK: u8 = 1;
2312 const OFFSET: u8 = 30;
2313 self.register.bits &= !((MASK as u32) << OFFSET);
2314 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2315 self.register
2316 }
2317 }
2318 impl R {
2319 # [ doc = r" Value of the register as raw bits" ]
2320 pub fn bits(&self) -> u32 {
2321 self.bits
2322 }
2323 fn _tim2rst(&self) -> u8 {
2324 const MASK: u8 = 1;
2325 const OFFSET: u8 = 0;
2326 ((self.bits >> OFFSET) & MASK as u32) as u8
2327 }
2328 # [ doc = "Bit 0 - Timer 2 reset" ]
2329 pub fn tim2rst(&self) -> Tim2rstR {
2330 Tim2rstR { bits: self._tim2rst() }
2331 }
2332 fn _tim3rst(&self) -> u8 {
2333 const MASK: u8 = 1;
2334 const OFFSET: u8 = 1;
2335 ((self.bits >> OFFSET) & MASK as u32) as u8
2336 }
2337 # [ doc = "Bit 1 - Timer 3 reset" ]
2338 pub fn tim3rst(&self) -> Tim3rstR {
2339 Tim3rstR { bits: self._tim3rst() }
2340 }
2341 fn _tim6rst(&self) -> u8 {
2342 const MASK: u8 = 1;
2343 const OFFSET: u8 = 4;
2344 ((self.bits >> OFFSET) & MASK as u32) as u8
2345 }
2346 # [ doc = "Bit 4 - Timer 6 reset" ]
2347 pub fn tim6rst(&self) -> Tim6rstR {
2348 Tim6rstR { bits: self._tim6rst() }
2349 }
2350 fn _tim7rst(&self) -> u8 {
2351 const MASK: u8 = 1;
2352 const OFFSET: u8 = 5;
2353 ((self.bits >> OFFSET) & MASK as u32) as u8
2354 }
2355 # [ doc = "Bit 5 - TIM7 timer reset" ]
2356 pub fn tim7rst(&self) -> Tim7rstR {
2357 Tim7rstR { bits: self._tim7rst() }
2358 }
2359 fn _tim14rst(&self) -> u8 {
2360 const MASK: u8 = 1;
2361 const OFFSET: u8 = 8;
2362 ((self.bits >> OFFSET) & MASK as u32) as u8
2363 }
2364 # [ doc = "Bit 8 - Timer 14 reset" ]
2365 pub fn tim14rst(&self) -> Tim14rstR {
2366 Tim14rstR { bits: self._tim14rst() }
2367 }
2368 fn _wwdgrst(&self) -> u8 {
2369 const MASK: u8 = 1;
2370 const OFFSET: u8 = 11;
2371 ((self.bits >> OFFSET) & MASK as u32) as u8
2372 }
2373 # [ doc = "Bit 11 - Window watchdog reset" ]
2374 pub fn wwdgrst(&self) -> WwdgrstR {
2375 WwdgrstR { bits: self._wwdgrst() }
2376 }
2377 fn _spi2rst(&self) -> u8 {
2378 const MASK: u8 = 1;
2379 const OFFSET: u8 = 14;
2380 ((self.bits >> OFFSET) & MASK as u32) as u8
2381 }
2382 # [ doc = "Bit 14 - SPI2 reset" ]
2383 pub fn spi2rst(&self) -> Spi2rstR {
2384 Spi2rstR { bits: self._spi2rst() }
2385 }
2386 fn _usart2rst(&self) -> u8 {
2387 const MASK: u8 = 1;
2388 const OFFSET: u8 = 17;
2389 ((self.bits >> OFFSET) & MASK as u32) as u8
2390 }
2391 # [ doc = "Bit 17 - USART 2 reset" ]
2392 pub fn usart2rst(&self) -> Usart2rstR {
2393 Usart2rstR { bits: self._usart2rst() }
2394 }
2395 fn _usart3rst(&self) -> u8 {
2396 const MASK: u8 = 1;
2397 const OFFSET: u8 = 18;
2398 ((self.bits >> OFFSET) & MASK as u32) as u8
2399 }
2400 # [ doc = "Bit 18 - USART3 reset" ]
2401 pub fn usart3rst(&self) -> Usart3rstR {
2402 Usart3rstR { bits: self._usart3rst() }
2403 }
2404 fn _usart4rst(&self) -> u8 {
2405 const MASK: u8 = 1;
2406 const OFFSET: u8 = 19;
2407 ((self.bits >> OFFSET) & MASK as u32) as u8
2408 }
2409 # [ doc = "Bit 19 - USART4 reset" ]
2410 pub fn usart4rst(&self) -> Usart4rstR {
2411 Usart4rstR { bits: self._usart4rst() }
2412 }
2413 fn _i2c1rst(&self) -> u8 {
2414 const MASK: u8 = 1;
2415 const OFFSET: u8 = 21;
2416 ((self.bits >> OFFSET) & MASK as u32) as u8
2417 }
2418 # [ doc = "Bit 21 - I2C1 reset" ]
2419 pub fn i2c1rst(&self) -> I2c1rstR {
2420 I2c1rstR { bits: self._i2c1rst() }
2421 }
2422 fn _i2c2rst(&self) -> u8 {
2423 const MASK: u8 = 1;
2424 const OFFSET: u8 = 22;
2425 ((self.bits >> OFFSET) & MASK as u32) as u8
2426 }
2427 # [ doc = "Bit 22 - I2C2 reset" ]
2428 pub fn i2c2rst(&self) -> I2c2rstR {
2429 I2c2rstR { bits: self._i2c2rst() }
2430 }
2431 fn _usbrst(&self) -> u8 {
2432 const MASK: u8 = 1;
2433 const OFFSET: u8 = 23;
2434 ((self.bits >> OFFSET) & MASK as u32) as u8
2435 }
2436 # [ doc = "Bit 23 - USB interface reset" ]
2437 pub fn usbrst(&self) -> UsbrstR {
2438 UsbrstR { bits: self._usbrst() }
2439 }
2440 fn _canrst(&self) -> u8 {
2441 const MASK: u8 = 1;
2442 const OFFSET: u8 = 25;
2443 ((self.bits >> OFFSET) & MASK as u32) as u8
2444 }
2445 # [ doc = "Bit 25 - CAN interface reset" ]
2446 pub fn canrst(&self) -> CanrstR {
2447 CanrstR { bits: self._canrst() }
2448 }
2449 fn _crsrst(&self) -> u8 {
2450 const MASK: u8 = 1;
2451 const OFFSET: u8 = 27;
2452 ((self.bits >> OFFSET) & MASK as u32) as u8
2453 }
2454 # [ doc = "Bit 27 - Clock Recovery System interface reset" ]
2455 pub fn crsrst(&self) -> CrsrstR {
2456 CrsrstR { bits: self._crsrst() }
2457 }
2458 fn _pwrrst(&self) -> u8 {
2459 const MASK: u8 = 1;
2460 const OFFSET: u8 = 28;
2461 ((self.bits >> OFFSET) & MASK as u32) as u8
2462 }
2463 # [ doc = "Bit 28 - Power interface reset" ]
2464 pub fn pwrrst(&self) -> PwrrstR {
2465 PwrrstR { bits: self._pwrrst() }
2466 }
2467 fn _dacrst(&self) -> u8 {
2468 const MASK: u8 = 1;
2469 const OFFSET: u8 = 29;
2470 ((self.bits >> OFFSET) & MASK as u32) as u8
2471 }
2472 # [ doc = "Bit 29 - DAC interface reset" ]
2473 pub fn dacrst(&self) -> DacrstR {
2474 DacrstR { bits: self._dacrst() }
2475 }
2476 fn _cecrst(&self) -> u8 {
2477 const MASK: u8 = 1;
2478 const OFFSET: u8 = 30;
2479 ((self.bits >> OFFSET) & MASK as u32) as u8
2480 }
2481 # [ doc = "Bit 30 - HDMI CEC reset" ]
2482 pub fn cecrst(&self) -> CecrstR {
2483 CecrstR { bits: self._cecrst() }
2484 }
2485 }
2486 impl W {
2487 # [ doc = r" Reset value of the register" ]
2488 pub fn reset_value() -> W {
2489 W { bits: 0 }
2490 }
2491 # [ doc = r" Writes raw `bits` to the register" ]
2492 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
2493 self.bits = bits;
2494 self
2495 }
2496 # [ doc = "Bit 0 - Timer 2 reset" ]
2497 pub fn tim2rst(&mut self) -> _Tim2rstW {
2498 _Tim2rstW { register: self }
2499 }
2500 # [ doc = "Bit 1 - Timer 3 reset" ]
2501 pub fn tim3rst(&mut self) -> _Tim3rstW {
2502 _Tim3rstW { register: self }
2503 }
2504 # [ doc = "Bit 4 - Timer 6 reset" ]
2505 pub fn tim6rst(&mut self) -> _Tim6rstW {
2506 _Tim6rstW { register: self }
2507 }
2508 # [ doc = "Bit 5 - TIM7 timer reset" ]
2509 pub fn tim7rst(&mut self) -> _Tim7rstW {
2510 _Tim7rstW { register: self }
2511 }
2512 # [ doc = "Bit 8 - Timer 14 reset" ]
2513 pub fn tim14rst(&mut self) -> _Tim14rstW {
2514 _Tim14rstW { register: self }
2515 }
2516 # [ doc = "Bit 11 - Window watchdog reset" ]
2517 pub fn wwdgrst(&mut self) -> _WwdgrstW {
2518 _WwdgrstW { register: self }
2519 }
2520 # [ doc = "Bit 14 - SPI2 reset" ]
2521 pub fn spi2rst(&mut self) -> _Spi2rstW {
2522 _Spi2rstW { register: self }
2523 }
2524 # [ doc = "Bit 17 - USART 2 reset" ]
2525 pub fn usart2rst(&mut self) -> _Usart2rstW {
2526 _Usart2rstW { register: self }
2527 }
2528 # [ doc = "Bit 18 - USART3 reset" ]
2529 pub fn usart3rst(&mut self) -> _Usart3rstW {
2530 _Usart3rstW { register: self }
2531 }
2532 # [ doc = "Bit 19 - USART4 reset" ]
2533 pub fn usart4rst(&mut self) -> _Usart4rstW {
2534 _Usart4rstW { register: self }
2535 }
2536 # [ doc = "Bit 21 - I2C1 reset" ]
2537 pub fn i2c1rst(&mut self) -> _I2c1rstW {
2538 _I2c1rstW { register: self }
2539 }
2540 # [ doc = "Bit 22 - I2C2 reset" ]
2541 pub fn i2c2rst(&mut self) -> _I2c2rstW {
2542 _I2c2rstW { register: self }
2543 }
2544 # [ doc = "Bit 23 - USB interface reset" ]
2545 pub fn usbrst(&mut self) -> _UsbrstW {
2546 _UsbrstW { register: self }
2547 }
2548 # [ doc = "Bit 25 - CAN interface reset" ]
2549 pub fn canrst(&mut self) -> _CanrstW {
2550 _CanrstW { register: self }
2551 }
2552 # [ doc = "Bit 27 - Clock Recovery System interface reset" ]
2553 pub fn crsrst(&mut self) -> _CrsrstW {
2554 _CrsrstW { register: self }
2555 }
2556 # [ doc = "Bit 28 - Power interface reset" ]
2557 pub fn pwrrst(&mut self) -> _PwrrstW {
2558 _PwrrstW { register: self }
2559 }
2560 # [ doc = "Bit 29 - DAC interface reset" ]
2561 pub fn dacrst(&mut self) -> _DacrstW {
2562 _DacrstW { register: self }
2563 }
2564 # [ doc = "Bit 30 - HDMI CEC reset" ]
2565 pub fn cecrst(&mut self) -> _CecrstW {
2566 _CecrstW { register: self }
2567 }
2568 }
2569}
2570
2571# [ doc = "AHB Peripheral Clock enable register (RCC_AHBENR)" ]
2572# [ repr ( C ) ]
2573pub struct Ahbenr {
2574 register: ::volatile_register::RW<u32>,
2575}
2576
2577# [ doc = "AHB Peripheral Clock enable register (RCC_AHBENR)" ]
2578pub mod ahbenr {
2579 # [ doc = r" Value read from the register" ]
2580 pub struct R {
2581 bits: u32,
2582 }
2583 # [ doc = r" Value to write to the register" ]
2584 pub struct W {
2585 bits: u32,
2586 }
2587 impl super::Ahbenr {
2588 # [ doc = r" Modifies the contents of the register" ]
2589 pub fn modify<F>(&mut self, f: F)
2590 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
2591 {
2592 let bits = self.register.read();
2593 let r = R { bits: bits };
2594 let mut w = W { bits: bits };
2595 f(&r, &mut w);
2596 self.register.write(w.bits);
2597 }
2598 # [ doc = r" Reads the contents of the register" ]
2599 pub fn read(&self) -> R {
2600 R { bits: self.register.read() }
2601 }
2602 # [ doc = r" Writes to the register" ]
2603 pub fn write<F>(&mut self, f: F)
2604 where F: FnOnce(&mut W) -> &mut W
2605 {
2606 let mut w = W::reset_value();
2607 f(&mut w);
2608 self.register.write(w.bits);
2609 }
2610 }
2611 # [ doc = "Value of the field DMAEN" ]
2612 pub struct DmaenR {
2613 bits: u8,
2614 }
2615 impl DmaenR {
2616 # [ doc = r" Value of the field as raw bits" ]
2617 pub fn bits(&self) -> u8 {
2618 self.bits
2619 }
2620 }
2621 # [ doc = "Value of the field SRAMEN" ]
2622 pub struct SramenR {
2623 bits: u8,
2624 }
2625 impl SramenR {
2626 # [ doc = r" Value of the field as raw bits" ]
2627 pub fn bits(&self) -> u8 {
2628 self.bits
2629 }
2630 }
2631 # [ doc = "Value of the field FLITFEN" ]
2632 pub struct FlitfenR {
2633 bits: u8,
2634 }
2635 impl FlitfenR {
2636 # [ doc = r" Value of the field as raw bits" ]
2637 pub fn bits(&self) -> u8 {
2638 self.bits
2639 }
2640 }
2641 # [ doc = "Value of the field CRCEN" ]
2642 pub struct CrcenR {
2643 bits: u8,
2644 }
2645 impl CrcenR {
2646 # [ doc = r" Value of the field as raw bits" ]
2647 pub fn bits(&self) -> u8 {
2648 self.bits
2649 }
2650 }
2651 # [ doc = "Value of the field IOPAEN" ]
2652 pub struct IopaenR {
2653 bits: u8,
2654 }
2655 impl IopaenR {
2656 # [ doc = r" Value of the field as raw bits" ]
2657 pub fn bits(&self) -> u8 {
2658 self.bits
2659 }
2660 }
2661 # [ doc = "Value of the field IOPBEN" ]
2662 pub struct IopbenR {
2663 bits: u8,
2664 }
2665 impl IopbenR {
2666 # [ doc = r" Value of the field as raw bits" ]
2667 pub fn bits(&self) -> u8 {
2668 self.bits
2669 }
2670 }
2671 # [ doc = "Value of the field IOPCEN" ]
2672 pub struct IopcenR {
2673 bits: u8,
2674 }
2675 impl IopcenR {
2676 # [ doc = r" Value of the field as raw bits" ]
2677 pub fn bits(&self) -> u8 {
2678 self.bits
2679 }
2680 }
2681 # [ doc = "Value of the field IOPDEN" ]
2682 pub struct IopdenR {
2683 bits: u8,
2684 }
2685 impl IopdenR {
2686 # [ doc = r" Value of the field as raw bits" ]
2687 pub fn bits(&self) -> u8 {
2688 self.bits
2689 }
2690 }
2691 # [ doc = "Value of the field IOPFEN" ]
2692 pub struct IopfenR {
2693 bits: u8,
2694 }
2695 impl IopfenR {
2696 # [ doc = r" Value of the field as raw bits" ]
2697 pub fn bits(&self) -> u8 {
2698 self.bits
2699 }
2700 }
2701 # [ doc = "Value of the field TSCEN" ]
2702 pub struct TscenR {
2703 bits: u8,
2704 }
2705 impl TscenR {
2706 # [ doc = r" Value of the field as raw bits" ]
2707 pub fn bits(&self) -> u8 {
2708 self.bits
2709 }
2710 }
2711 # [ doc = r" Proxy" ]
2712 pub struct _DmaenW<'a> {
2713 register: &'a mut W,
2714 }
2715 impl<'a> _DmaenW<'a> {
2716 # [ doc = r" Writes raw `bits` to the field" ]
2717 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2718 const MASK: u8 = 1;
2719 const OFFSET: u8 = 0;
2720 self.register.bits &= !((MASK as u32) << OFFSET);
2721 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2722 self.register
2723 }
2724 }
2725 # [ doc = r" Proxy" ]
2726 pub struct _SramenW<'a> {
2727 register: &'a mut W,
2728 }
2729 impl<'a> _SramenW<'a> {
2730 # [ doc = r" Writes raw `bits` to the field" ]
2731 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2732 const MASK: u8 = 1;
2733 const OFFSET: u8 = 2;
2734 self.register.bits &= !((MASK as u32) << OFFSET);
2735 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2736 self.register
2737 }
2738 }
2739 # [ doc = r" Proxy" ]
2740 pub struct _FlitfenW<'a> {
2741 register: &'a mut W,
2742 }
2743 impl<'a> _FlitfenW<'a> {
2744 # [ doc = r" Writes raw `bits` to the field" ]
2745 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2746 const MASK: u8 = 1;
2747 const OFFSET: u8 = 4;
2748 self.register.bits &= !((MASK as u32) << OFFSET);
2749 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2750 self.register
2751 }
2752 }
2753 # [ doc = r" Proxy" ]
2754 pub struct _CrcenW<'a> {
2755 register: &'a mut W,
2756 }
2757 impl<'a> _CrcenW<'a> {
2758 # [ doc = r" Writes raw `bits` to the field" ]
2759 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2760 const MASK: u8 = 1;
2761 const OFFSET: u8 = 6;
2762 self.register.bits &= !((MASK as u32) << OFFSET);
2763 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2764 self.register
2765 }
2766 }
2767 # [ doc = r" Proxy" ]
2768 pub struct _IopaenW<'a> {
2769 register: &'a mut W,
2770 }
2771 impl<'a> _IopaenW<'a> {
2772 # [ doc = r" Writes raw `bits` to the field" ]
2773 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2774 const MASK: u8 = 1;
2775 const OFFSET: u8 = 17;
2776 self.register.bits &= !((MASK as u32) << OFFSET);
2777 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2778 self.register
2779 }
2780 }
2781 # [ doc = r" Proxy" ]
2782 pub struct _IopbenW<'a> {
2783 register: &'a mut W,
2784 }
2785 impl<'a> _IopbenW<'a> {
2786 # [ doc = r" Writes raw `bits` to the field" ]
2787 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2788 const MASK: u8 = 1;
2789 const OFFSET: u8 = 18;
2790 self.register.bits &= !((MASK as u32) << OFFSET);
2791 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2792 self.register
2793 }
2794 }
2795 # [ doc = r" Proxy" ]
2796 pub struct _IopcenW<'a> {
2797 register: &'a mut W,
2798 }
2799 impl<'a> _IopcenW<'a> {
2800 # [ doc = r" Writes raw `bits` to the field" ]
2801 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2802 const MASK: u8 = 1;
2803 const OFFSET: u8 = 19;
2804 self.register.bits &= !((MASK as u32) << OFFSET);
2805 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2806 self.register
2807 }
2808 }
2809 # [ doc = r" Proxy" ]
2810 pub struct _IopdenW<'a> {
2811 register: &'a mut W,
2812 }
2813 impl<'a> _IopdenW<'a> {
2814 # [ doc = r" Writes raw `bits` to the field" ]
2815 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2816 const MASK: u8 = 1;
2817 const OFFSET: u8 = 20;
2818 self.register.bits &= !((MASK as u32) << OFFSET);
2819 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2820 self.register
2821 }
2822 }
2823 # [ doc = r" Proxy" ]
2824 pub struct _IopfenW<'a> {
2825 register: &'a mut W,
2826 }
2827 impl<'a> _IopfenW<'a> {
2828 # [ doc = r" Writes raw `bits` to the field" ]
2829 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2830 const MASK: u8 = 1;
2831 const OFFSET: u8 = 22;
2832 self.register.bits &= !((MASK as u32) << OFFSET);
2833 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2834 self.register
2835 }
2836 }
2837 # [ doc = r" Proxy" ]
2838 pub struct _TscenW<'a> {
2839 register: &'a mut W,
2840 }
2841 impl<'a> _TscenW<'a> {
2842 # [ doc = r" Writes raw `bits` to the field" ]
2843 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2844 const MASK: u8 = 1;
2845 const OFFSET: u8 = 24;
2846 self.register.bits &= !((MASK as u32) << OFFSET);
2847 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2848 self.register
2849 }
2850 }
2851 impl R {
2852 # [ doc = r" Value of the register as raw bits" ]
2853 pub fn bits(&self) -> u32 {
2854 self.bits
2855 }
2856 fn _dmaen(&self) -> u8 {
2857 const MASK: u8 = 1;
2858 const OFFSET: u8 = 0;
2859 ((self.bits >> OFFSET) & MASK as u32) as u8
2860 }
2861 # [ doc = "Bit 0 - DMA1 clock enable" ]
2862 pub fn dmaen(&self) -> DmaenR {
2863 DmaenR { bits: self._dmaen() }
2864 }
2865 fn _sramen(&self) -> u8 {
2866 const MASK: u8 = 1;
2867 const OFFSET: u8 = 2;
2868 ((self.bits >> OFFSET) & MASK as u32) as u8
2869 }
2870 # [ doc = "Bit 2 - SRAM interface clock enable" ]
2871 pub fn sramen(&self) -> SramenR {
2872 SramenR { bits: self._sramen() }
2873 }
2874 fn _flitfen(&self) -> u8 {
2875 const MASK: u8 = 1;
2876 const OFFSET: u8 = 4;
2877 ((self.bits >> OFFSET) & MASK as u32) as u8
2878 }
2879 # [ doc = "Bit 4 - FLITF clock enable" ]
2880 pub fn flitfen(&self) -> FlitfenR {
2881 FlitfenR { bits: self._flitfen() }
2882 }
2883 fn _crcen(&self) -> u8 {
2884 const MASK: u8 = 1;
2885 const OFFSET: u8 = 6;
2886 ((self.bits >> OFFSET) & MASK as u32) as u8
2887 }
2888 # [ doc = "Bit 6 - CRC clock enable" ]
2889 pub fn crcen(&self) -> CrcenR {
2890 CrcenR { bits: self._crcen() }
2891 }
2892 fn _iopaen(&self) -> u8 {
2893 const MASK: u8 = 1;
2894 const OFFSET: u8 = 17;
2895 ((self.bits >> OFFSET) & MASK as u32) as u8
2896 }
2897 # [ doc = "Bit 17 - I/O port A clock enable" ]
2898 pub fn iopaen(&self) -> IopaenR {
2899 IopaenR { bits: self._iopaen() }
2900 }
2901 fn _iopben(&self) -> u8 {
2902 const MASK: u8 = 1;
2903 const OFFSET: u8 = 18;
2904 ((self.bits >> OFFSET) & MASK as u32) as u8
2905 }
2906 # [ doc = "Bit 18 - I/O port B clock enable" ]
2907 pub fn iopben(&self) -> IopbenR {
2908 IopbenR { bits: self._iopben() }
2909 }
2910 fn _iopcen(&self) -> u8 {
2911 const MASK: u8 = 1;
2912 const OFFSET: u8 = 19;
2913 ((self.bits >> OFFSET) & MASK as u32) as u8
2914 }
2915 # [ doc = "Bit 19 - I/O port C clock enable" ]
2916 pub fn iopcen(&self) -> IopcenR {
2917 IopcenR { bits: self._iopcen() }
2918 }
2919 fn _iopden(&self) -> u8 {
2920 const MASK: u8 = 1;
2921 const OFFSET: u8 = 20;
2922 ((self.bits >> OFFSET) & MASK as u32) as u8
2923 }
2924 # [ doc = "Bit 20 - I/O port D clock enable" ]
2925 pub fn iopden(&self) -> IopdenR {
2926 IopdenR { bits: self._iopden() }
2927 }
2928 fn _iopfen(&self) -> u8 {
2929 const MASK: u8 = 1;
2930 const OFFSET: u8 = 22;
2931 ((self.bits >> OFFSET) & MASK as u32) as u8
2932 }
2933 # [ doc = "Bit 22 - I/O port F clock enable" ]
2934 pub fn iopfen(&self) -> IopfenR {
2935 IopfenR { bits: self._iopfen() }
2936 }
2937 fn _tscen(&self) -> u8 {
2938 const MASK: u8 = 1;
2939 const OFFSET: u8 = 24;
2940 ((self.bits >> OFFSET) & MASK as u32) as u8
2941 }
2942 # [ doc = "Bit 24 - Touch sensing controller clock enable" ]
2943 pub fn tscen(&self) -> TscenR {
2944 TscenR { bits: self._tscen() }
2945 }
2946 }
2947 impl W {
2948 # [ doc = r" Reset value of the register" ]
2949 pub fn reset_value() -> W {
2950 W { bits: 20 }
2951 }
2952 # [ doc = r" Writes raw `bits` to the register" ]
2953 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
2954 self.bits = bits;
2955 self
2956 }
2957 # [ doc = "Bit 0 - DMA1 clock enable" ]
2958 pub fn dmaen(&mut self) -> _DmaenW {
2959 _DmaenW { register: self }
2960 }
2961 # [ doc = "Bit 2 - SRAM interface clock enable" ]
2962 pub fn sramen(&mut self) -> _SramenW {
2963 _SramenW { register: self }
2964 }
2965 # [ doc = "Bit 4 - FLITF clock enable" ]
2966 pub fn flitfen(&mut self) -> _FlitfenW {
2967 _FlitfenW { register: self }
2968 }
2969 # [ doc = "Bit 6 - CRC clock enable" ]
2970 pub fn crcen(&mut self) -> _CrcenW {
2971 _CrcenW { register: self }
2972 }
2973 # [ doc = "Bit 17 - I/O port A clock enable" ]
2974 pub fn iopaen(&mut self) -> _IopaenW {
2975 _IopaenW { register: self }
2976 }
2977 # [ doc = "Bit 18 - I/O port B clock enable" ]
2978 pub fn iopben(&mut self) -> _IopbenW {
2979 _IopbenW { register: self }
2980 }
2981 # [ doc = "Bit 19 - I/O port C clock enable" ]
2982 pub fn iopcen(&mut self) -> _IopcenW {
2983 _IopcenW { register: self }
2984 }
2985 # [ doc = "Bit 20 - I/O port D clock enable" ]
2986 pub fn iopden(&mut self) -> _IopdenW {
2987 _IopdenW { register: self }
2988 }
2989 # [ doc = "Bit 22 - I/O port F clock enable" ]
2990 pub fn iopfen(&mut self) -> _IopfenW {
2991 _IopfenW { register: self }
2992 }
2993 # [ doc = "Bit 24 - Touch sensing controller clock enable" ]
2994 pub fn tscen(&mut self) -> _TscenW {
2995 _TscenW { register: self }
2996 }
2997 }
2998}
2999
3000# [ doc = "APB2 peripheral clock enable register (RCC_APB2ENR)" ]
3001# [ repr ( C ) ]
3002pub struct Apb2enr {
3003 register: ::volatile_register::RW<u32>,
3004}
3005
3006# [ doc = "APB2 peripheral clock enable register (RCC_APB2ENR)" ]
3007pub mod apb2enr {
3008 # [ doc = r" Value read from the register" ]
3009 pub struct R {
3010 bits: u32,
3011 }
3012 # [ doc = r" Value to write to the register" ]
3013 pub struct W {
3014 bits: u32,
3015 }
3016 impl super::Apb2enr {
3017 # [ doc = r" Modifies the contents of the register" ]
3018 pub fn modify<F>(&mut self, f: F)
3019 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
3020 {
3021 let bits = self.register.read();
3022 let r = R { bits: bits };
3023 let mut w = W { bits: bits };
3024 f(&r, &mut w);
3025 self.register.write(w.bits);
3026 }
3027 # [ doc = r" Reads the contents of the register" ]
3028 pub fn read(&self) -> R {
3029 R { bits: self.register.read() }
3030 }
3031 # [ doc = r" Writes to the register" ]
3032 pub fn write<F>(&mut self, f: F)
3033 where F: FnOnce(&mut W) -> &mut W
3034 {
3035 let mut w = W::reset_value();
3036 f(&mut w);
3037 self.register.write(w.bits);
3038 }
3039 }
3040 # [ doc = "Value of the field SYSCFGEN" ]
3041 pub struct SyscfgenR {
3042 bits: u8,
3043 }
3044 impl SyscfgenR {
3045 # [ doc = r" Value of the field as raw bits" ]
3046 pub fn bits(&self) -> u8 {
3047 self.bits
3048 }
3049 }
3050 # [ doc = "Value of the field ADCEN" ]
3051 pub struct AdcenR {
3052 bits: u8,
3053 }
3054 impl AdcenR {
3055 # [ doc = r" Value of the field as raw bits" ]
3056 pub fn bits(&self) -> u8 {
3057 self.bits
3058 }
3059 }
3060 # [ doc = "Value of the field TIM1EN" ]
3061 pub struct Tim1enR {
3062 bits: u8,
3063 }
3064 impl Tim1enR {
3065 # [ doc = r" Value of the field as raw bits" ]
3066 pub fn bits(&self) -> u8 {
3067 self.bits
3068 }
3069 }
3070 # [ doc = "Value of the field SPI1EN" ]
3071 pub struct Spi1enR {
3072 bits: u8,
3073 }
3074 impl Spi1enR {
3075 # [ doc = r" Value of the field as raw bits" ]
3076 pub fn bits(&self) -> u8 {
3077 self.bits
3078 }
3079 }
3080 # [ doc = "Value of the field USART1EN" ]
3081 pub struct Usart1enR {
3082 bits: u8,
3083 }
3084 impl Usart1enR {
3085 # [ doc = r" Value of the field as raw bits" ]
3086 pub fn bits(&self) -> u8 {
3087 self.bits
3088 }
3089 }
3090 # [ doc = "Value of the field TIM15EN" ]
3091 pub struct Tim15enR {
3092 bits: u8,
3093 }
3094 impl Tim15enR {
3095 # [ doc = r" Value of the field as raw bits" ]
3096 pub fn bits(&self) -> u8 {
3097 self.bits
3098 }
3099 }
3100 # [ doc = "Value of the field TIM16EN" ]
3101 pub struct Tim16enR {
3102 bits: u8,
3103 }
3104 impl Tim16enR {
3105 # [ doc = r" Value of the field as raw bits" ]
3106 pub fn bits(&self) -> u8 {
3107 self.bits
3108 }
3109 }
3110 # [ doc = "Value of the field TIM17EN" ]
3111 pub struct Tim17enR {
3112 bits: u8,
3113 }
3114 impl Tim17enR {
3115 # [ doc = r" Value of the field as raw bits" ]
3116 pub fn bits(&self) -> u8 {
3117 self.bits
3118 }
3119 }
3120 # [ doc = "Value of the field DBGMCUEN" ]
3121 pub struct DbgmcuenR {
3122 bits: u8,
3123 }
3124 impl DbgmcuenR {
3125 # [ doc = r" Value of the field as raw bits" ]
3126 pub fn bits(&self) -> u8 {
3127 self.bits
3128 }
3129 }
3130 # [ doc = r" Proxy" ]
3131 pub struct _SyscfgenW<'a> {
3132 register: &'a mut W,
3133 }
3134 impl<'a> _SyscfgenW<'a> {
3135 # [ doc = r" Writes raw `bits` to the field" ]
3136 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3137 const MASK: u8 = 1;
3138 const OFFSET: u8 = 0;
3139 self.register.bits &= !((MASK as u32) << OFFSET);
3140 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3141 self.register
3142 }
3143 }
3144 # [ doc = r" Proxy" ]
3145 pub struct _AdcenW<'a> {
3146 register: &'a mut W,
3147 }
3148 impl<'a> _AdcenW<'a> {
3149 # [ doc = r" Writes raw `bits` to the field" ]
3150 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3151 const MASK: u8 = 1;
3152 const OFFSET: u8 = 9;
3153 self.register.bits &= !((MASK as u32) << OFFSET);
3154 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3155 self.register
3156 }
3157 }
3158 # [ doc = r" Proxy" ]
3159 pub struct _Tim1enW<'a> {
3160 register: &'a mut W,
3161 }
3162 impl<'a> _Tim1enW<'a> {
3163 # [ doc = r" Writes raw `bits` to the field" ]
3164 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3165 const MASK: u8 = 1;
3166 const OFFSET: u8 = 11;
3167 self.register.bits &= !((MASK as u32) << OFFSET);
3168 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3169 self.register
3170 }
3171 }
3172 # [ doc = r" Proxy" ]
3173 pub struct _Spi1enW<'a> {
3174 register: &'a mut W,
3175 }
3176 impl<'a> _Spi1enW<'a> {
3177 # [ doc = r" Writes raw `bits` to the field" ]
3178 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3179 const MASK: u8 = 1;
3180 const OFFSET: u8 = 12;
3181 self.register.bits &= !((MASK as u32) << OFFSET);
3182 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3183 self.register
3184 }
3185 }
3186 # [ doc = r" Proxy" ]
3187 pub struct _Usart1enW<'a> {
3188 register: &'a mut W,
3189 }
3190 impl<'a> _Usart1enW<'a> {
3191 # [ doc = r" Writes raw `bits` to the field" ]
3192 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3193 const MASK: u8 = 1;
3194 const OFFSET: u8 = 14;
3195 self.register.bits &= !((MASK as u32) << OFFSET);
3196 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3197 self.register
3198 }
3199 }
3200 # [ doc = r" Proxy" ]
3201 pub struct _Tim15enW<'a> {
3202 register: &'a mut W,
3203 }
3204 impl<'a> _Tim15enW<'a> {
3205 # [ doc = r" Writes raw `bits` to the field" ]
3206 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3207 const MASK: u8 = 1;
3208 const OFFSET: u8 = 16;
3209 self.register.bits &= !((MASK as u32) << OFFSET);
3210 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3211 self.register
3212 }
3213 }
3214 # [ doc = r" Proxy" ]
3215 pub struct _Tim16enW<'a> {
3216 register: &'a mut W,
3217 }
3218 impl<'a> _Tim16enW<'a> {
3219 # [ doc = r" Writes raw `bits` to the field" ]
3220 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3221 const MASK: u8 = 1;
3222 const OFFSET: u8 = 17;
3223 self.register.bits &= !((MASK as u32) << OFFSET);
3224 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3225 self.register
3226 }
3227 }
3228 # [ doc = r" Proxy" ]
3229 pub struct _Tim17enW<'a> {
3230 register: &'a mut W,
3231 }
3232 impl<'a> _Tim17enW<'a> {
3233 # [ doc = r" Writes raw `bits` to the field" ]
3234 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3235 const MASK: u8 = 1;
3236 const OFFSET: u8 = 18;
3237 self.register.bits &= !((MASK as u32) << OFFSET);
3238 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3239 self.register
3240 }
3241 }
3242 # [ doc = r" Proxy" ]
3243 pub struct _DbgmcuenW<'a> {
3244 register: &'a mut W,
3245 }
3246 impl<'a> _DbgmcuenW<'a> {
3247 # [ doc = r" Writes raw `bits` to the field" ]
3248 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3249 const MASK: u8 = 1;
3250 const OFFSET: u8 = 22;
3251 self.register.bits &= !((MASK as u32) << OFFSET);
3252 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3253 self.register
3254 }
3255 }
3256 impl R {
3257 # [ doc = r" Value of the register as raw bits" ]
3258 pub fn bits(&self) -> u32 {
3259 self.bits
3260 }
3261 fn _syscfgen(&self) -> u8 {
3262 const MASK: u8 = 1;
3263 const OFFSET: u8 = 0;
3264 ((self.bits >> OFFSET) & MASK as u32) as u8
3265 }
3266 # [ doc = "Bit 0 - SYSCFG clock enable" ]
3267 pub fn syscfgen(&self) -> SyscfgenR {
3268 SyscfgenR { bits: self._syscfgen() }
3269 }
3270 fn _adcen(&self) -> u8 {
3271 const MASK: u8 = 1;
3272 const OFFSET: u8 = 9;
3273 ((self.bits >> OFFSET) & MASK as u32) as u8
3274 }
3275 # [ doc = "Bit 9 - ADC 1 interface clock enable" ]
3276 pub fn adcen(&self) -> AdcenR {
3277 AdcenR { bits: self._adcen() }
3278 }
3279 fn _tim1en(&self) -> u8 {
3280 const MASK: u8 = 1;
3281 const OFFSET: u8 = 11;
3282 ((self.bits >> OFFSET) & MASK as u32) as u8
3283 }
3284 # [ doc = "Bit 11 - TIM1 Timer clock enable" ]
3285 pub fn tim1en(&self) -> Tim1enR {
3286 Tim1enR { bits: self._tim1en() }
3287 }
3288 fn _spi1en(&self) -> u8 {
3289 const MASK: u8 = 1;
3290 const OFFSET: u8 = 12;
3291 ((self.bits >> OFFSET) & MASK as u32) as u8
3292 }
3293 # [ doc = "Bit 12 - SPI 1 clock enable" ]
3294 pub fn spi1en(&self) -> Spi1enR {
3295 Spi1enR { bits: self._spi1en() }
3296 }
3297 fn _usart1en(&self) -> u8 {
3298 const MASK: u8 = 1;
3299 const OFFSET: u8 = 14;
3300 ((self.bits >> OFFSET) & MASK as u32) as u8
3301 }
3302 # [ doc = "Bit 14 - USART1 clock enable" ]
3303 pub fn usart1en(&self) -> Usart1enR {
3304 Usart1enR { bits: self._usart1en() }
3305 }
3306 fn _tim15en(&self) -> u8 {
3307 const MASK: u8 = 1;
3308 const OFFSET: u8 = 16;
3309 ((self.bits >> OFFSET) & MASK as u32) as u8
3310 }
3311 # [ doc = "Bit 16 - TIM15 timer clock enable" ]
3312 pub fn tim15en(&self) -> Tim15enR {
3313 Tim15enR { bits: self._tim15en() }
3314 }
3315 fn _tim16en(&self) -> u8 {
3316 const MASK: u8 = 1;
3317 const OFFSET: u8 = 17;
3318 ((self.bits >> OFFSET) & MASK as u32) as u8
3319 }
3320 # [ doc = "Bit 17 - TIM16 timer clock enable" ]
3321 pub fn tim16en(&self) -> Tim16enR {
3322 Tim16enR { bits: self._tim16en() }
3323 }
3324 fn _tim17en(&self) -> u8 {
3325 const MASK: u8 = 1;
3326 const OFFSET: u8 = 18;
3327 ((self.bits >> OFFSET) & MASK as u32) as u8
3328 }
3329 # [ doc = "Bit 18 - TIM17 timer clock enable" ]
3330 pub fn tim17en(&self) -> Tim17enR {
3331 Tim17enR { bits: self._tim17en() }
3332 }
3333 fn _dbgmcuen(&self) -> u8 {
3334 const MASK: u8 = 1;
3335 const OFFSET: u8 = 22;
3336 ((self.bits >> OFFSET) & MASK as u32) as u8
3337 }
3338 # [ doc = "Bit 22 - MCU debug module clock enable" ]
3339 pub fn dbgmcuen(&self) -> DbgmcuenR {
3340 DbgmcuenR { bits: self._dbgmcuen() }
3341 }
3342 }
3343 impl W {
3344 # [ doc = r" Reset value of the register" ]
3345 pub fn reset_value() -> W {
3346 W { bits: 0 }
3347 }
3348 # [ doc = r" Writes raw `bits` to the register" ]
3349 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
3350 self.bits = bits;
3351 self
3352 }
3353 # [ doc = "Bit 0 - SYSCFG clock enable" ]
3354 pub fn syscfgen(&mut self) -> _SyscfgenW {
3355 _SyscfgenW { register: self }
3356 }
3357 # [ doc = "Bit 9 - ADC 1 interface clock enable" ]
3358 pub fn adcen(&mut self) -> _AdcenW {
3359 _AdcenW { register: self }
3360 }
3361 # [ doc = "Bit 11 - TIM1 Timer clock enable" ]
3362 pub fn tim1en(&mut self) -> _Tim1enW {
3363 _Tim1enW { register: self }
3364 }
3365 # [ doc = "Bit 12 - SPI 1 clock enable" ]
3366 pub fn spi1en(&mut self) -> _Spi1enW {
3367 _Spi1enW { register: self }
3368 }
3369 # [ doc = "Bit 14 - USART1 clock enable" ]
3370 pub fn usart1en(&mut self) -> _Usart1enW {
3371 _Usart1enW { register: self }
3372 }
3373 # [ doc = "Bit 16 - TIM15 timer clock enable" ]
3374 pub fn tim15en(&mut self) -> _Tim15enW {
3375 _Tim15enW { register: self }
3376 }
3377 # [ doc = "Bit 17 - TIM16 timer clock enable" ]
3378 pub fn tim16en(&mut self) -> _Tim16enW {
3379 _Tim16enW { register: self }
3380 }
3381 # [ doc = "Bit 18 - TIM17 timer clock enable" ]
3382 pub fn tim17en(&mut self) -> _Tim17enW {
3383 _Tim17enW { register: self }
3384 }
3385 # [ doc = "Bit 22 - MCU debug module clock enable" ]
3386 pub fn dbgmcuen(&mut self) -> _DbgmcuenW {
3387 _DbgmcuenW { register: self }
3388 }
3389 }
3390}
3391
3392# [ doc = "APB1 peripheral clock enable register (RCC_APB1ENR)" ]
3393# [ repr ( C ) ]
3394pub struct Apb1enr {
3395 register: ::volatile_register::RW<u32>,
3396}
3397
3398# [ doc = "APB1 peripheral clock enable register (RCC_APB1ENR)" ]
3399pub mod apb1enr {
3400 # [ doc = r" Value read from the register" ]
3401 pub struct R {
3402 bits: u32,
3403 }
3404 # [ doc = r" Value to write to the register" ]
3405 pub struct W {
3406 bits: u32,
3407 }
3408 impl super::Apb1enr {
3409 # [ doc = r" Modifies the contents of the register" ]
3410 pub fn modify<F>(&mut self, f: F)
3411 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
3412 {
3413 let bits = self.register.read();
3414 let r = R { bits: bits };
3415 let mut w = W { bits: bits };
3416 f(&r, &mut w);
3417 self.register.write(w.bits);
3418 }
3419 # [ doc = r" Reads the contents of the register" ]
3420 pub fn read(&self) -> R {
3421 R { bits: self.register.read() }
3422 }
3423 # [ doc = r" Writes to the register" ]
3424 pub fn write<F>(&mut self, f: F)
3425 where F: FnOnce(&mut W) -> &mut W
3426 {
3427 let mut w = W::reset_value();
3428 f(&mut w);
3429 self.register.write(w.bits);
3430 }
3431 }
3432 # [ doc = "Value of the field TIM2EN" ]
3433 pub struct Tim2enR {
3434 bits: u8,
3435 }
3436 impl Tim2enR {
3437 # [ doc = r" Value of the field as raw bits" ]
3438 pub fn bits(&self) -> u8 {
3439 self.bits
3440 }
3441 }
3442 # [ doc = "Value of the field TIM3EN" ]
3443 pub struct Tim3enR {
3444 bits: u8,
3445 }
3446 impl Tim3enR {
3447 # [ doc = r" Value of the field as raw bits" ]
3448 pub fn bits(&self) -> u8 {
3449 self.bits
3450 }
3451 }
3452 # [ doc = "Value of the field TIM6EN" ]
3453 pub struct Tim6enR {
3454 bits: u8,
3455 }
3456 impl Tim6enR {
3457 # [ doc = r" Value of the field as raw bits" ]
3458 pub fn bits(&self) -> u8 {
3459 self.bits
3460 }
3461 }
3462 # [ doc = "Value of the field TIM7EN" ]
3463 pub struct Tim7enR {
3464 bits: u8,
3465 }
3466 impl Tim7enR {
3467 # [ doc = r" Value of the field as raw bits" ]
3468 pub fn bits(&self) -> u8 {
3469 self.bits
3470 }
3471 }
3472 # [ doc = "Value of the field TIM14EN" ]
3473 pub struct Tim14enR {
3474 bits: u8,
3475 }
3476 impl Tim14enR {
3477 # [ doc = r" Value of the field as raw bits" ]
3478 pub fn bits(&self) -> u8 {
3479 self.bits
3480 }
3481 }
3482 # [ doc = "Value of the field WWDGEN" ]
3483 pub struct WwdgenR {
3484 bits: u8,
3485 }
3486 impl WwdgenR {
3487 # [ doc = r" Value of the field as raw bits" ]
3488 pub fn bits(&self) -> u8 {
3489 self.bits
3490 }
3491 }
3492 # [ doc = "Value of the field SPI2EN" ]
3493 pub struct Spi2enR {
3494 bits: u8,
3495 }
3496 impl Spi2enR {
3497 # [ doc = r" Value of the field as raw bits" ]
3498 pub fn bits(&self) -> u8 {
3499 self.bits
3500 }
3501 }
3502 # [ doc = "Value of the field USART2EN" ]
3503 pub struct Usart2enR {
3504 bits: u8,
3505 }
3506 impl Usart2enR {
3507 # [ doc = r" Value of the field as raw bits" ]
3508 pub fn bits(&self) -> u8 {
3509 self.bits
3510 }
3511 }
3512 # [ doc = "Value of the field USART3EN" ]
3513 pub struct Usart3enR {
3514 bits: u8,
3515 }
3516 impl Usart3enR {
3517 # [ doc = r" Value of the field as raw bits" ]
3518 pub fn bits(&self) -> u8 {
3519 self.bits
3520 }
3521 }
3522 # [ doc = "Value of the field USART4EN" ]
3523 pub struct Usart4enR {
3524 bits: u8,
3525 }
3526 impl Usart4enR {
3527 # [ doc = r" Value of the field as raw bits" ]
3528 pub fn bits(&self) -> u8 {
3529 self.bits
3530 }
3531 }
3532 # [ doc = "Value of the field I2C1EN" ]
3533 pub struct I2c1enR {
3534 bits: u8,
3535 }
3536 impl I2c1enR {
3537 # [ doc = r" Value of the field as raw bits" ]
3538 pub fn bits(&self) -> u8 {
3539 self.bits
3540 }
3541 }
3542 # [ doc = "Value of the field I2C2EN" ]
3543 pub struct I2c2enR {
3544 bits: u8,
3545 }
3546 impl I2c2enR {
3547 # [ doc = r" Value of the field as raw bits" ]
3548 pub fn bits(&self) -> u8 {
3549 self.bits
3550 }
3551 }
3552 # [ doc = "Value of the field USBRST" ]
3553 pub struct UsbrstR {
3554 bits: u8,
3555 }
3556 impl UsbrstR {
3557 # [ doc = r" Value of the field as raw bits" ]
3558 pub fn bits(&self) -> u8 {
3559 self.bits
3560 }
3561 }
3562 # [ doc = "Value of the field CANEN" ]
3563 pub struct CanenR {
3564 bits: u8,
3565 }
3566 impl CanenR {
3567 # [ doc = r" Value of the field as raw bits" ]
3568 pub fn bits(&self) -> u8 {
3569 self.bits
3570 }
3571 }
3572 # [ doc = "Value of the field CRSEN" ]
3573 pub struct CrsenR {
3574 bits: u8,
3575 }
3576 impl CrsenR {
3577 # [ doc = r" Value of the field as raw bits" ]
3578 pub fn bits(&self) -> u8 {
3579 self.bits
3580 }
3581 }
3582 # [ doc = "Value of the field PWREN" ]
3583 pub struct PwrenR {
3584 bits: u8,
3585 }
3586 impl PwrenR {
3587 # [ doc = r" Value of the field as raw bits" ]
3588 pub fn bits(&self) -> u8 {
3589 self.bits
3590 }
3591 }
3592 # [ doc = "Value of the field DACEN" ]
3593 pub struct DacenR {
3594 bits: u8,
3595 }
3596 impl DacenR {
3597 # [ doc = r" Value of the field as raw bits" ]
3598 pub fn bits(&self) -> u8 {
3599 self.bits
3600 }
3601 }
3602 # [ doc = "Value of the field CECEN" ]
3603 pub struct CecenR {
3604 bits: u8,
3605 }
3606 impl CecenR {
3607 # [ doc = r" Value of the field as raw bits" ]
3608 pub fn bits(&self) -> u8 {
3609 self.bits
3610 }
3611 }
3612 # [ doc = r" Proxy" ]
3613 pub struct _Tim2enW<'a> {
3614 register: &'a mut W,
3615 }
3616 impl<'a> _Tim2enW<'a> {
3617 # [ doc = r" Writes raw `bits` to the field" ]
3618 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3619 const MASK: u8 = 1;
3620 const OFFSET: u8 = 0;
3621 self.register.bits &= !((MASK as u32) << OFFSET);
3622 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3623 self.register
3624 }
3625 }
3626 # [ doc = r" Proxy" ]
3627 pub struct _Tim3enW<'a> {
3628 register: &'a mut W,
3629 }
3630 impl<'a> _Tim3enW<'a> {
3631 # [ doc = r" Writes raw `bits` to the field" ]
3632 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3633 const MASK: u8 = 1;
3634 const OFFSET: u8 = 1;
3635 self.register.bits &= !((MASK as u32) << OFFSET);
3636 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3637 self.register
3638 }
3639 }
3640 # [ doc = r" Proxy" ]
3641 pub struct _Tim6enW<'a> {
3642 register: &'a mut W,
3643 }
3644 impl<'a> _Tim6enW<'a> {
3645 # [ doc = r" Writes raw `bits` to the field" ]
3646 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3647 const MASK: u8 = 1;
3648 const OFFSET: u8 = 4;
3649 self.register.bits &= !((MASK as u32) << OFFSET);
3650 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3651 self.register
3652 }
3653 }
3654 # [ doc = r" Proxy" ]
3655 pub struct _Tim7enW<'a> {
3656 register: &'a mut W,
3657 }
3658 impl<'a> _Tim7enW<'a> {
3659 # [ doc = r" Writes raw `bits` to the field" ]
3660 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3661 const MASK: u8 = 1;
3662 const OFFSET: u8 = 5;
3663 self.register.bits &= !((MASK as u32) << OFFSET);
3664 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3665 self.register
3666 }
3667 }
3668 # [ doc = r" Proxy" ]
3669 pub struct _Tim14enW<'a> {
3670 register: &'a mut W,
3671 }
3672 impl<'a> _Tim14enW<'a> {
3673 # [ doc = r" Writes raw `bits` to the field" ]
3674 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3675 const MASK: u8 = 1;
3676 const OFFSET: u8 = 8;
3677 self.register.bits &= !((MASK as u32) << OFFSET);
3678 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3679 self.register
3680 }
3681 }
3682 # [ doc = r" Proxy" ]
3683 pub struct _WwdgenW<'a> {
3684 register: &'a mut W,
3685 }
3686 impl<'a> _WwdgenW<'a> {
3687 # [ doc = r" Writes raw `bits` to the field" ]
3688 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3689 const MASK: u8 = 1;
3690 const OFFSET: u8 = 11;
3691 self.register.bits &= !((MASK as u32) << OFFSET);
3692 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3693 self.register
3694 }
3695 }
3696 # [ doc = r" Proxy" ]
3697 pub struct _Spi2enW<'a> {
3698 register: &'a mut W,
3699 }
3700 impl<'a> _Spi2enW<'a> {
3701 # [ doc = r" Writes raw `bits` to the field" ]
3702 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3703 const MASK: u8 = 1;
3704 const OFFSET: u8 = 14;
3705 self.register.bits &= !((MASK as u32) << OFFSET);
3706 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3707 self.register
3708 }
3709 }
3710 # [ doc = r" Proxy" ]
3711 pub struct _Usart2enW<'a> {
3712 register: &'a mut W,
3713 }
3714 impl<'a> _Usart2enW<'a> {
3715 # [ doc = r" Writes raw `bits` to the field" ]
3716 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3717 const MASK: u8 = 1;
3718 const OFFSET: u8 = 17;
3719 self.register.bits &= !((MASK as u32) << OFFSET);
3720 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3721 self.register
3722 }
3723 }
3724 # [ doc = r" Proxy" ]
3725 pub struct _Usart3enW<'a> {
3726 register: &'a mut W,
3727 }
3728 impl<'a> _Usart3enW<'a> {
3729 # [ doc = r" Writes raw `bits` to the field" ]
3730 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3731 const MASK: u8 = 1;
3732 const OFFSET: u8 = 18;
3733 self.register.bits &= !((MASK as u32) << OFFSET);
3734 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3735 self.register
3736 }
3737 }
3738 # [ doc = r" Proxy" ]
3739 pub struct _Usart4enW<'a> {
3740 register: &'a mut W,
3741 }
3742 impl<'a> _Usart4enW<'a> {
3743 # [ doc = r" Writes raw `bits` to the field" ]
3744 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3745 const MASK: u8 = 1;
3746 const OFFSET: u8 = 19;
3747 self.register.bits &= !((MASK as u32) << OFFSET);
3748 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3749 self.register
3750 }
3751 }
3752 # [ doc = r" Proxy" ]
3753 pub struct _I2c1enW<'a> {
3754 register: &'a mut W,
3755 }
3756 impl<'a> _I2c1enW<'a> {
3757 # [ doc = r" Writes raw `bits` to the field" ]
3758 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3759 const MASK: u8 = 1;
3760 const OFFSET: u8 = 21;
3761 self.register.bits &= !((MASK as u32) << OFFSET);
3762 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3763 self.register
3764 }
3765 }
3766 # [ doc = r" Proxy" ]
3767 pub struct _I2c2enW<'a> {
3768 register: &'a mut W,
3769 }
3770 impl<'a> _I2c2enW<'a> {
3771 # [ doc = r" Writes raw `bits` to the field" ]
3772 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3773 const MASK: u8 = 1;
3774 const OFFSET: u8 = 22;
3775 self.register.bits &= !((MASK as u32) << OFFSET);
3776 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3777 self.register
3778 }
3779 }
3780 # [ doc = r" Proxy" ]
3781 pub struct _UsbrstW<'a> {
3782 register: &'a mut W,
3783 }
3784 impl<'a> _UsbrstW<'a> {
3785 # [ doc = r" Writes raw `bits` to the field" ]
3786 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3787 const MASK: u8 = 1;
3788 const OFFSET: u8 = 23;
3789 self.register.bits &= !((MASK as u32) << OFFSET);
3790 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3791 self.register
3792 }
3793 }
3794 # [ doc = r" Proxy" ]
3795 pub struct _CanenW<'a> {
3796 register: &'a mut W,
3797 }
3798 impl<'a> _CanenW<'a> {
3799 # [ doc = r" Writes raw `bits` to the field" ]
3800 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3801 const MASK: u8 = 1;
3802 const OFFSET: u8 = 25;
3803 self.register.bits &= !((MASK as u32) << OFFSET);
3804 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3805 self.register
3806 }
3807 }
3808 # [ doc = r" Proxy" ]
3809 pub struct _CrsenW<'a> {
3810 register: &'a mut W,
3811 }
3812 impl<'a> _CrsenW<'a> {
3813 # [ doc = r" Writes raw `bits` to the field" ]
3814 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3815 const MASK: u8 = 1;
3816 const OFFSET: u8 = 27;
3817 self.register.bits &= !((MASK as u32) << OFFSET);
3818 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3819 self.register
3820 }
3821 }
3822 # [ doc = r" Proxy" ]
3823 pub struct _PwrenW<'a> {
3824 register: &'a mut W,
3825 }
3826 impl<'a> _PwrenW<'a> {
3827 # [ doc = r" Writes raw `bits` to the field" ]
3828 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3829 const MASK: u8 = 1;
3830 const OFFSET: u8 = 28;
3831 self.register.bits &= !((MASK as u32) << OFFSET);
3832 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3833 self.register
3834 }
3835 }
3836 # [ doc = r" Proxy" ]
3837 pub struct _DacenW<'a> {
3838 register: &'a mut W,
3839 }
3840 impl<'a> _DacenW<'a> {
3841 # [ doc = r" Writes raw `bits` to the field" ]
3842 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3843 const MASK: u8 = 1;
3844 const OFFSET: u8 = 29;
3845 self.register.bits &= !((MASK as u32) << OFFSET);
3846 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3847 self.register
3848 }
3849 }
3850 # [ doc = r" Proxy" ]
3851 pub struct _CecenW<'a> {
3852 register: &'a mut W,
3853 }
3854 impl<'a> _CecenW<'a> {
3855 # [ doc = r" Writes raw `bits` to the field" ]
3856 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3857 const MASK: u8 = 1;
3858 const OFFSET: u8 = 30;
3859 self.register.bits &= !((MASK as u32) << OFFSET);
3860 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3861 self.register
3862 }
3863 }
3864 impl R {
3865 # [ doc = r" Value of the register as raw bits" ]
3866 pub fn bits(&self) -> u32 {
3867 self.bits
3868 }
3869 fn _tim2en(&self) -> u8 {
3870 const MASK: u8 = 1;
3871 const OFFSET: u8 = 0;
3872 ((self.bits >> OFFSET) & MASK as u32) as u8
3873 }
3874 # [ doc = "Bit 0 - Timer 2 clock enable" ]
3875 pub fn tim2en(&self) -> Tim2enR {
3876 Tim2enR { bits: self._tim2en() }
3877 }
3878 fn _tim3en(&self) -> u8 {
3879 const MASK: u8 = 1;
3880 const OFFSET: u8 = 1;
3881 ((self.bits >> OFFSET) & MASK as u32) as u8
3882 }
3883 # [ doc = "Bit 1 - Timer 3 clock enable" ]
3884 pub fn tim3en(&self) -> Tim3enR {
3885 Tim3enR { bits: self._tim3en() }
3886 }
3887 fn _tim6en(&self) -> u8 {
3888 const MASK: u8 = 1;
3889 const OFFSET: u8 = 4;
3890 ((self.bits >> OFFSET) & MASK as u32) as u8
3891 }
3892 # [ doc = "Bit 4 - Timer 6 clock enable" ]
3893 pub fn tim6en(&self) -> Tim6enR {
3894 Tim6enR { bits: self._tim6en() }
3895 }
3896 fn _tim7en(&self) -> u8 {
3897 const MASK: u8 = 1;
3898 const OFFSET: u8 = 5;
3899 ((self.bits >> OFFSET) & MASK as u32) as u8
3900 }
3901 # [ doc = "Bit 5 - TIM7 timer clock enable" ]
3902 pub fn tim7en(&self) -> Tim7enR {
3903 Tim7enR { bits: self._tim7en() }
3904 }
3905 fn _tim14en(&self) -> u8 {
3906 const MASK: u8 = 1;
3907 const OFFSET: u8 = 8;
3908 ((self.bits >> OFFSET) & MASK as u32) as u8
3909 }
3910 # [ doc = "Bit 8 - Timer 14 clock enable" ]
3911 pub fn tim14en(&self) -> Tim14enR {
3912 Tim14enR { bits: self._tim14en() }
3913 }
3914 fn _wwdgen(&self) -> u8 {
3915 const MASK: u8 = 1;
3916 const OFFSET: u8 = 11;
3917 ((self.bits >> OFFSET) & MASK as u32) as u8
3918 }
3919 # [ doc = "Bit 11 - Window watchdog clock enable" ]
3920 pub fn wwdgen(&self) -> WwdgenR {
3921 WwdgenR { bits: self._wwdgen() }
3922 }
3923 fn _spi2en(&self) -> u8 {
3924 const MASK: u8 = 1;
3925 const OFFSET: u8 = 14;
3926 ((self.bits >> OFFSET) & MASK as u32) as u8
3927 }
3928 # [ doc = "Bit 14 - SPI 2 clock enable" ]
3929 pub fn spi2en(&self) -> Spi2enR {
3930 Spi2enR { bits: self._spi2en() }
3931 }
3932 fn _usart2en(&self) -> u8 {
3933 const MASK: u8 = 1;
3934 const OFFSET: u8 = 17;
3935 ((self.bits >> OFFSET) & MASK as u32) as u8
3936 }
3937 # [ doc = "Bit 17 - USART 2 clock enable" ]
3938 pub fn usart2en(&self) -> Usart2enR {
3939 Usart2enR { bits: self._usart2en() }
3940 }
3941 fn _usart3en(&self) -> u8 {
3942 const MASK: u8 = 1;
3943 const OFFSET: u8 = 18;
3944 ((self.bits >> OFFSET) & MASK as u32) as u8
3945 }
3946 # [ doc = "Bit 18 - USART3 clock enable" ]
3947 pub fn usart3en(&self) -> Usart3enR {
3948 Usart3enR { bits: self._usart3en() }
3949 }
3950 fn _usart4en(&self) -> u8 {
3951 const MASK: u8 = 1;
3952 const OFFSET: u8 = 19;
3953 ((self.bits >> OFFSET) & MASK as u32) as u8
3954 }
3955 # [ doc = "Bit 19 - USART4 clock enable" ]
3956 pub fn usart4en(&self) -> Usart4enR {
3957 Usart4enR { bits: self._usart4en() }
3958 }
3959 fn _i2c1en(&self) -> u8 {
3960 const MASK: u8 = 1;
3961 const OFFSET: u8 = 21;
3962 ((self.bits >> OFFSET) & MASK as u32) as u8
3963 }
3964 # [ doc = "Bit 21 - I2C 1 clock enable" ]
3965 pub fn i2c1en(&self) -> I2c1enR {
3966 I2c1enR { bits: self._i2c1en() }
3967 }
3968 fn _i2c2en(&self) -> u8 {
3969 const MASK: u8 = 1;
3970 const OFFSET: u8 = 22;
3971 ((self.bits >> OFFSET) & MASK as u32) as u8
3972 }
3973 # [ doc = "Bit 22 - I2C 2 clock enable" ]
3974 pub fn i2c2en(&self) -> I2c2enR {
3975 I2c2enR { bits: self._i2c2en() }
3976 }
3977 fn _usbrst(&self) -> u8 {
3978 const MASK: u8 = 1;
3979 const OFFSET: u8 = 23;
3980 ((self.bits >> OFFSET) & MASK as u32) as u8
3981 }
3982 # [ doc = "Bit 23 - USB interface clock enable" ]
3983 pub fn usbrst(&self) -> UsbrstR {
3984 UsbrstR { bits: self._usbrst() }
3985 }
3986 fn _canen(&self) -> u8 {
3987 const MASK: u8 = 1;
3988 const OFFSET: u8 = 25;
3989 ((self.bits >> OFFSET) & MASK as u32) as u8
3990 }
3991 # [ doc = "Bit 25 - CAN interface clock enable" ]
3992 pub fn canen(&self) -> CanenR {
3993 CanenR { bits: self._canen() }
3994 }
3995 fn _crsen(&self) -> u8 {
3996 const MASK: u8 = 1;
3997 const OFFSET: u8 = 27;
3998 ((self.bits >> OFFSET) & MASK as u32) as u8
3999 }
4000 # [ doc = "Bit 27 - Clock Recovery System interface clock enable" ]
4001 pub fn crsen(&self) -> CrsenR {
4002 CrsenR { bits: self._crsen() }
4003 }
4004 fn _pwren(&self) -> u8 {
4005 const MASK: u8 = 1;
4006 const OFFSET: u8 = 28;
4007 ((self.bits >> OFFSET) & MASK as u32) as u8
4008 }
4009 # [ doc = "Bit 28 - Power interface clock enable" ]
4010 pub fn pwren(&self) -> PwrenR {
4011 PwrenR { bits: self._pwren() }
4012 }
4013 fn _dacen(&self) -> u8 {
4014 const MASK: u8 = 1;
4015 const OFFSET: u8 = 29;
4016 ((self.bits >> OFFSET) & MASK as u32) as u8
4017 }
4018 # [ doc = "Bit 29 - DAC interface clock enable" ]
4019 pub fn dacen(&self) -> DacenR {
4020 DacenR { bits: self._dacen() }
4021 }
4022 fn _cecen(&self) -> u8 {
4023 const MASK: u8 = 1;
4024 const OFFSET: u8 = 30;
4025 ((self.bits >> OFFSET) & MASK as u32) as u8
4026 }
4027 # [ doc = "Bit 30 - HDMI CEC interface clock enable" ]
4028 pub fn cecen(&self) -> CecenR {
4029 CecenR { bits: self._cecen() }
4030 }
4031 }
4032 impl W {
4033 # [ doc = r" Reset value of the register" ]
4034 pub fn reset_value() -> W {
4035 W { bits: 0 }
4036 }
4037 # [ doc = r" Writes raw `bits` to the register" ]
4038 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
4039 self.bits = bits;
4040 self
4041 }
4042 # [ doc = "Bit 0 - Timer 2 clock enable" ]
4043 pub fn tim2en(&mut self) -> _Tim2enW {
4044 _Tim2enW { register: self }
4045 }
4046 # [ doc = "Bit 1 - Timer 3 clock enable" ]
4047 pub fn tim3en(&mut self) -> _Tim3enW {
4048 _Tim3enW { register: self }
4049 }
4050 # [ doc = "Bit 4 - Timer 6 clock enable" ]
4051 pub fn tim6en(&mut self) -> _Tim6enW {
4052 _Tim6enW { register: self }
4053 }
4054 # [ doc = "Bit 5 - TIM7 timer clock enable" ]
4055 pub fn tim7en(&mut self) -> _Tim7enW {
4056 _Tim7enW { register: self }
4057 }
4058 # [ doc = "Bit 8 - Timer 14 clock enable" ]
4059 pub fn tim14en(&mut self) -> _Tim14enW {
4060 _Tim14enW { register: self }
4061 }
4062 # [ doc = "Bit 11 - Window watchdog clock enable" ]
4063 pub fn wwdgen(&mut self) -> _WwdgenW {
4064 _WwdgenW { register: self }
4065 }
4066 # [ doc = "Bit 14 - SPI 2 clock enable" ]
4067 pub fn spi2en(&mut self) -> _Spi2enW {
4068 _Spi2enW { register: self }
4069 }
4070 # [ doc = "Bit 17 - USART 2 clock enable" ]
4071 pub fn usart2en(&mut self) -> _Usart2enW {
4072 _Usart2enW { register: self }
4073 }
4074 # [ doc = "Bit 18 - USART3 clock enable" ]
4075 pub fn usart3en(&mut self) -> _Usart3enW {
4076 _Usart3enW { register: self }
4077 }
4078 # [ doc = "Bit 19 - USART4 clock enable" ]
4079 pub fn usart4en(&mut self) -> _Usart4enW {
4080 _Usart4enW { register: self }
4081 }
4082 # [ doc = "Bit 21 - I2C 1 clock enable" ]
4083 pub fn i2c1en(&mut self) -> _I2c1enW {
4084 _I2c1enW { register: self }
4085 }
4086 # [ doc = "Bit 22 - I2C 2 clock enable" ]
4087 pub fn i2c2en(&mut self) -> _I2c2enW {
4088 _I2c2enW { register: self }
4089 }
4090 # [ doc = "Bit 23 - USB interface clock enable" ]
4091 pub fn usbrst(&mut self) -> _UsbrstW {
4092 _UsbrstW { register: self }
4093 }
4094 # [ doc = "Bit 25 - CAN interface clock enable" ]
4095 pub fn canen(&mut self) -> _CanenW {
4096 _CanenW { register: self }
4097 }
4098 # [ doc = "Bit 27 - Clock Recovery System interface clock enable" ]
4099 pub fn crsen(&mut self) -> _CrsenW {
4100 _CrsenW { register: self }
4101 }
4102 # [ doc = "Bit 28 - Power interface clock enable" ]
4103 pub fn pwren(&mut self) -> _PwrenW {
4104 _PwrenW { register: self }
4105 }
4106 # [ doc = "Bit 29 - DAC interface clock enable" ]
4107 pub fn dacen(&mut self) -> _DacenW {
4108 _DacenW { register: self }
4109 }
4110 # [ doc = "Bit 30 - HDMI CEC interface clock enable" ]
4111 pub fn cecen(&mut self) -> _CecenW {
4112 _CecenW { register: self }
4113 }
4114 }
4115}
4116
4117# [ doc = "Backup domain control register (RCC_BDCR)" ]
4118# [ repr ( C ) ]
4119pub struct Bdcr {
4120 register: ::volatile_register::RW<u32>,
4121}
4122
4123# [ doc = "Backup domain control register (RCC_BDCR)" ]
4124pub mod bdcr {
4125 # [ doc = r" Value read from the register" ]
4126 pub struct R {
4127 bits: u32,
4128 }
4129 # [ doc = r" Value to write to the register" ]
4130 pub struct W {
4131 bits: u32,
4132 }
4133 impl super::Bdcr {
4134 # [ doc = r" Modifies the contents of the register" ]
4135 pub fn modify<F>(&mut self, f: F)
4136 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
4137 {
4138 let bits = self.register.read();
4139 let r = R { bits: bits };
4140 let mut w = W { bits: bits };
4141 f(&r, &mut w);
4142 self.register.write(w.bits);
4143 }
4144 # [ doc = r" Reads the contents of the register" ]
4145 pub fn read(&self) -> R {
4146 R { bits: self.register.read() }
4147 }
4148 # [ doc = r" Writes to the register" ]
4149 pub fn write<F>(&mut self, f: F)
4150 where F: FnOnce(&mut W) -> &mut W
4151 {
4152 let mut w = W::reset_value();
4153 f(&mut w);
4154 self.register.write(w.bits);
4155 }
4156 }
4157 # [ doc = "Value of the field LSEON" ]
4158 pub struct LseonR {
4159 bits: u8,
4160 }
4161 impl LseonR {
4162 # [ doc = r" Value of the field as raw bits" ]
4163 pub fn bits(&self) -> u8 {
4164 self.bits
4165 }
4166 }
4167 # [ doc = "Value of the field LSERDY" ]
4168 pub struct LserdyR {
4169 bits: u8,
4170 }
4171 impl LserdyR {
4172 # [ doc = r" Value of the field as raw bits" ]
4173 pub fn bits(&self) -> u8 {
4174 self.bits
4175 }
4176 }
4177 # [ doc = "Value of the field LSEBYP" ]
4178 pub struct LsebypR {
4179 bits: u8,
4180 }
4181 impl LsebypR {
4182 # [ doc = r" Value of the field as raw bits" ]
4183 pub fn bits(&self) -> u8 {
4184 self.bits
4185 }
4186 }
4187 # [ doc = "Value of the field LSEDRV" ]
4188 pub struct LsedrvR {
4189 bits: u8,
4190 }
4191 impl LsedrvR {
4192 # [ doc = r" Value of the field as raw bits" ]
4193 pub fn bits(&self) -> u8 {
4194 self.bits
4195 }
4196 }
4197 # [ doc = "Value of the field RTCSEL" ]
4198 pub struct RtcselR {
4199 bits: u8,
4200 }
4201 impl RtcselR {
4202 # [ doc = r" Value of the field as raw bits" ]
4203 pub fn bits(&self) -> u8 {
4204 self.bits
4205 }
4206 }
4207 # [ doc = "Value of the field RTCEN" ]
4208 pub struct RtcenR {
4209 bits: u8,
4210 }
4211 impl RtcenR {
4212 # [ doc = r" Value of the field as raw bits" ]
4213 pub fn bits(&self) -> u8 {
4214 self.bits
4215 }
4216 }
4217 # [ doc = "Value of the field BDRST" ]
4218 pub struct BdrstR {
4219 bits: u8,
4220 }
4221 impl BdrstR {
4222 # [ doc = r" Value of the field as raw bits" ]
4223 pub fn bits(&self) -> u8 {
4224 self.bits
4225 }
4226 }
4227 # [ doc = r" Proxy" ]
4228 pub struct _LseonW<'a> {
4229 register: &'a mut W,
4230 }
4231 impl<'a> _LseonW<'a> {
4232 # [ doc = r" Writes raw `bits` to the field" ]
4233 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
4234 const MASK: u8 = 1;
4235 const OFFSET: u8 = 0;
4236 self.register.bits &= !((MASK as u32) << OFFSET);
4237 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4238 self.register
4239 }
4240 }
4241 # [ doc = r" Proxy" ]
4242 pub struct _LsebypW<'a> {
4243 register: &'a mut W,
4244 }
4245 impl<'a> _LsebypW<'a> {
4246 # [ doc = r" Writes raw `bits` to the field" ]
4247 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
4248 const MASK: u8 = 1;
4249 const OFFSET: u8 = 2;
4250 self.register.bits &= !((MASK as u32) << OFFSET);
4251 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4252 self.register
4253 }
4254 }
4255 # [ doc = r" Proxy" ]
4256 pub struct _LsedrvW<'a> {
4257 register: &'a mut W,
4258 }
4259 impl<'a> _LsedrvW<'a> {
4260 # [ doc = r" Writes raw `bits` to the field" ]
4261 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
4262 const MASK: u8 = 3;
4263 const OFFSET: u8 = 3;
4264 self.register.bits &= !((MASK as u32) << OFFSET);
4265 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4266 self.register
4267 }
4268 }
4269 # [ doc = r" Proxy" ]
4270 pub struct _RtcselW<'a> {
4271 register: &'a mut W,
4272 }
4273 impl<'a> _RtcselW<'a> {
4274 # [ doc = r" Writes raw `bits` to the field" ]
4275 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
4276 const MASK: u8 = 3;
4277 const OFFSET: u8 = 8;
4278 self.register.bits &= !((MASK as u32) << OFFSET);
4279 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4280 self.register
4281 }
4282 }
4283 # [ doc = r" Proxy" ]
4284 pub struct _RtcenW<'a> {
4285 register: &'a mut W,
4286 }
4287 impl<'a> _RtcenW<'a> {
4288 # [ doc = r" Writes raw `bits` to the field" ]
4289 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
4290 const MASK: u8 = 1;
4291 const OFFSET: u8 = 15;
4292 self.register.bits &= !((MASK as u32) << OFFSET);
4293 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4294 self.register
4295 }
4296 }
4297 # [ doc = r" Proxy" ]
4298 pub struct _BdrstW<'a> {
4299 register: &'a mut W,
4300 }
4301 impl<'a> _BdrstW<'a> {
4302 # [ doc = r" Writes raw `bits` to the field" ]
4303 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
4304 const MASK: u8 = 1;
4305 const OFFSET: u8 = 16;
4306 self.register.bits &= !((MASK as u32) << OFFSET);
4307 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4308 self.register
4309 }
4310 }
4311 impl R {
4312 # [ doc = r" Value of the register as raw bits" ]
4313 pub fn bits(&self) -> u32 {
4314 self.bits
4315 }
4316 fn _lseon(&self) -> u8 {
4317 const MASK: u8 = 1;
4318 const OFFSET: u8 = 0;
4319 ((self.bits >> OFFSET) & MASK as u32) as u8
4320 }
4321 # [ doc = "Bit 0 - External Low Speed oscillator enable" ]
4322 pub fn lseon(&self) -> LseonR {
4323 LseonR { bits: self._lseon() }
4324 }
4325 fn _lserdy(&self) -> u8 {
4326 const MASK: u8 = 1;
4327 const OFFSET: u8 = 1;
4328 ((self.bits >> OFFSET) & MASK as u32) as u8
4329 }
4330 # [ doc = "Bit 1 - External Low Speed oscillator ready" ]
4331 pub fn lserdy(&self) -> LserdyR {
4332 LserdyR { bits: self._lserdy() }
4333 }
4334 fn _lsebyp(&self) -> u8 {
4335 const MASK: u8 = 1;
4336 const OFFSET: u8 = 2;
4337 ((self.bits >> OFFSET) & MASK as u32) as u8
4338 }
4339 # [ doc = "Bit 2 - External Low Speed oscillator bypass" ]
4340 pub fn lsebyp(&self) -> LsebypR {
4341 LsebypR { bits: self._lsebyp() }
4342 }
4343 fn _lsedrv(&self) -> u8 {
4344 const MASK: u8 = 3;
4345 const OFFSET: u8 = 3;
4346 ((self.bits >> OFFSET) & MASK as u32) as u8
4347 }
4348 # [ doc = "Bits 3:4 - LSE oscillator drive capability" ]
4349 pub fn lsedrv(&self) -> LsedrvR {
4350 LsedrvR { bits: self._lsedrv() }
4351 }
4352 fn _rtcsel(&self) -> u8 {
4353 const MASK: u8 = 3;
4354 const OFFSET: u8 = 8;
4355 ((self.bits >> OFFSET) & MASK as u32) as u8
4356 }
4357 # [ doc = "Bits 8:9 - RTC clock source selection" ]
4358 pub fn rtcsel(&self) -> RtcselR {
4359 RtcselR { bits: self._rtcsel() }
4360 }
4361 fn _rtcen(&self) -> u8 {
4362 const MASK: u8 = 1;
4363 const OFFSET: u8 = 15;
4364 ((self.bits >> OFFSET) & MASK as u32) as u8
4365 }
4366 # [ doc = "Bit 15 - RTC clock enable" ]
4367 pub fn rtcen(&self) -> RtcenR {
4368 RtcenR { bits: self._rtcen() }
4369 }
4370 fn _bdrst(&self) -> u8 {
4371 const MASK: u8 = 1;
4372 const OFFSET: u8 = 16;
4373 ((self.bits >> OFFSET) & MASK as u32) as u8
4374 }
4375 # [ doc = "Bit 16 - Backup domain software reset" ]
4376 pub fn bdrst(&self) -> BdrstR {
4377 BdrstR { bits: self._bdrst() }
4378 }
4379 }
4380 impl W {
4381 # [ doc = r" Reset value of the register" ]
4382 pub fn reset_value() -> W {
4383 W { bits: 0 }
4384 }
4385 # [ doc = r" Writes raw `bits` to the register" ]
4386 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
4387 self.bits = bits;
4388 self
4389 }
4390 # [ doc = "Bit 0 - External Low Speed oscillator enable" ]
4391 pub fn lseon(&mut self) -> _LseonW {
4392 _LseonW { register: self }
4393 }
4394 # [ doc = "Bit 2 - External Low Speed oscillator bypass" ]
4395 pub fn lsebyp(&mut self) -> _LsebypW {
4396 _LsebypW { register: self }
4397 }
4398 # [ doc = "Bits 3:4 - LSE oscillator drive capability" ]
4399 pub fn lsedrv(&mut self) -> _LsedrvW {
4400 _LsedrvW { register: self }
4401 }
4402 # [ doc = "Bits 8:9 - RTC clock source selection" ]
4403 pub fn rtcsel(&mut self) -> _RtcselW {
4404 _RtcselW { register: self }
4405 }
4406 # [ doc = "Bit 15 - RTC clock enable" ]
4407 pub fn rtcen(&mut self) -> _RtcenW {
4408 _RtcenW { register: self }
4409 }
4410 # [ doc = "Bit 16 - Backup domain software reset" ]
4411 pub fn bdrst(&mut self) -> _BdrstW {
4412 _BdrstW { register: self }
4413 }
4414 }
4415}
4416
4417# [ doc = "Control/status register (RCC_CSR)" ]
4418# [ repr ( C ) ]
4419pub struct Csr {
4420 register: ::volatile_register::RW<u32>,
4421}
4422
4423# [ doc = "Control/status register (RCC_CSR)" ]
4424pub mod csr {
4425 # [ doc = r" Value read from the register" ]
4426 pub struct R {
4427 bits: u32,
4428 }
4429 # [ doc = r" Value to write to the register" ]
4430 pub struct W {
4431 bits: u32,
4432 }
4433 impl super::Csr {
4434 # [ doc = r" Modifies the contents of the register" ]
4435 pub fn modify<F>(&mut self, f: F)
4436 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
4437 {
4438 let bits = self.register.read();
4439 let r = R { bits: bits };
4440 let mut w = W { bits: bits };
4441 f(&r, &mut w);
4442 self.register.write(w.bits);
4443 }
4444 # [ doc = r" Reads the contents of the register" ]
4445 pub fn read(&self) -> R {
4446 R { bits: self.register.read() }
4447 }
4448 # [ doc = r" Writes to the register" ]
4449 pub fn write<F>(&mut self, f: F)
4450 where F: FnOnce(&mut W) -> &mut W
4451 {
4452 let mut w = W::reset_value();
4453 f(&mut w);
4454 self.register.write(w.bits);
4455 }
4456 }
4457 # [ doc = "Value of the field LSION" ]
4458 pub struct LsionR {
4459 bits: u8,
4460 }
4461 impl LsionR {
4462 # [ doc = r" Value of the field as raw bits" ]
4463 pub fn bits(&self) -> u8 {
4464 self.bits
4465 }
4466 }
4467 # [ doc = "Value of the field LSIRDY" ]
4468 pub struct LsirdyR {
4469 bits: u8,
4470 }
4471 impl LsirdyR {
4472 # [ doc = r" Value of the field as raw bits" ]
4473 pub fn bits(&self) -> u8 {
4474 self.bits
4475 }
4476 }
4477 # [ doc = "Value of the field RMVF" ]
4478 pub struct RmvfR {
4479 bits: u8,
4480 }
4481 impl RmvfR {
4482 # [ doc = r" Value of the field as raw bits" ]
4483 pub fn bits(&self) -> u8 {
4484 self.bits
4485 }
4486 }
4487 # [ doc = "Value of the field OBLRSTF" ]
4488 pub struct OblrstfR {
4489 bits: u8,
4490 }
4491 impl OblrstfR {
4492 # [ doc = r" Value of the field as raw bits" ]
4493 pub fn bits(&self) -> u8 {
4494 self.bits
4495 }
4496 }
4497 # [ doc = "Value of the field PINRSTF" ]
4498 pub struct PinrstfR {
4499 bits: u8,
4500 }
4501 impl PinrstfR {
4502 # [ doc = r" Value of the field as raw bits" ]
4503 pub fn bits(&self) -> u8 {
4504 self.bits
4505 }
4506 }
4507 # [ doc = "Value of the field PORRSTF" ]
4508 pub struct PorrstfR {
4509 bits: u8,
4510 }
4511 impl PorrstfR {
4512 # [ doc = r" Value of the field as raw bits" ]
4513 pub fn bits(&self) -> u8 {
4514 self.bits
4515 }
4516 }
4517 # [ doc = "Value of the field SFTRSTF" ]
4518 pub struct SftrstfR {
4519 bits: u8,
4520 }
4521 impl SftrstfR {
4522 # [ doc = r" Value of the field as raw bits" ]
4523 pub fn bits(&self) -> u8 {
4524 self.bits
4525 }
4526 }
4527 # [ doc = "Value of the field IWDGRSTF" ]
4528 pub struct IwdgrstfR {
4529 bits: u8,
4530 }
4531 impl IwdgrstfR {
4532 # [ doc = r" Value of the field as raw bits" ]
4533 pub fn bits(&self) -> u8 {
4534 self.bits
4535 }
4536 }
4537 # [ doc = "Value of the field WWDGRSTF" ]
4538 pub struct WwdgrstfR {
4539 bits: u8,
4540 }
4541 impl WwdgrstfR {
4542 # [ doc = r" Value of the field as raw bits" ]
4543 pub fn bits(&self) -> u8 {
4544 self.bits
4545 }
4546 }
4547 # [ doc = "Value of the field LPWRRSTF" ]
4548 pub struct LpwrrstfR {
4549 bits: u8,
4550 }
4551 impl LpwrrstfR {
4552 # [ doc = r" Value of the field as raw bits" ]
4553 pub fn bits(&self) -> u8 {
4554 self.bits
4555 }
4556 }
4557 # [ doc = r" Proxy" ]
4558 pub struct _LsionW<'a> {
4559 register: &'a mut W,
4560 }
4561 impl<'a> _LsionW<'a> {
4562 # [ doc = r" Writes raw `bits` to the field" ]
4563 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
4564 const MASK: u8 = 1;
4565 const OFFSET: u8 = 0;
4566 self.register.bits &= !((MASK as u32) << OFFSET);
4567 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4568 self.register
4569 }
4570 }
4571 # [ doc = r" Proxy" ]
4572 pub struct _RmvfW<'a> {
4573 register: &'a mut W,
4574 }
4575 impl<'a> _RmvfW<'a> {
4576 # [ doc = r" Writes raw `bits` to the field" ]
4577 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
4578 const MASK: u8 = 1;
4579 const OFFSET: u8 = 24;
4580 self.register.bits &= !((MASK as u32) << OFFSET);
4581 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4582 self.register
4583 }
4584 }
4585 # [ doc = r" Proxy" ]
4586 pub struct _OblrstfW<'a> {
4587 register: &'a mut W,
4588 }
4589 impl<'a> _OblrstfW<'a> {
4590 # [ doc = r" Writes raw `bits` to the field" ]
4591 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
4592 const MASK: u8 = 1;
4593 const OFFSET: u8 = 25;
4594 self.register.bits &= !((MASK as u32) << OFFSET);
4595 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4596 self.register
4597 }
4598 }
4599 # [ doc = r" Proxy" ]
4600 pub struct _PinrstfW<'a> {
4601 register: &'a mut W,
4602 }
4603 impl<'a> _PinrstfW<'a> {
4604 # [ doc = r" Writes raw `bits` to the field" ]
4605 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
4606 const MASK: u8 = 1;
4607 const OFFSET: u8 = 26;
4608 self.register.bits &= !((MASK as u32) << OFFSET);
4609 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4610 self.register
4611 }
4612 }
4613 # [ doc = r" Proxy" ]
4614 pub struct _PorrstfW<'a> {
4615 register: &'a mut W,
4616 }
4617 impl<'a> _PorrstfW<'a> {
4618 # [ doc = r" Writes raw `bits` to the field" ]
4619 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
4620 const MASK: u8 = 1;
4621 const OFFSET: u8 = 27;
4622 self.register.bits &= !((MASK as u32) << OFFSET);
4623 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4624 self.register
4625 }
4626 }
4627 # [ doc = r" Proxy" ]
4628 pub struct _SftrstfW<'a> {
4629 register: &'a mut W,
4630 }
4631 impl<'a> _SftrstfW<'a> {
4632 # [ doc = r" Writes raw `bits` to the field" ]
4633 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
4634 const MASK: u8 = 1;
4635 const OFFSET: u8 = 28;
4636 self.register.bits &= !((MASK as u32) << OFFSET);
4637 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4638 self.register
4639 }
4640 }
4641 # [ doc = r" Proxy" ]
4642 pub struct _IwdgrstfW<'a> {
4643 register: &'a mut W,
4644 }
4645 impl<'a> _IwdgrstfW<'a> {
4646 # [ doc = r" Writes raw `bits` to the field" ]
4647 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
4648 const MASK: u8 = 1;
4649 const OFFSET: u8 = 29;
4650 self.register.bits &= !((MASK as u32) << OFFSET);
4651 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4652 self.register
4653 }
4654 }
4655 # [ doc = r" Proxy" ]
4656 pub struct _WwdgrstfW<'a> {
4657 register: &'a mut W,
4658 }
4659 impl<'a> _WwdgrstfW<'a> {
4660 # [ doc = r" Writes raw `bits` to the field" ]
4661 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
4662 const MASK: u8 = 1;
4663 const OFFSET: u8 = 30;
4664 self.register.bits &= !((MASK as u32) << OFFSET);
4665 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4666 self.register
4667 }
4668 }
4669 # [ doc = r" Proxy" ]
4670 pub struct _LpwrrstfW<'a> {
4671 register: &'a mut W,
4672 }
4673 impl<'a> _LpwrrstfW<'a> {
4674 # [ doc = r" Writes raw `bits` to the field" ]
4675 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
4676 const MASK: u8 = 1;
4677 const OFFSET: u8 = 31;
4678 self.register.bits &= !((MASK as u32) << OFFSET);
4679 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4680 self.register
4681 }
4682 }
4683 impl R {
4684 # [ doc = r" Value of the register as raw bits" ]
4685 pub fn bits(&self) -> u32 {
4686 self.bits
4687 }
4688 fn _lsion(&self) -> u8 {
4689 const MASK: u8 = 1;
4690 const OFFSET: u8 = 0;
4691 ((self.bits >> OFFSET) & MASK as u32) as u8
4692 }
4693 # [ doc = "Bit 0 - Internal low speed oscillator enable" ]
4694 pub fn lsion(&self) -> LsionR {
4695 LsionR { bits: self._lsion() }
4696 }
4697 fn _lsirdy(&self) -> u8 {
4698 const MASK: u8 = 1;
4699 const OFFSET: u8 = 1;
4700 ((self.bits >> OFFSET) & MASK as u32) as u8
4701 }
4702 # [ doc = "Bit 1 - Internal low speed oscillator ready" ]
4703 pub fn lsirdy(&self) -> LsirdyR {
4704 LsirdyR { bits: self._lsirdy() }
4705 }
4706 fn _rmvf(&self) -> u8 {
4707 const MASK: u8 = 1;
4708 const OFFSET: u8 = 24;
4709 ((self.bits >> OFFSET) & MASK as u32) as u8
4710 }
4711 # [ doc = "Bit 24 - Remove reset flag" ]
4712 pub fn rmvf(&self) -> RmvfR {
4713 RmvfR { bits: self._rmvf() }
4714 }
4715 fn _oblrstf(&self) -> u8 {
4716 const MASK: u8 = 1;
4717 const OFFSET: u8 = 25;
4718 ((self.bits >> OFFSET) & MASK as u32) as u8
4719 }
4720 # [ doc = "Bit 25 - Option byte loader reset flag" ]
4721 pub fn oblrstf(&self) -> OblrstfR {
4722 OblrstfR { bits: self._oblrstf() }
4723 }
4724 fn _pinrstf(&self) -> u8 {
4725 const MASK: u8 = 1;
4726 const OFFSET: u8 = 26;
4727 ((self.bits >> OFFSET) & MASK as u32) as u8
4728 }
4729 # [ doc = "Bit 26 - PIN reset flag" ]
4730 pub fn pinrstf(&self) -> PinrstfR {
4731 PinrstfR { bits: self._pinrstf() }
4732 }
4733 fn _porrstf(&self) -> u8 {
4734 const MASK: u8 = 1;
4735 const OFFSET: u8 = 27;
4736 ((self.bits >> OFFSET) & MASK as u32) as u8
4737 }
4738 # [ doc = "Bit 27 - POR/PDR reset flag" ]
4739 pub fn porrstf(&self) -> PorrstfR {
4740 PorrstfR { bits: self._porrstf() }
4741 }
4742 fn _sftrstf(&self) -> u8 {
4743 const MASK: u8 = 1;
4744 const OFFSET: u8 = 28;
4745 ((self.bits >> OFFSET) & MASK as u32) as u8
4746 }
4747 # [ doc = "Bit 28 - Software reset flag" ]
4748 pub fn sftrstf(&self) -> SftrstfR {
4749 SftrstfR { bits: self._sftrstf() }
4750 }
4751 fn _iwdgrstf(&self) -> u8 {
4752 const MASK: u8 = 1;
4753 const OFFSET: u8 = 29;
4754 ((self.bits >> OFFSET) & MASK as u32) as u8
4755 }
4756 # [ doc = "Bit 29 - Independent watchdog reset flag" ]
4757 pub fn iwdgrstf(&self) -> IwdgrstfR {
4758 IwdgrstfR { bits: self._iwdgrstf() }
4759 }
4760 fn _wwdgrstf(&self) -> u8 {
4761 const MASK: u8 = 1;
4762 const OFFSET: u8 = 30;
4763 ((self.bits >> OFFSET) & MASK as u32) as u8
4764 }
4765 # [ doc = "Bit 30 - Window watchdog reset flag" ]
4766 pub fn wwdgrstf(&self) -> WwdgrstfR {
4767 WwdgrstfR { bits: self._wwdgrstf() }
4768 }
4769 fn _lpwrrstf(&self) -> u8 {
4770 const MASK: u8 = 1;
4771 const OFFSET: u8 = 31;
4772 ((self.bits >> OFFSET) & MASK as u32) as u8
4773 }
4774 # [ doc = "Bit 31 - Low-power reset flag" ]
4775 pub fn lpwrrstf(&self) -> LpwrrstfR {
4776 LpwrrstfR { bits: self._lpwrrstf() }
4777 }
4778 }
4779 impl W {
4780 # [ doc = r" Reset value of the register" ]
4781 pub fn reset_value() -> W {
4782 W { bits: 201326592 }
4783 }
4784 # [ doc = r" Writes raw `bits` to the register" ]
4785 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
4786 self.bits = bits;
4787 self
4788 }
4789 # [ doc = "Bit 0 - Internal low speed oscillator enable" ]
4790 pub fn lsion(&mut self) -> _LsionW {
4791 _LsionW { register: self }
4792 }
4793 # [ doc = "Bit 24 - Remove reset flag" ]
4794 pub fn rmvf(&mut self) -> _RmvfW {
4795 _RmvfW { register: self }
4796 }
4797 # [ doc = "Bit 25 - Option byte loader reset flag" ]
4798 pub fn oblrstf(&mut self) -> _OblrstfW {
4799 _OblrstfW { register: self }
4800 }
4801 # [ doc = "Bit 26 - PIN reset flag" ]
4802 pub fn pinrstf(&mut self) -> _PinrstfW {
4803 _PinrstfW { register: self }
4804 }
4805 # [ doc = "Bit 27 - POR/PDR reset flag" ]
4806 pub fn porrstf(&mut self) -> _PorrstfW {
4807 _PorrstfW { register: self }
4808 }
4809 # [ doc = "Bit 28 - Software reset flag" ]
4810 pub fn sftrstf(&mut self) -> _SftrstfW {
4811 _SftrstfW { register: self }
4812 }
4813 # [ doc = "Bit 29 - Independent watchdog reset flag" ]
4814 pub fn iwdgrstf(&mut self) -> _IwdgrstfW {
4815 _IwdgrstfW { register: self }
4816 }
4817 # [ doc = "Bit 30 - Window watchdog reset flag" ]
4818 pub fn wwdgrstf(&mut self) -> _WwdgrstfW {
4819 _WwdgrstfW { register: self }
4820 }
4821 # [ doc = "Bit 31 - Low-power reset flag" ]
4822 pub fn lpwrrstf(&mut self) -> _LpwrrstfW {
4823 _LpwrrstfW { register: self }
4824 }
4825 }
4826}
4827
4828# [ doc = "AHB peripheral reset register" ]
4829# [ repr ( C ) ]
4830pub struct Ahbrstr {
4831 register: ::volatile_register::RW<u32>,
4832}
4833
4834# [ doc = "AHB peripheral reset register" ]
4835pub mod ahbrstr {
4836 # [ doc = r" Value read from the register" ]
4837 pub struct R {
4838 bits: u32,
4839 }
4840 # [ doc = r" Value to write to the register" ]
4841 pub struct W {
4842 bits: u32,
4843 }
4844 impl super::Ahbrstr {
4845 # [ doc = r" Modifies the contents of the register" ]
4846 pub fn modify<F>(&mut self, f: F)
4847 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
4848 {
4849 let bits = self.register.read();
4850 let r = R { bits: bits };
4851 let mut w = W { bits: bits };
4852 f(&r, &mut w);
4853 self.register.write(w.bits);
4854 }
4855 # [ doc = r" Reads the contents of the register" ]
4856 pub fn read(&self) -> R {
4857 R { bits: self.register.read() }
4858 }
4859 # [ doc = r" Writes to the register" ]
4860 pub fn write<F>(&mut self, f: F)
4861 where F: FnOnce(&mut W) -> &mut W
4862 {
4863 let mut w = W::reset_value();
4864 f(&mut w);
4865 self.register.write(w.bits);
4866 }
4867 }
4868 # [ doc = "Value of the field IOPARST" ]
4869 pub struct IoparstR {
4870 bits: u8,
4871 }
4872 impl IoparstR {
4873 # [ doc = r" Value of the field as raw bits" ]
4874 pub fn bits(&self) -> u8 {
4875 self.bits
4876 }
4877 }
4878 # [ doc = "Value of the field IOPBRST" ]
4879 pub struct IopbrstR {
4880 bits: u8,
4881 }
4882 impl IopbrstR {
4883 # [ doc = r" Value of the field as raw bits" ]
4884 pub fn bits(&self) -> u8 {
4885 self.bits
4886 }
4887 }
4888 # [ doc = "Value of the field IOPCRST" ]
4889 pub struct IopcrstR {
4890 bits: u8,
4891 }
4892 impl IopcrstR {
4893 # [ doc = r" Value of the field as raw bits" ]
4894 pub fn bits(&self) -> u8 {
4895 self.bits
4896 }
4897 }
4898 # [ doc = "Value of the field IOPDRST" ]
4899 pub struct IopdrstR {
4900 bits: u8,
4901 }
4902 impl IopdrstR {
4903 # [ doc = r" Value of the field as raw bits" ]
4904 pub fn bits(&self) -> u8 {
4905 self.bits
4906 }
4907 }
4908 # [ doc = "Value of the field IOPFRST" ]
4909 pub struct IopfrstR {
4910 bits: u8,
4911 }
4912 impl IopfrstR {
4913 # [ doc = r" Value of the field as raw bits" ]
4914 pub fn bits(&self) -> u8 {
4915 self.bits
4916 }
4917 }
4918 # [ doc = "Value of the field TSCRST" ]
4919 pub struct TscrstR {
4920 bits: u8,
4921 }
4922 impl TscrstR {
4923 # [ doc = r" Value of the field as raw bits" ]
4924 pub fn bits(&self) -> u8 {
4925 self.bits
4926 }
4927 }
4928 # [ doc = r" Proxy" ]
4929 pub struct _IoparstW<'a> {
4930 register: &'a mut W,
4931 }
4932 impl<'a> _IoparstW<'a> {
4933 # [ doc = r" Writes raw `bits` to the field" ]
4934 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
4935 const MASK: u8 = 1;
4936 const OFFSET: u8 = 17;
4937 self.register.bits &= !((MASK as u32) << OFFSET);
4938 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4939 self.register
4940 }
4941 }
4942 # [ doc = r" Proxy" ]
4943 pub struct _IopbrstW<'a> {
4944 register: &'a mut W,
4945 }
4946 impl<'a> _IopbrstW<'a> {
4947 # [ doc = r" Writes raw `bits` to the field" ]
4948 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
4949 const MASK: u8 = 1;
4950 const OFFSET: u8 = 18;
4951 self.register.bits &= !((MASK as u32) << OFFSET);
4952 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4953 self.register
4954 }
4955 }
4956 # [ doc = r" Proxy" ]
4957 pub struct _IopcrstW<'a> {
4958 register: &'a mut W,
4959 }
4960 impl<'a> _IopcrstW<'a> {
4961 # [ doc = r" Writes raw `bits` to the field" ]
4962 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
4963 const MASK: u8 = 1;
4964 const OFFSET: u8 = 19;
4965 self.register.bits &= !((MASK as u32) << OFFSET);
4966 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4967 self.register
4968 }
4969 }
4970 # [ doc = r" Proxy" ]
4971 pub struct _IopdrstW<'a> {
4972 register: &'a mut W,
4973 }
4974 impl<'a> _IopdrstW<'a> {
4975 # [ doc = r" Writes raw `bits` to the field" ]
4976 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
4977 const MASK: u8 = 1;
4978 const OFFSET: u8 = 20;
4979 self.register.bits &= !((MASK as u32) << OFFSET);
4980 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4981 self.register
4982 }
4983 }
4984 # [ doc = r" Proxy" ]
4985 pub struct _IopfrstW<'a> {
4986 register: &'a mut W,
4987 }
4988 impl<'a> _IopfrstW<'a> {
4989 # [ doc = r" Writes raw `bits` to the field" ]
4990 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
4991 const MASK: u8 = 1;
4992 const OFFSET: u8 = 22;
4993 self.register.bits &= !((MASK as u32) << OFFSET);
4994 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4995 self.register
4996 }
4997 }
4998 # [ doc = r" Proxy" ]
4999 pub struct _TscrstW<'a> {
5000 register: &'a mut W,
5001 }
5002 impl<'a> _TscrstW<'a> {
5003 # [ doc = r" Writes raw `bits` to the field" ]
5004 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
5005 const MASK: u8 = 1;
5006 const OFFSET: u8 = 24;
5007 self.register.bits &= !((MASK as u32) << OFFSET);
5008 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
5009 self.register
5010 }
5011 }
5012 impl R {
5013 # [ doc = r" Value of the register as raw bits" ]
5014 pub fn bits(&self) -> u32 {
5015 self.bits
5016 }
5017 fn _ioparst(&self) -> u8 {
5018 const MASK: u8 = 1;
5019 const OFFSET: u8 = 17;
5020 ((self.bits >> OFFSET) & MASK as u32) as u8
5021 }
5022 # [ doc = "Bit 17 - I/O port A reset" ]
5023 pub fn ioparst(&self) -> IoparstR {
5024 IoparstR { bits: self._ioparst() }
5025 }
5026 fn _iopbrst(&self) -> u8 {
5027 const MASK: u8 = 1;
5028 const OFFSET: u8 = 18;
5029 ((self.bits >> OFFSET) & MASK as u32) as u8
5030 }
5031 # [ doc = "Bit 18 - I/O port B reset" ]
5032 pub fn iopbrst(&self) -> IopbrstR {
5033 IopbrstR { bits: self._iopbrst() }
5034 }
5035 fn _iopcrst(&self) -> u8 {
5036 const MASK: u8 = 1;
5037 const OFFSET: u8 = 19;
5038 ((self.bits >> OFFSET) & MASK as u32) as u8
5039 }
5040 # [ doc = "Bit 19 - I/O port C reset" ]
5041 pub fn iopcrst(&self) -> IopcrstR {
5042 IopcrstR { bits: self._iopcrst() }
5043 }
5044 fn _iopdrst(&self) -> u8 {
5045 const MASK: u8 = 1;
5046 const OFFSET: u8 = 20;
5047 ((self.bits >> OFFSET) & MASK as u32) as u8
5048 }
5049 # [ doc = "Bit 20 - I/O port D reset" ]
5050 pub fn iopdrst(&self) -> IopdrstR {
5051 IopdrstR { bits: self._iopdrst() }
5052 }
5053 fn _iopfrst(&self) -> u8 {
5054 const MASK: u8 = 1;
5055 const OFFSET: u8 = 22;
5056 ((self.bits >> OFFSET) & MASK as u32) as u8
5057 }
5058 # [ doc = "Bit 22 - I/O port F reset" ]
5059 pub fn iopfrst(&self) -> IopfrstR {
5060 IopfrstR { bits: self._iopfrst() }
5061 }
5062 fn _tscrst(&self) -> u8 {
5063 const MASK: u8 = 1;
5064 const OFFSET: u8 = 24;
5065 ((self.bits >> OFFSET) & MASK as u32) as u8
5066 }
5067 # [ doc = "Bit 24 - Touch sensing controller reset" ]
5068 pub fn tscrst(&self) -> TscrstR {
5069 TscrstR { bits: self._tscrst() }
5070 }
5071 }
5072 impl W {
5073 # [ doc = r" Reset value of the register" ]
5074 pub fn reset_value() -> W {
5075 W { bits: 0 }
5076 }
5077 # [ doc = r" Writes raw `bits` to the register" ]
5078 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
5079 self.bits = bits;
5080 self
5081 }
5082 # [ doc = "Bit 17 - I/O port A reset" ]
5083 pub fn ioparst(&mut self) -> _IoparstW {
5084 _IoparstW { register: self }
5085 }
5086 # [ doc = "Bit 18 - I/O port B reset" ]
5087 pub fn iopbrst(&mut self) -> _IopbrstW {
5088 _IopbrstW { register: self }
5089 }
5090 # [ doc = "Bit 19 - I/O port C reset" ]
5091 pub fn iopcrst(&mut self) -> _IopcrstW {
5092 _IopcrstW { register: self }
5093 }
5094 # [ doc = "Bit 20 - I/O port D reset" ]
5095 pub fn iopdrst(&mut self) -> _IopdrstW {
5096 _IopdrstW { register: self }
5097 }
5098 # [ doc = "Bit 22 - I/O port F reset" ]
5099 pub fn iopfrst(&mut self) -> _IopfrstW {
5100 _IopfrstW { register: self }
5101 }
5102 # [ doc = "Bit 24 - Touch sensing controller reset" ]
5103 pub fn tscrst(&mut self) -> _TscrstW {
5104 _TscrstW { register: self }
5105 }
5106 }
5107}
5108
5109# [ doc = "Clock configuration register 2" ]
5110# [ repr ( C ) ]
5111pub struct Cfgr2 {
5112 register: ::volatile_register::RW<u32>,
5113}
5114
5115# [ doc = "Clock configuration register 2" ]
5116pub mod cfgr2 {
5117 # [ doc = r" Value read from the register" ]
5118 pub struct R {
5119 bits: u32,
5120 }
5121 # [ doc = r" Value to write to the register" ]
5122 pub struct W {
5123 bits: u32,
5124 }
5125 impl super::Cfgr2 {
5126 # [ doc = r" Modifies the contents of the register" ]
5127 pub fn modify<F>(&mut self, f: F)
5128 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
5129 {
5130 let bits = self.register.read();
5131 let r = R { bits: bits };
5132 let mut w = W { bits: bits };
5133 f(&r, &mut w);
5134 self.register.write(w.bits);
5135 }
5136 # [ doc = r" Reads the contents of the register" ]
5137 pub fn read(&self) -> R {
5138 R { bits: self.register.read() }
5139 }
5140 # [ doc = r" Writes to the register" ]
5141 pub fn write<F>(&mut self, f: F)
5142 where F: FnOnce(&mut W) -> &mut W
5143 {
5144 let mut w = W::reset_value();
5145 f(&mut w);
5146 self.register.write(w.bits);
5147 }
5148 }
5149 # [ doc = "Value of the field PREDIV" ]
5150 pub struct PredivR {
5151 bits: u8,
5152 }
5153 impl PredivR {
5154 # [ doc = r" Value of the field as raw bits" ]
5155 pub fn bits(&self) -> u8 {
5156 self.bits
5157 }
5158 }
5159 # [ doc = r" Proxy" ]
5160 pub struct _PredivW<'a> {
5161 register: &'a mut W,
5162 }
5163 impl<'a> _PredivW<'a> {
5164 # [ doc = r" Writes raw `bits` to the field" ]
5165 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
5166 const MASK: u8 = 15;
5167 const OFFSET: u8 = 0;
5168 self.register.bits &= !((MASK as u32) << OFFSET);
5169 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
5170 self.register
5171 }
5172 }
5173 impl R {
5174 # [ doc = r" Value of the register as raw bits" ]
5175 pub fn bits(&self) -> u32 {
5176 self.bits
5177 }
5178 fn _prediv(&self) -> u8 {
5179 const MASK: u8 = 15;
5180 const OFFSET: u8 = 0;
5181 ((self.bits >> OFFSET) & MASK as u32) as u8
5182 }
5183 # [ doc = "Bits 0:3 - PREDIV division factor" ]
5184 pub fn prediv(&self) -> PredivR {
5185 PredivR { bits: self._prediv() }
5186 }
5187 }
5188 impl W {
5189 # [ doc = r" Reset value of the register" ]
5190 pub fn reset_value() -> W {
5191 W { bits: 0 }
5192 }
5193 # [ doc = r" Writes raw `bits` to the register" ]
5194 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
5195 self.bits = bits;
5196 self
5197 }
5198 # [ doc = "Bits 0:3 - PREDIV division factor" ]
5199 pub fn prediv(&mut self) -> _PredivW {
5200 _PredivW { register: self }
5201 }
5202 }
5203}
5204
5205# [ doc = "Clock configuration register 3" ]
5206# [ repr ( C ) ]
5207pub struct Cfgr3 {
5208 register: ::volatile_register::RW<u32>,
5209}
5210
5211# [ doc = "Clock configuration register 3" ]
5212pub mod cfgr3 {
5213 # [ doc = r" Value read from the register" ]
5214 pub struct R {
5215 bits: u32,
5216 }
5217 # [ doc = r" Value to write to the register" ]
5218 pub struct W {
5219 bits: u32,
5220 }
5221 impl super::Cfgr3 {
5222 # [ doc = r" Modifies the contents of the register" ]
5223 pub fn modify<F>(&mut self, f: F)
5224 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
5225 {
5226 let bits = self.register.read();
5227 let r = R { bits: bits };
5228 let mut w = W { bits: bits };
5229 f(&r, &mut w);
5230 self.register.write(w.bits);
5231 }
5232 # [ doc = r" Reads the contents of the register" ]
5233 pub fn read(&self) -> R {
5234 R { bits: self.register.read() }
5235 }
5236 # [ doc = r" Writes to the register" ]
5237 pub fn write<F>(&mut self, f: F)
5238 where F: FnOnce(&mut W) -> &mut W
5239 {
5240 let mut w = W::reset_value();
5241 f(&mut w);
5242 self.register.write(w.bits);
5243 }
5244 }
5245 # [ doc = "Value of the field USART1SW" ]
5246 pub struct Usart1swR {
5247 bits: u8,
5248 }
5249 impl Usart1swR {
5250 # [ doc = r" Value of the field as raw bits" ]
5251 pub fn bits(&self) -> u8 {
5252 self.bits
5253 }
5254 }
5255 # [ doc = "Value of the field I2C1SW" ]
5256 pub struct I2c1swR {
5257 bits: u8,
5258 }
5259 impl I2c1swR {
5260 # [ doc = r" Value of the field as raw bits" ]
5261 pub fn bits(&self) -> u8 {
5262 self.bits
5263 }
5264 }
5265 # [ doc = "Value of the field CECSW" ]
5266 pub struct CecswR {
5267 bits: u8,
5268 }
5269 impl CecswR {
5270 # [ doc = r" Value of the field as raw bits" ]
5271 pub fn bits(&self) -> u8 {
5272 self.bits
5273 }
5274 }
5275 # [ doc = "Value of the field USBSW" ]
5276 pub struct UsbswR {
5277 bits: u8,
5278 }
5279 impl UsbswR {
5280 # [ doc = r" Value of the field as raw bits" ]
5281 pub fn bits(&self) -> u8 {
5282 self.bits
5283 }
5284 }
5285 # [ doc = "Value of the field ADCSW" ]
5286 pub struct AdcswR {
5287 bits: u8,
5288 }
5289 impl AdcswR {
5290 # [ doc = r" Value of the field as raw bits" ]
5291 pub fn bits(&self) -> u8 {
5292 self.bits
5293 }
5294 }
5295 # [ doc = "Value of the field USART2SW" ]
5296 pub struct Usart2swR {
5297 bits: u8,
5298 }
5299 impl Usart2swR {
5300 # [ doc = r" Value of the field as raw bits" ]
5301 pub fn bits(&self) -> u8 {
5302 self.bits
5303 }
5304 }
5305 # [ doc = r" Proxy" ]
5306 pub struct _Usart1swW<'a> {
5307 register: &'a mut W,
5308 }
5309 impl<'a> _Usart1swW<'a> {
5310 # [ doc = r" Writes raw `bits` to the field" ]
5311 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
5312 const MASK: u8 = 3;
5313 const OFFSET: u8 = 0;
5314 self.register.bits &= !((MASK as u32) << OFFSET);
5315 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
5316 self.register
5317 }
5318 }
5319 # [ doc = r" Proxy" ]
5320 pub struct _I2c1swW<'a> {
5321 register: &'a mut W,
5322 }
5323 impl<'a> _I2c1swW<'a> {
5324 # [ doc = r" Writes raw `bits` to the field" ]
5325 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
5326 const MASK: u8 = 1;
5327 const OFFSET: u8 = 4;
5328 self.register.bits &= !((MASK as u32) << OFFSET);
5329 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
5330 self.register
5331 }
5332 }
5333 # [ doc = r" Proxy" ]
5334 pub struct _CecswW<'a> {
5335 register: &'a mut W,
5336 }
5337 impl<'a> _CecswW<'a> {
5338 # [ doc = r" Writes raw `bits` to the field" ]
5339 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
5340 const MASK: u8 = 1;
5341 const OFFSET: u8 = 6;
5342 self.register.bits &= !((MASK as u32) << OFFSET);
5343 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
5344 self.register
5345 }
5346 }
5347 # [ doc = r" Proxy" ]
5348 pub struct _UsbswW<'a> {
5349 register: &'a mut W,
5350 }
5351 impl<'a> _UsbswW<'a> {
5352 # [ doc = r" Writes raw `bits` to the field" ]
5353 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
5354 const MASK: u8 = 1;
5355 const OFFSET: u8 = 7;
5356 self.register.bits &= !((MASK as u32) << OFFSET);
5357 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
5358 self.register
5359 }
5360 }
5361 # [ doc = r" Proxy" ]
5362 pub struct _AdcswW<'a> {
5363 register: &'a mut W,
5364 }
5365 impl<'a> _AdcswW<'a> {
5366 # [ doc = r" Writes raw `bits` to the field" ]
5367 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
5368 const MASK: u8 = 1;
5369 const OFFSET: u8 = 8;
5370 self.register.bits &= !((MASK as u32) << OFFSET);
5371 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
5372 self.register
5373 }
5374 }
5375 # [ doc = r" Proxy" ]
5376 pub struct _Usart2swW<'a> {
5377 register: &'a mut W,
5378 }
5379 impl<'a> _Usart2swW<'a> {
5380 # [ doc = r" Writes raw `bits` to the field" ]
5381 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
5382 const MASK: u8 = 3;
5383 const OFFSET: u8 = 16;
5384 self.register.bits &= !((MASK as u32) << OFFSET);
5385 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
5386 self.register
5387 }
5388 }
5389 impl R {
5390 # [ doc = r" Value of the register as raw bits" ]
5391 pub fn bits(&self) -> u32 {
5392 self.bits
5393 }
5394 fn _usart1sw(&self) -> u8 {
5395 const MASK: u8 = 3;
5396 const OFFSET: u8 = 0;
5397 ((self.bits >> OFFSET) & MASK as u32) as u8
5398 }
5399 # [ doc = "Bits 0:1 - USART1 clock source selection" ]
5400 pub fn usart1sw(&self) -> Usart1swR {
5401 Usart1swR { bits: self._usart1sw() }
5402 }
5403 fn _i2c1sw(&self) -> u8 {
5404 const MASK: u8 = 1;
5405 const OFFSET: u8 = 4;
5406 ((self.bits >> OFFSET) & MASK as u32) as u8
5407 }
5408 # [ doc = "Bit 4 - I2C1 clock source selection" ]
5409 pub fn i2c1sw(&self) -> I2c1swR {
5410 I2c1swR { bits: self._i2c1sw() }
5411 }
5412 fn _cecsw(&self) -> u8 {
5413 const MASK: u8 = 1;
5414 const OFFSET: u8 = 6;
5415 ((self.bits >> OFFSET) & MASK as u32) as u8
5416 }
5417 # [ doc = "Bit 6 - HDMI CEC clock source selection" ]
5418 pub fn cecsw(&self) -> CecswR {
5419 CecswR { bits: self._cecsw() }
5420 }
5421 fn _usbsw(&self) -> u8 {
5422 const MASK: u8 = 1;
5423 const OFFSET: u8 = 7;
5424 ((self.bits >> OFFSET) & MASK as u32) as u8
5425 }
5426 # [ doc = "Bit 7 - USB clock source selection" ]
5427 pub fn usbsw(&self) -> UsbswR {
5428 UsbswR { bits: self._usbsw() }
5429 }
5430 fn _adcsw(&self) -> u8 {
5431 const MASK: u8 = 1;
5432 const OFFSET: u8 = 8;
5433 ((self.bits >> OFFSET) & MASK as u32) as u8
5434 }
5435 # [ doc = "Bit 8 - ADC clock source selection" ]
5436 pub fn adcsw(&self) -> AdcswR {
5437 AdcswR { bits: self._adcsw() }
5438 }
5439 fn _usart2sw(&self) -> u8 {
5440 const MASK: u8 = 3;
5441 const OFFSET: u8 = 16;
5442 ((self.bits >> OFFSET) & MASK as u32) as u8
5443 }
5444 # [ doc = "Bits 16:17 - USART2 clock source selection" ]
5445 pub fn usart2sw(&self) -> Usart2swR {
5446 Usart2swR { bits: self._usart2sw() }
5447 }
5448 }
5449 impl W {
5450 # [ doc = r" Reset value of the register" ]
5451 pub fn reset_value() -> W {
5452 W { bits: 0 }
5453 }
5454 # [ doc = r" Writes raw `bits` to the register" ]
5455 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
5456 self.bits = bits;
5457 self
5458 }
5459 # [ doc = "Bits 0:1 - USART1 clock source selection" ]
5460 pub fn usart1sw(&mut self) -> _Usart1swW {
5461 _Usart1swW { register: self }
5462 }
5463 # [ doc = "Bit 4 - I2C1 clock source selection" ]
5464 pub fn i2c1sw(&mut self) -> _I2c1swW {
5465 _I2c1swW { register: self }
5466 }
5467 # [ doc = "Bit 6 - HDMI CEC clock source selection" ]
5468 pub fn cecsw(&mut self) -> _CecswW {
5469 _CecswW { register: self }
5470 }
5471 # [ doc = "Bit 7 - USB clock source selection" ]
5472 pub fn usbsw(&mut self) -> _UsbswW {
5473 _UsbswW { register: self }
5474 }
5475 # [ doc = "Bit 8 - ADC clock source selection" ]
5476 pub fn adcsw(&mut self) -> _AdcswW {
5477 _AdcswW { register: self }
5478 }
5479 # [ doc = "Bits 16:17 - USART2 clock source selection" ]
5480 pub fn usart2sw(&mut self) -> _Usart2swW {
5481 _Usart2swW { register: self }
5482 }
5483 }
5484}
5485
5486# [ doc = "Clock control register 2" ]
5487# [ repr ( C ) ]
5488pub struct Cr2 {
5489 register: ::volatile_register::RW<u32>,
5490}
5491
5492# [ doc = "Clock control register 2" ]
5493pub mod cr2 {
5494 # [ doc = r" Value read from the register" ]
5495 pub struct R {
5496 bits: u32,
5497 }
5498 # [ doc = r" Value to write to the register" ]
5499 pub struct W {
5500 bits: u32,
5501 }
5502 impl super::Cr2 {
5503 # [ doc = r" Modifies the contents of the register" ]
5504 pub fn modify<F>(&mut self, f: F)
5505 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
5506 {
5507 let bits = self.register.read();
5508 let r = R { bits: bits };
5509 let mut w = W { bits: bits };
5510 f(&r, &mut w);
5511 self.register.write(w.bits);
5512 }
5513 # [ doc = r" Reads the contents of the register" ]
5514 pub fn read(&self) -> R {
5515 R { bits: self.register.read() }
5516 }
5517 # [ doc = r" Writes to the register" ]
5518 pub fn write<F>(&mut self, f: F)
5519 where F: FnOnce(&mut W) -> &mut W
5520 {
5521 let mut w = W::reset_value();
5522 f(&mut w);
5523 self.register.write(w.bits);
5524 }
5525 }
5526 # [ doc = "Value of the field HSI14ON" ]
5527 pub struct Hsi14onR {
5528 bits: u8,
5529 }
5530 impl Hsi14onR {
5531 # [ doc = r" Value of the field as raw bits" ]
5532 pub fn bits(&self) -> u8 {
5533 self.bits
5534 }
5535 }
5536 # [ doc = "Value of the field HSI14RDY" ]
5537 pub struct Hsi14rdyR {
5538 bits: u8,
5539 }
5540 impl Hsi14rdyR {
5541 # [ doc = r" Value of the field as raw bits" ]
5542 pub fn bits(&self) -> u8 {
5543 self.bits
5544 }
5545 }
5546 # [ doc = "Value of the field HSI14DIS" ]
5547 pub struct Hsi14disR {
5548 bits: u8,
5549 }
5550 impl Hsi14disR {
5551 # [ doc = r" Value of the field as raw bits" ]
5552 pub fn bits(&self) -> u8 {
5553 self.bits
5554 }
5555 }
5556 # [ doc = "Value of the field HSI14TRIM" ]
5557 pub struct Hsi14trimR {
5558 bits: u8,
5559 }
5560 impl Hsi14trimR {
5561 # [ doc = r" Value of the field as raw bits" ]
5562 pub fn bits(&self) -> u8 {
5563 self.bits
5564 }
5565 }
5566 # [ doc = "Value of the field HSI14CAL" ]
5567 pub struct Hsi14calR {
5568 bits: u8,
5569 }
5570 impl Hsi14calR {
5571 # [ doc = r" Value of the field as raw bits" ]
5572 pub fn bits(&self) -> u8 {
5573 self.bits
5574 }
5575 }
5576 # [ doc = "Value of the field HSI48ON" ]
5577 pub struct Hsi48onR {
5578 bits: u8,
5579 }
5580 impl Hsi48onR {
5581 # [ doc = r" Value of the field as raw bits" ]
5582 pub fn bits(&self) -> u8 {
5583 self.bits
5584 }
5585 }
5586 # [ doc = "Value of the field HSI48RDY" ]
5587 pub struct Hsi48rdyR {
5588 bits: u8,
5589 }
5590 impl Hsi48rdyR {
5591 # [ doc = r" Value of the field as raw bits" ]
5592 pub fn bits(&self) -> u8 {
5593 self.bits
5594 }
5595 }
5596 # [ doc = "Value of the field HSI48CAL" ]
5597 pub struct Hsi48calR {
5598 bits: u8,
5599 }
5600 impl Hsi48calR {
5601 # [ doc = r" Value of the field as raw bits" ]
5602 pub fn bits(&self) -> u8 {
5603 self.bits
5604 }
5605 }
5606 # [ doc = r" Proxy" ]
5607 pub struct _Hsi14onW<'a> {
5608 register: &'a mut W,
5609 }
5610 impl<'a> _Hsi14onW<'a> {
5611 # [ doc = r" Writes raw `bits` to the field" ]
5612 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
5613 const MASK: u8 = 1;
5614 const OFFSET: u8 = 0;
5615 self.register.bits &= !((MASK as u32) << OFFSET);
5616 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
5617 self.register
5618 }
5619 }
5620 # [ doc = r" Proxy" ]
5621 pub struct _Hsi14disW<'a> {
5622 register: &'a mut W,
5623 }
5624 impl<'a> _Hsi14disW<'a> {
5625 # [ doc = r" Writes raw `bits` to the field" ]
5626 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
5627 const MASK: u8 = 1;
5628 const OFFSET: u8 = 2;
5629 self.register.bits &= !((MASK as u32) << OFFSET);
5630 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
5631 self.register
5632 }
5633 }
5634 # [ doc = r" Proxy" ]
5635 pub struct _Hsi14trimW<'a> {
5636 register: &'a mut W,
5637 }
5638 impl<'a> _Hsi14trimW<'a> {
5639 # [ doc = r" Writes raw `bits` to the field" ]
5640 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
5641 const MASK: u8 = 31;
5642 const OFFSET: u8 = 3;
5643 self.register.bits &= !((MASK as u32) << OFFSET);
5644 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
5645 self.register
5646 }
5647 }
5648 # [ doc = r" Proxy" ]
5649 pub struct _Hsi48onW<'a> {
5650 register: &'a mut W,
5651 }
5652 impl<'a> _Hsi48onW<'a> {
5653 # [ doc = r" Writes raw `bits` to the field" ]
5654 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
5655 const MASK: u8 = 1;
5656 const OFFSET: u8 = 16;
5657 self.register.bits &= !((MASK as u32) << OFFSET);
5658 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
5659 self.register
5660 }
5661 }
5662 impl R {
5663 # [ doc = r" Value of the register as raw bits" ]
5664 pub fn bits(&self) -> u32 {
5665 self.bits
5666 }
5667 fn _hsi14on(&self) -> u8 {
5668 const MASK: u8 = 1;
5669 const OFFSET: u8 = 0;
5670 ((self.bits >> OFFSET) & MASK as u32) as u8
5671 }
5672 # [ doc = "Bit 0 - HSI14 clock enable" ]
5673 pub fn hsi14on(&self) -> Hsi14onR {
5674 Hsi14onR { bits: self._hsi14on() }
5675 }
5676 fn _hsi14rdy(&self) -> u8 {
5677 const MASK: u8 = 1;
5678 const OFFSET: u8 = 1;
5679 ((self.bits >> OFFSET) & MASK as u32) as u8
5680 }
5681 # [ doc = "Bit 1 - HR14 clock ready flag" ]
5682 pub fn hsi14rdy(&self) -> Hsi14rdyR {
5683 Hsi14rdyR { bits: self._hsi14rdy() }
5684 }
5685 fn _hsi14dis(&self) -> u8 {
5686 const MASK: u8 = 1;
5687 const OFFSET: u8 = 2;
5688 ((self.bits >> OFFSET) & MASK as u32) as u8
5689 }
5690 # [ doc = "Bit 2 - HSI14 clock request from ADC disable" ]
5691 pub fn hsi14dis(&self) -> Hsi14disR {
5692 Hsi14disR { bits: self._hsi14dis() }
5693 }
5694 fn _hsi14trim(&self) -> u8 {
5695 const MASK: u8 = 31;
5696 const OFFSET: u8 = 3;
5697 ((self.bits >> OFFSET) & MASK as u32) as u8
5698 }
5699 # [ doc = "Bits 3:7 - HSI14 clock trimming" ]
5700 pub fn hsi14trim(&self) -> Hsi14trimR {
5701 Hsi14trimR { bits: self._hsi14trim() }
5702 }
5703 fn _hsi14cal(&self) -> u8 {
5704 const MASK: u8 = 255;
5705 const OFFSET: u8 = 8;
5706 ((self.bits >> OFFSET) & MASK as u32) as u8
5707 }
5708 # [ doc = "Bits 8:15 - HSI14 clock calibration" ]
5709 pub fn hsi14cal(&self) -> Hsi14calR {
5710 Hsi14calR { bits: self._hsi14cal() }
5711 }
5712 fn _hsi48on(&self) -> u8 {
5713 const MASK: u8 = 1;
5714 const OFFSET: u8 = 16;
5715 ((self.bits >> OFFSET) & MASK as u32) as u8
5716 }
5717 # [ doc = "Bit 16 - HSI48 clock enable" ]
5718 pub fn hsi48on(&self) -> Hsi48onR {
5719 Hsi48onR { bits: self._hsi48on() }
5720 }
5721 fn _hsi48rdy(&self) -> u8 {
5722 const MASK: u8 = 1;
5723 const OFFSET: u8 = 17;
5724 ((self.bits >> OFFSET) & MASK as u32) as u8
5725 }
5726 # [ doc = "Bit 17 - HSI48 clock ready flag" ]
5727 pub fn hsi48rdy(&self) -> Hsi48rdyR {
5728 Hsi48rdyR { bits: self._hsi48rdy() }
5729 }
5730 fn _hsi48cal(&self) -> u8 {
5731 const MASK: u8 = 1;
5732 const OFFSET: u8 = 24;
5733 ((self.bits >> OFFSET) & MASK as u32) as u8
5734 }
5735 # [ doc = "Bit 24 - HSI48 factory clock calibration" ]
5736 pub fn hsi48cal(&self) -> Hsi48calR {
5737 Hsi48calR { bits: self._hsi48cal() }
5738 }
5739 }
5740 impl W {
5741 # [ doc = r" Reset value of the register" ]
5742 pub fn reset_value() -> W {
5743 W { bits: 128 }
5744 }
5745 # [ doc = r" Writes raw `bits` to the register" ]
5746 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
5747 self.bits = bits;
5748 self
5749 }
5750 # [ doc = "Bit 0 - HSI14 clock enable" ]
5751 pub fn hsi14on(&mut self) -> _Hsi14onW {
5752 _Hsi14onW { register: self }
5753 }
5754 # [ doc = "Bit 2 - HSI14 clock request from ADC disable" ]
5755 pub fn hsi14dis(&mut self) -> _Hsi14disW {
5756 _Hsi14disW { register: self }
5757 }
5758 # [ doc = "Bits 3:7 - HSI14 clock trimming" ]
5759 pub fn hsi14trim(&mut self) -> _Hsi14trimW {
5760 _Hsi14trimW { register: self }
5761 }
5762 # [ doc = "Bit 16 - HSI48 clock enable" ]
5763 pub fn hsi48on(&mut self) -> _Hsi48onW {
5764 _Hsi48onW { register: self }
5765 }
5766 }
5767}