1# ! [ doc = "Inter-integrated circuit" ]
2# [ doc = r" Register block" ]
3# [ repr ( C ) ]
4pub struct I2c {
5 # [ doc = "0x00 - Control register 1" ]
6 pub cr1: Cr1,
7 # [ doc = "0x04 - Control register 2" ]
8 pub cr2: Cr2,
9 # [ doc = "0x08 - Own address register 1" ]
10 pub oar1: Oar1,
11 # [ doc = "0x0c - Own address register 2" ]
12 pub oar2: Oar2,
13 # [ doc = "0x10 - Timing register" ]
14 pub timingr: Timingr,
15 # [ doc = "0x14 - Status register 1" ]
16 pub timeoutr: Timeoutr,
17 # [ doc = "0x18 - Interrupt and Status register" ]
18 pub isr: Isr,
19 # [ doc = "0x1c - Interrupt clear register" ]
20 pub icr: Icr,
21 # [ doc = "0x20 - PEC register" ]
22 pub pecr: Pecr,
23 # [ doc = "0x24 - Receive data register" ]
24 pub rxdr: Rxdr,
25 # [ doc = "0x28 - Transmit data register" ]
26 pub txdr: Txdr,
27}
28
29# [ doc = "Control register 1" ]
30# [ repr ( C ) ]
31pub struct Cr1 {
32 register: ::volatile_register::RW<u32>,
33}
34
35# [ doc = "Control register 1" ]
36pub mod cr1 {
37 # [ doc = r" Value read from the register" ]
38 pub struct R {
39 bits: u32,
40 }
41 # [ doc = r" Value to write to the register" ]
42 pub struct W {
43 bits: u32,
44 }
45 impl super::Cr1 {
46 # [ doc = r" Modifies the contents of the register" ]
47 pub fn modify<F>(&mut self, f: F)
48 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
49 {
50 let bits = self.register.read();
51 let r = R { bits: bits };
52 let mut w = W { bits: bits };
53 f(&r, &mut w);
54 self.register.write(w.bits);
55 }
56 # [ doc = r" Reads the contents of the register" ]
57 pub fn read(&self) -> R {
58 R { bits: self.register.read() }
59 }
60 # [ doc = r" Writes to the register" ]
61 pub fn write<F>(&mut self, f: F)
62 where F: FnOnce(&mut W) -> &mut W
63 {
64 let mut w = W::reset_value();
65 f(&mut w);
66 self.register.write(w.bits);
67 }
68 }
69 # [ doc = "Value of the field PE" ]
70 pub struct PeR {
71 bits: u8,
72 }
73 impl PeR {
74 # [ doc = r" Value of the field as raw bits" ]
75 pub fn bits(&self) -> u8 {
76 self.bits
77 }
78 }
79 # [ doc = "Value of the field TXIE" ]
80 pub struct TxieR {
81 bits: u8,
82 }
83 impl TxieR {
84 # [ doc = r" Value of the field as raw bits" ]
85 pub fn bits(&self) -> u8 {
86 self.bits
87 }
88 }
89 # [ doc = "Value of the field RXIE" ]
90 pub struct RxieR {
91 bits: u8,
92 }
93 impl RxieR {
94 # [ doc = r" Value of the field as raw bits" ]
95 pub fn bits(&self) -> u8 {
96 self.bits
97 }
98 }
99 # [ doc = "Value of the field ADDRIE" ]
100 pub struct AddrieR {
101 bits: u8,
102 }
103 impl AddrieR {
104 # [ doc = r" Value of the field as raw bits" ]
105 pub fn bits(&self) -> u8 {
106 self.bits
107 }
108 }
109 # [ doc = "Value of the field NACKIE" ]
110 pub struct NackieR {
111 bits: u8,
112 }
113 impl NackieR {
114 # [ doc = r" Value of the field as raw bits" ]
115 pub fn bits(&self) -> u8 {
116 self.bits
117 }
118 }
119 # [ doc = "Value of the field STOPIE" ]
120 pub struct StopieR {
121 bits: u8,
122 }
123 impl StopieR {
124 # [ doc = r" Value of the field as raw bits" ]
125 pub fn bits(&self) -> u8 {
126 self.bits
127 }
128 }
129 # [ doc = "Value of the field TCIE" ]
130 pub struct TcieR {
131 bits: u8,
132 }
133 impl TcieR {
134 # [ doc = r" Value of the field as raw bits" ]
135 pub fn bits(&self) -> u8 {
136 self.bits
137 }
138 }
139 # [ doc = "Value of the field ERRIE" ]
140 pub struct ErrieR {
141 bits: u8,
142 }
143 impl ErrieR {
144 # [ doc = r" Value of the field as raw bits" ]
145 pub fn bits(&self) -> u8 {
146 self.bits
147 }
148 }
149 # [ doc = "Value of the field DNF" ]
150 pub struct DnfR {
151 bits: u8,
152 }
153 impl DnfR {
154 # [ doc = r" Value of the field as raw bits" ]
155 pub fn bits(&self) -> u8 {
156 self.bits
157 }
158 }
159 # [ doc = "Value of the field ANFOFF" ]
160 pub struct AnfoffR {
161 bits: u8,
162 }
163 impl AnfoffR {
164 # [ doc = r" Value of the field as raw bits" ]
165 pub fn bits(&self) -> u8 {
166 self.bits
167 }
168 }
169 # [ doc = "Value of the field TXDMAEN" ]
170 pub struct TxdmaenR {
171 bits: u8,
172 }
173 impl TxdmaenR {
174 # [ doc = r" Value of the field as raw bits" ]
175 pub fn bits(&self) -> u8 {
176 self.bits
177 }
178 }
179 # [ doc = "Value of the field RXDMAEN" ]
180 pub struct RxdmaenR {
181 bits: u8,
182 }
183 impl RxdmaenR {
184 # [ doc = r" Value of the field as raw bits" ]
185 pub fn bits(&self) -> u8 {
186 self.bits
187 }
188 }
189 # [ doc = "Value of the field SBC" ]
190 pub struct SbcR {
191 bits: u8,
192 }
193 impl SbcR {
194 # [ doc = r" Value of the field as raw bits" ]
195 pub fn bits(&self) -> u8 {
196 self.bits
197 }
198 }
199 # [ doc = "Value of the field NOSTRETCH" ]
200 pub struct NostretchR {
201 bits: u8,
202 }
203 impl NostretchR {
204 # [ doc = r" Value of the field as raw bits" ]
205 pub fn bits(&self) -> u8 {
206 self.bits
207 }
208 }
209 # [ doc = "Value of the field WUPEN" ]
210 pub struct WupenR {
211 bits: u8,
212 }
213 impl WupenR {
214 # [ doc = r" Value of the field as raw bits" ]
215 pub fn bits(&self) -> u8 {
216 self.bits
217 }
218 }
219 # [ doc = "Value of the field GCEN" ]
220 pub struct GcenR {
221 bits: u8,
222 }
223 impl GcenR {
224 # [ doc = r" Value of the field as raw bits" ]
225 pub fn bits(&self) -> u8 {
226 self.bits
227 }
228 }
229 # [ doc = "Value of the field SMBHEN" ]
230 pub struct SmbhenR {
231 bits: u8,
232 }
233 impl SmbhenR {
234 # [ doc = r" Value of the field as raw bits" ]
235 pub fn bits(&self) -> u8 {
236 self.bits
237 }
238 }
239 # [ doc = "Value of the field SMBDEN" ]
240 pub struct SmbdenR {
241 bits: u8,
242 }
243 impl SmbdenR {
244 # [ doc = r" Value of the field as raw bits" ]
245 pub fn bits(&self) -> u8 {
246 self.bits
247 }
248 }
249 # [ doc = "Value of the field ALERTEN" ]
250 pub struct AlertenR {
251 bits: u8,
252 }
253 impl AlertenR {
254 # [ doc = r" Value of the field as raw bits" ]
255 pub fn bits(&self) -> u8 {
256 self.bits
257 }
258 }
259 # [ doc = "Value of the field PECEN" ]
260 pub struct PecenR {
261 bits: u8,
262 }
263 impl PecenR {
264 # [ doc = r" Value of the field as raw bits" ]
265 pub fn bits(&self) -> u8 {
266 self.bits
267 }
268 }
269 # [ doc = r" Proxy" ]
270 pub struct _PeW<'a> {
271 register: &'a mut W,
272 }
273 impl<'a> _PeW<'a> {
274 # [ doc = r" Writes raw `bits` to the field" ]
275 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
276 const MASK: u8 = 1;
277 const OFFSET: u8 = 0;
278 self.register.bits &= !((MASK as u32) << OFFSET);
279 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
280 self.register
281 }
282 }
283 # [ doc = r" Proxy" ]
284 pub struct _TxieW<'a> {
285 register: &'a mut W,
286 }
287 impl<'a> _TxieW<'a> {
288 # [ doc = r" Writes raw `bits` to the field" ]
289 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
290 const MASK: u8 = 1;
291 const OFFSET: u8 = 1;
292 self.register.bits &= !((MASK as u32) << OFFSET);
293 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
294 self.register
295 }
296 }
297 # [ doc = r" Proxy" ]
298 pub struct _RxieW<'a> {
299 register: &'a mut W,
300 }
301 impl<'a> _RxieW<'a> {
302 # [ doc = r" Writes raw `bits` to the field" ]
303 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
304 const MASK: u8 = 1;
305 const OFFSET: u8 = 2;
306 self.register.bits &= !((MASK as u32) << OFFSET);
307 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
308 self.register
309 }
310 }
311 # [ doc = r" Proxy" ]
312 pub struct _AddrieW<'a> {
313 register: &'a mut W,
314 }
315 impl<'a> _AddrieW<'a> {
316 # [ doc = r" Writes raw `bits` to the field" ]
317 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
318 const MASK: u8 = 1;
319 const OFFSET: u8 = 3;
320 self.register.bits &= !((MASK as u32) << OFFSET);
321 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
322 self.register
323 }
324 }
325 # [ doc = r" Proxy" ]
326 pub struct _NackieW<'a> {
327 register: &'a mut W,
328 }
329 impl<'a> _NackieW<'a> {
330 # [ doc = r" Writes raw `bits` to the field" ]
331 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
332 const MASK: u8 = 1;
333 const OFFSET: u8 = 4;
334 self.register.bits &= !((MASK as u32) << OFFSET);
335 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
336 self.register
337 }
338 }
339 # [ doc = r" Proxy" ]
340 pub struct _StopieW<'a> {
341 register: &'a mut W,
342 }
343 impl<'a> _StopieW<'a> {
344 # [ doc = r" Writes raw `bits` to the field" ]
345 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
346 const MASK: u8 = 1;
347 const OFFSET: u8 = 5;
348 self.register.bits &= !((MASK as u32) << OFFSET);
349 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
350 self.register
351 }
352 }
353 # [ doc = r" Proxy" ]
354 pub struct _TcieW<'a> {
355 register: &'a mut W,
356 }
357 impl<'a> _TcieW<'a> {
358 # [ doc = r" Writes raw `bits` to the field" ]
359 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
360 const MASK: u8 = 1;
361 const OFFSET: u8 = 6;
362 self.register.bits &= !((MASK as u32) << OFFSET);
363 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
364 self.register
365 }
366 }
367 # [ doc = r" Proxy" ]
368 pub struct _ErrieW<'a> {
369 register: &'a mut W,
370 }
371 impl<'a> _ErrieW<'a> {
372 # [ doc = r" Writes raw `bits` to the field" ]
373 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
374 const MASK: u8 = 1;
375 const OFFSET: u8 = 7;
376 self.register.bits &= !((MASK as u32) << OFFSET);
377 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
378 self.register
379 }
380 }
381 # [ doc = r" Proxy" ]
382 pub struct _DnfW<'a> {
383 register: &'a mut W,
384 }
385 impl<'a> _DnfW<'a> {
386 # [ doc = r" Writes raw `bits` to the field" ]
387 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
388 const MASK: u8 = 15;
389 const OFFSET: u8 = 8;
390 self.register.bits &= !((MASK as u32) << OFFSET);
391 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
392 self.register
393 }
394 }
395 # [ doc = r" Proxy" ]
396 pub struct _AnfoffW<'a> {
397 register: &'a mut W,
398 }
399 impl<'a> _AnfoffW<'a> {
400 # [ doc = r" Writes raw `bits` to the field" ]
401 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
402 const MASK: u8 = 1;
403 const OFFSET: u8 = 12;
404 self.register.bits &= !((MASK as u32) << OFFSET);
405 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
406 self.register
407 }
408 }
409 # [ doc = r" Proxy" ]
410 pub struct _SwrstW<'a> {
411 register: &'a mut W,
412 }
413 impl<'a> _SwrstW<'a> {
414 # [ doc = r" Writes raw `bits` to the field" ]
415 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
416 const MASK: u8 = 1;
417 const OFFSET: u8 = 13;
418 self.register.bits &= !((MASK as u32) << OFFSET);
419 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
420 self.register
421 }
422 }
423 # [ doc = r" Proxy" ]
424 pub struct _TxdmaenW<'a> {
425 register: &'a mut W,
426 }
427 impl<'a> _TxdmaenW<'a> {
428 # [ doc = r" Writes raw `bits` to the field" ]
429 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
430 const MASK: u8 = 1;
431 const OFFSET: u8 = 14;
432 self.register.bits &= !((MASK as u32) << OFFSET);
433 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
434 self.register
435 }
436 }
437 # [ doc = r" Proxy" ]
438 pub struct _RxdmaenW<'a> {
439 register: &'a mut W,
440 }
441 impl<'a> _RxdmaenW<'a> {
442 # [ doc = r" Writes raw `bits` to the field" ]
443 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
444 const MASK: u8 = 1;
445 const OFFSET: u8 = 15;
446 self.register.bits &= !((MASK as u32) << OFFSET);
447 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
448 self.register
449 }
450 }
451 # [ doc = r" Proxy" ]
452 pub struct _SbcW<'a> {
453 register: &'a mut W,
454 }
455 impl<'a> _SbcW<'a> {
456 # [ doc = r" Writes raw `bits` to the field" ]
457 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
458 const MASK: u8 = 1;
459 const OFFSET: u8 = 16;
460 self.register.bits &= !((MASK as u32) << OFFSET);
461 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
462 self.register
463 }
464 }
465 # [ doc = r" Proxy" ]
466 pub struct _NostretchW<'a> {
467 register: &'a mut W,
468 }
469 impl<'a> _NostretchW<'a> {
470 # [ doc = r" Writes raw `bits` to the field" ]
471 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
472 const MASK: u8 = 1;
473 const OFFSET: u8 = 17;
474 self.register.bits &= !((MASK as u32) << OFFSET);
475 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
476 self.register
477 }
478 }
479 # [ doc = r" Proxy" ]
480 pub struct _WupenW<'a> {
481 register: &'a mut W,
482 }
483 impl<'a> _WupenW<'a> {
484 # [ doc = r" Writes raw `bits` to the field" ]
485 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
486 const MASK: u8 = 1;
487 const OFFSET: u8 = 18;
488 self.register.bits &= !((MASK as u32) << OFFSET);
489 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
490 self.register
491 }
492 }
493 # [ doc = r" Proxy" ]
494 pub struct _GcenW<'a> {
495 register: &'a mut W,
496 }
497 impl<'a> _GcenW<'a> {
498 # [ doc = r" Writes raw `bits` to the field" ]
499 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
500 const MASK: u8 = 1;
501 const OFFSET: u8 = 19;
502 self.register.bits &= !((MASK as u32) << OFFSET);
503 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
504 self.register
505 }
506 }
507 # [ doc = r" Proxy" ]
508 pub struct _SmbhenW<'a> {
509 register: &'a mut W,
510 }
511 impl<'a> _SmbhenW<'a> {
512 # [ doc = r" Writes raw `bits` to the field" ]
513 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
514 const MASK: u8 = 1;
515 const OFFSET: u8 = 20;
516 self.register.bits &= !((MASK as u32) << OFFSET);
517 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
518 self.register
519 }
520 }
521 # [ doc = r" Proxy" ]
522 pub struct _SmbdenW<'a> {
523 register: &'a mut W,
524 }
525 impl<'a> _SmbdenW<'a> {
526 # [ doc = r" Writes raw `bits` to the field" ]
527 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
528 const MASK: u8 = 1;
529 const OFFSET: u8 = 21;
530 self.register.bits &= !((MASK as u32) << OFFSET);
531 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
532 self.register
533 }
534 }
535 # [ doc = r" Proxy" ]
536 pub struct _AlertenW<'a> {
537 register: &'a mut W,
538 }
539 impl<'a> _AlertenW<'a> {
540 # [ doc = r" Writes raw `bits` to the field" ]
541 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
542 const MASK: u8 = 1;
543 const OFFSET: u8 = 22;
544 self.register.bits &= !((MASK as u32) << OFFSET);
545 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
546 self.register
547 }
548 }
549 # [ doc = r" Proxy" ]
550 pub struct _PecenW<'a> {
551 register: &'a mut W,
552 }
553 impl<'a> _PecenW<'a> {
554 # [ doc = r" Writes raw `bits` to the field" ]
555 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
556 const MASK: u8 = 1;
557 const OFFSET: u8 = 23;
558 self.register.bits &= !((MASK as u32) << OFFSET);
559 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
560 self.register
561 }
562 }
563 impl R {
564 # [ doc = r" Value of the register as raw bits" ]
565 pub fn bits(&self) -> u32 {
566 self.bits
567 }
568 fn _pe(&self) -> u8 {
569 const MASK: u8 = 1;
570 const OFFSET: u8 = 0;
571 ((self.bits >> OFFSET) & MASK as u32) as u8
572 }
573 # [ doc = "Bit 0 - Peripheral enable" ]
574 pub fn pe(&self) -> PeR {
575 PeR { bits: self._pe() }
576 }
577 fn _txie(&self) -> u8 {
578 const MASK: u8 = 1;
579 const OFFSET: u8 = 1;
580 ((self.bits >> OFFSET) & MASK as u32) as u8
581 }
582 # [ doc = "Bit 1 - TX Interrupt enable" ]
583 pub fn txie(&self) -> TxieR {
584 TxieR { bits: self._txie() }
585 }
586 fn _rxie(&self) -> u8 {
587 const MASK: u8 = 1;
588 const OFFSET: u8 = 2;
589 ((self.bits >> OFFSET) & MASK as u32) as u8
590 }
591 # [ doc = "Bit 2 - RX Interrupt enable" ]
592 pub fn rxie(&self) -> RxieR {
593 RxieR { bits: self._rxie() }
594 }
595 fn _addrie(&self) -> u8 {
596 const MASK: u8 = 1;
597 const OFFSET: u8 = 3;
598 ((self.bits >> OFFSET) & MASK as u32) as u8
599 }
600 # [ doc = "Bit 3 - Address match interrupt enable (slave only)" ]
601 pub fn addrie(&self) -> AddrieR {
602 AddrieR { bits: self._addrie() }
603 }
604 fn _nackie(&self) -> u8 {
605 const MASK: u8 = 1;
606 const OFFSET: u8 = 4;
607 ((self.bits >> OFFSET) & MASK as u32) as u8
608 }
609 # [ doc = "Bit 4 - Not acknowledge received interrupt enable" ]
610 pub fn nackie(&self) -> NackieR {
611 NackieR { bits: self._nackie() }
612 }
613 fn _stopie(&self) -> u8 {
614 const MASK: u8 = 1;
615 const OFFSET: u8 = 5;
616 ((self.bits >> OFFSET) & MASK as u32) as u8
617 }
618 # [ doc = "Bit 5 - STOP detection Interrupt enable" ]
619 pub fn stopie(&self) -> StopieR {
620 StopieR { bits: self._stopie() }
621 }
622 fn _tcie(&self) -> u8 {
623 const MASK: u8 = 1;
624 const OFFSET: u8 = 6;
625 ((self.bits >> OFFSET) & MASK as u32) as u8
626 }
627 # [ doc = "Bit 6 - Transfer Complete interrupt enable" ]
628 pub fn tcie(&self) -> TcieR {
629 TcieR { bits: self._tcie() }
630 }
631 fn _errie(&self) -> u8 {
632 const MASK: u8 = 1;
633 const OFFSET: u8 = 7;
634 ((self.bits >> OFFSET) & MASK as u32) as u8
635 }
636 # [ doc = "Bit 7 - Error interrupts enable" ]
637 pub fn errie(&self) -> ErrieR {
638 ErrieR { bits: self._errie() }
639 }
640 fn _dnf(&self) -> u8 {
641 const MASK: u8 = 15;
642 const OFFSET: u8 = 8;
643 ((self.bits >> OFFSET) & MASK as u32) as u8
644 }
645 # [ doc = "Bits 8:11 - Digital noise filter" ]
646 pub fn dnf(&self) -> DnfR {
647 DnfR { bits: self._dnf() }
648 }
649 fn _anfoff(&self) -> u8 {
650 const MASK: u8 = 1;
651 const OFFSET: u8 = 12;
652 ((self.bits >> OFFSET) & MASK as u32) as u8
653 }
654 # [ doc = "Bit 12 - Analog noise filter OFF" ]
655 pub fn anfoff(&self) -> AnfoffR {
656 AnfoffR { bits: self._anfoff() }
657 }
658 fn _txdmaen(&self) -> u8 {
659 const MASK: u8 = 1;
660 const OFFSET: u8 = 14;
661 ((self.bits >> OFFSET) & MASK as u32) as u8
662 }
663 # [ doc = "Bit 14 - DMA transmission requests enable" ]
664 pub fn txdmaen(&self) -> TxdmaenR {
665 TxdmaenR { bits: self._txdmaen() }
666 }
667 fn _rxdmaen(&self) -> u8 {
668 const MASK: u8 = 1;
669 const OFFSET: u8 = 15;
670 ((self.bits >> OFFSET) & MASK as u32) as u8
671 }
672 # [ doc = "Bit 15 - DMA reception requests enable" ]
673 pub fn rxdmaen(&self) -> RxdmaenR {
674 RxdmaenR { bits: self._rxdmaen() }
675 }
676 fn _sbc(&self) -> u8 {
677 const MASK: u8 = 1;
678 const OFFSET: u8 = 16;
679 ((self.bits >> OFFSET) & MASK as u32) as u8
680 }
681 # [ doc = "Bit 16 - Slave byte control" ]
682 pub fn sbc(&self) -> SbcR {
683 SbcR { bits: self._sbc() }
684 }
685 fn _nostretch(&self) -> u8 {
686 const MASK: u8 = 1;
687 const OFFSET: u8 = 17;
688 ((self.bits >> OFFSET) & MASK as u32) as u8
689 }
690 # [ doc = "Bit 17 - Clock stretching disable" ]
691 pub fn nostretch(&self) -> NostretchR {
692 NostretchR { bits: self._nostretch() }
693 }
694 fn _wupen(&self) -> u8 {
695 const MASK: u8 = 1;
696 const OFFSET: u8 = 18;
697 ((self.bits >> OFFSET) & MASK as u32) as u8
698 }
699 # [ doc = "Bit 18 - Wakeup from STOP enable" ]
700 pub fn wupen(&self) -> WupenR {
701 WupenR { bits: self._wupen() }
702 }
703 fn _gcen(&self) -> u8 {
704 const MASK: u8 = 1;
705 const OFFSET: u8 = 19;
706 ((self.bits >> OFFSET) & MASK as u32) as u8
707 }
708 # [ doc = "Bit 19 - General call enable" ]
709 pub fn gcen(&self) -> GcenR {
710 GcenR { bits: self._gcen() }
711 }
712 fn _smbhen(&self) -> u8 {
713 const MASK: u8 = 1;
714 const OFFSET: u8 = 20;
715 ((self.bits >> OFFSET) & MASK as u32) as u8
716 }
717 # [ doc = "Bit 20 - SMBus Host address enable" ]
718 pub fn smbhen(&self) -> SmbhenR {
719 SmbhenR { bits: self._smbhen() }
720 }
721 fn _smbden(&self) -> u8 {
722 const MASK: u8 = 1;
723 const OFFSET: u8 = 21;
724 ((self.bits >> OFFSET) & MASK as u32) as u8
725 }
726 # [ doc = "Bit 21 - SMBus Device Default address enable" ]
727 pub fn smbden(&self) -> SmbdenR {
728 SmbdenR { bits: self._smbden() }
729 }
730 fn _alerten(&self) -> u8 {
731 const MASK: u8 = 1;
732 const OFFSET: u8 = 22;
733 ((self.bits >> OFFSET) & MASK as u32) as u8
734 }
735 # [ doc = "Bit 22 - SMBUS alert enable" ]
736 pub fn alerten(&self) -> AlertenR {
737 AlertenR { bits: self._alerten() }
738 }
739 fn _pecen(&self) -> u8 {
740 const MASK: u8 = 1;
741 const OFFSET: u8 = 23;
742 ((self.bits >> OFFSET) & MASK as u32) as u8
743 }
744 # [ doc = "Bit 23 - PEC enable" ]
745 pub fn pecen(&self) -> PecenR {
746 PecenR { bits: self._pecen() }
747 }
748 }
749 impl W {
750 # [ doc = r" Reset value of the register" ]
751 pub fn reset_value() -> W {
752 W { bits: 0 }
753 }
754 # [ doc = r" Writes raw `bits` to the register" ]
755 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
756 self.bits = bits;
757 self
758 }
759 # [ doc = "Bit 0 - Peripheral enable" ]
760 pub fn pe(&mut self) -> _PeW {
761 _PeW { register: self }
762 }
763 # [ doc = "Bit 1 - TX Interrupt enable" ]
764 pub fn txie(&mut self) -> _TxieW {
765 _TxieW { register: self }
766 }
767 # [ doc = "Bit 2 - RX Interrupt enable" ]
768 pub fn rxie(&mut self) -> _RxieW {
769 _RxieW { register: self }
770 }
771 # [ doc = "Bit 3 - Address match interrupt enable (slave only)" ]
772 pub fn addrie(&mut self) -> _AddrieW {
773 _AddrieW { register: self }
774 }
775 # [ doc = "Bit 4 - Not acknowledge received interrupt enable" ]
776 pub fn nackie(&mut self) -> _NackieW {
777 _NackieW { register: self }
778 }
779 # [ doc = "Bit 5 - STOP detection Interrupt enable" ]
780 pub fn stopie(&mut self) -> _StopieW {
781 _StopieW { register: self }
782 }
783 # [ doc = "Bit 6 - Transfer Complete interrupt enable" ]
784 pub fn tcie(&mut self) -> _TcieW {
785 _TcieW { register: self }
786 }
787 # [ doc = "Bit 7 - Error interrupts enable" ]
788 pub fn errie(&mut self) -> _ErrieW {
789 _ErrieW { register: self }
790 }
791 # [ doc = "Bits 8:11 - Digital noise filter" ]
792 pub fn dnf(&mut self) -> _DnfW {
793 _DnfW { register: self }
794 }
795 # [ doc = "Bit 12 - Analog noise filter OFF" ]
796 pub fn anfoff(&mut self) -> _AnfoffW {
797 _AnfoffW { register: self }
798 }
799 # [ doc = "Bit 13 - Software reset" ]
800 pub fn swrst(&mut self) -> _SwrstW {
801 _SwrstW { register: self }
802 }
803 # [ doc = "Bit 14 - DMA transmission requests enable" ]
804 pub fn txdmaen(&mut self) -> _TxdmaenW {
805 _TxdmaenW { register: self }
806 }
807 # [ doc = "Bit 15 - DMA reception requests enable" ]
808 pub fn rxdmaen(&mut self) -> _RxdmaenW {
809 _RxdmaenW { register: self }
810 }
811 # [ doc = "Bit 16 - Slave byte control" ]
812 pub fn sbc(&mut self) -> _SbcW {
813 _SbcW { register: self }
814 }
815 # [ doc = "Bit 17 - Clock stretching disable" ]
816 pub fn nostretch(&mut self) -> _NostretchW {
817 _NostretchW { register: self }
818 }
819 # [ doc = "Bit 18 - Wakeup from STOP enable" ]
820 pub fn wupen(&mut self) -> _WupenW {
821 _WupenW { register: self }
822 }
823 # [ doc = "Bit 19 - General call enable" ]
824 pub fn gcen(&mut self) -> _GcenW {
825 _GcenW { register: self }
826 }
827 # [ doc = "Bit 20 - SMBus Host address enable" ]
828 pub fn smbhen(&mut self) -> _SmbhenW {
829 _SmbhenW { register: self }
830 }
831 # [ doc = "Bit 21 - SMBus Device Default address enable" ]
832 pub fn smbden(&mut self) -> _SmbdenW {
833 _SmbdenW { register: self }
834 }
835 # [ doc = "Bit 22 - SMBUS alert enable" ]
836 pub fn alerten(&mut self) -> _AlertenW {
837 _AlertenW { register: self }
838 }
839 # [ doc = "Bit 23 - PEC enable" ]
840 pub fn pecen(&mut self) -> _PecenW {
841 _PecenW { register: self }
842 }
843 }
844}
845
846# [ doc = "Control register 2" ]
847# [ repr ( C ) ]
848pub struct Cr2 {
849 register: ::volatile_register::RW<u32>,
850}
851
852# [ doc = "Control register 2" ]
853pub mod cr2 {
854 # [ doc = r" Value read from the register" ]
855 pub struct R {
856 bits: u32,
857 }
858 # [ doc = r" Value to write to the register" ]
859 pub struct W {
860 bits: u32,
861 }
862 impl super::Cr2 {
863 # [ doc = r" Modifies the contents of the register" ]
864 pub fn modify<F>(&mut self, f: F)
865 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
866 {
867 let bits = self.register.read();
868 let r = R { bits: bits };
869 let mut w = W { bits: bits };
870 f(&r, &mut w);
871 self.register.write(w.bits);
872 }
873 # [ doc = r" Reads the contents of the register" ]
874 pub fn read(&self) -> R {
875 R { bits: self.register.read() }
876 }
877 # [ doc = r" Writes to the register" ]
878 pub fn write<F>(&mut self, f: F)
879 where F: FnOnce(&mut W) -> &mut W
880 {
881 let mut w = W::reset_value();
882 f(&mut w);
883 self.register.write(w.bits);
884 }
885 }
886 # [ doc = "Value of the field PECBYTE" ]
887 pub struct PecbyteR {
888 bits: u8,
889 }
890 impl PecbyteR {
891 # [ doc = r" Value of the field as raw bits" ]
892 pub fn bits(&self) -> u8 {
893 self.bits
894 }
895 }
896 # [ doc = "Value of the field AUTOEND" ]
897 pub struct AutoendR {
898 bits: u8,
899 }
900 impl AutoendR {
901 # [ doc = r" Value of the field as raw bits" ]
902 pub fn bits(&self) -> u8 {
903 self.bits
904 }
905 }
906 # [ doc = "Value of the field RELOAD" ]
907 pub struct ReloadR {
908 bits: u8,
909 }
910 impl ReloadR {
911 # [ doc = r" Value of the field as raw bits" ]
912 pub fn bits(&self) -> u8 {
913 self.bits
914 }
915 }
916 # [ doc = "Value of the field NBYTES" ]
917 pub struct NbytesR {
918 bits: u8,
919 }
920 impl NbytesR {
921 # [ doc = r" Value of the field as raw bits" ]
922 pub fn bits(&self) -> u8 {
923 self.bits
924 }
925 }
926 # [ doc = "Value of the field NACK" ]
927 pub struct NackR {
928 bits: u8,
929 }
930 impl NackR {
931 # [ doc = r" Value of the field as raw bits" ]
932 pub fn bits(&self) -> u8 {
933 self.bits
934 }
935 }
936 # [ doc = "Value of the field STOP" ]
937 pub struct StopR {
938 bits: u8,
939 }
940 impl StopR {
941 # [ doc = r" Value of the field as raw bits" ]
942 pub fn bits(&self) -> u8 {
943 self.bits
944 }
945 }
946 # [ doc = "Value of the field START" ]
947 pub struct StartR {
948 bits: u8,
949 }
950 impl StartR {
951 # [ doc = r" Value of the field as raw bits" ]
952 pub fn bits(&self) -> u8 {
953 self.bits
954 }
955 }
956 # [ doc = "Value of the field HEAD10R" ]
957 pub struct Head10rR {
958 bits: u8,
959 }
960 impl Head10rR {
961 # [ doc = r" Value of the field as raw bits" ]
962 pub fn bits(&self) -> u8 {
963 self.bits
964 }
965 }
966 # [ doc = "Value of the field ADD10" ]
967 pub struct Add10R {
968 bits: u8,
969 }
970 impl Add10R {
971 # [ doc = r" Value of the field as raw bits" ]
972 pub fn bits(&self) -> u8 {
973 self.bits
974 }
975 }
976 # [ doc = "Value of the field RD_WRN" ]
977 pub struct RdWrnR {
978 bits: u8,
979 }
980 impl RdWrnR {
981 # [ doc = r" Value of the field as raw bits" ]
982 pub fn bits(&self) -> u8 {
983 self.bits
984 }
985 }
986 # [ doc = "Value of the field SADD8" ]
987 pub struct Sadd8R {
988 bits: u8,
989 }
990 impl Sadd8R {
991 # [ doc = r" Value of the field as raw bits" ]
992 pub fn bits(&self) -> u8 {
993 self.bits
994 }
995 }
996 # [ doc = "Value of the field SADD1" ]
997 pub struct Sadd1R {
998 bits: u8,
999 }
1000 impl Sadd1R {
1001 # [ doc = r" Value of the field as raw bits" ]
1002 pub fn bits(&self) -> u8 {
1003 self.bits
1004 }
1005 }
1006 # [ doc = "Value of the field SADD0" ]
1007 pub struct Sadd0R {
1008 bits: u8,
1009 }
1010 impl Sadd0R {
1011 # [ doc = r" Value of the field as raw bits" ]
1012 pub fn bits(&self) -> u8 {
1013 self.bits
1014 }
1015 }
1016 # [ doc = r" Proxy" ]
1017 pub struct _PecbyteW<'a> {
1018 register: &'a mut W,
1019 }
1020 impl<'a> _PecbyteW<'a> {
1021 # [ doc = r" Writes raw `bits` to the field" ]
1022 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1023 const MASK: u8 = 1;
1024 const OFFSET: u8 = 26;
1025 self.register.bits &= !((MASK as u32) << OFFSET);
1026 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1027 self.register
1028 }
1029 }
1030 # [ doc = r" Proxy" ]
1031 pub struct _AutoendW<'a> {
1032 register: &'a mut W,
1033 }
1034 impl<'a> _AutoendW<'a> {
1035 # [ doc = r" Writes raw `bits` to the field" ]
1036 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1037 const MASK: u8 = 1;
1038 const OFFSET: u8 = 25;
1039 self.register.bits &= !((MASK as u32) << OFFSET);
1040 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1041 self.register
1042 }
1043 }
1044 # [ doc = r" Proxy" ]
1045 pub struct _ReloadW<'a> {
1046 register: &'a mut W,
1047 }
1048 impl<'a> _ReloadW<'a> {
1049 # [ doc = r" Writes raw `bits` to the field" ]
1050 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1051 const MASK: u8 = 1;
1052 const OFFSET: u8 = 24;
1053 self.register.bits &= !((MASK as u32) << OFFSET);
1054 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1055 self.register
1056 }
1057 }
1058 # [ doc = r" Proxy" ]
1059 pub struct _NbytesW<'a> {
1060 register: &'a mut W,
1061 }
1062 impl<'a> _NbytesW<'a> {
1063 # [ doc = r" Writes raw `bits` to the field" ]
1064 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1065 const MASK: u8 = 255;
1066 const OFFSET: u8 = 16;
1067 self.register.bits &= !((MASK as u32) << OFFSET);
1068 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1069 self.register
1070 }
1071 }
1072 # [ doc = r" Proxy" ]
1073 pub struct _NackW<'a> {
1074 register: &'a mut W,
1075 }
1076 impl<'a> _NackW<'a> {
1077 # [ doc = r" Writes raw `bits` to the field" ]
1078 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1079 const MASK: u8 = 1;
1080 const OFFSET: u8 = 15;
1081 self.register.bits &= !((MASK as u32) << OFFSET);
1082 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1083 self.register
1084 }
1085 }
1086 # [ doc = r" Proxy" ]
1087 pub struct _StopW<'a> {
1088 register: &'a mut W,
1089 }
1090 impl<'a> _StopW<'a> {
1091 # [ doc = r" Writes raw `bits` to the field" ]
1092 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1093 const MASK: u8 = 1;
1094 const OFFSET: u8 = 14;
1095 self.register.bits &= !((MASK as u32) << OFFSET);
1096 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1097 self.register
1098 }
1099 }
1100 # [ doc = r" Proxy" ]
1101 pub struct _StartW<'a> {
1102 register: &'a mut W,
1103 }
1104 impl<'a> _StartW<'a> {
1105 # [ doc = r" Writes raw `bits` to the field" ]
1106 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1107 const MASK: u8 = 1;
1108 const OFFSET: u8 = 13;
1109 self.register.bits &= !((MASK as u32) << OFFSET);
1110 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1111 self.register
1112 }
1113 }
1114 # [ doc = r" Proxy" ]
1115 pub struct _Head10rW<'a> {
1116 register: &'a mut W,
1117 }
1118 impl<'a> _Head10rW<'a> {
1119 # [ doc = r" Writes raw `bits` to the field" ]
1120 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1121 const MASK: u8 = 1;
1122 const OFFSET: u8 = 12;
1123 self.register.bits &= !((MASK as u32) << OFFSET);
1124 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1125 self.register
1126 }
1127 }
1128 # [ doc = r" Proxy" ]
1129 pub struct _Add10W<'a> {
1130 register: &'a mut W,
1131 }
1132 impl<'a> _Add10W<'a> {
1133 # [ doc = r" Writes raw `bits` to the field" ]
1134 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1135 const MASK: u8 = 1;
1136 const OFFSET: u8 = 11;
1137 self.register.bits &= !((MASK as u32) << OFFSET);
1138 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1139 self.register
1140 }
1141 }
1142 # [ doc = r" Proxy" ]
1143 pub struct _RdWrnW<'a> {
1144 register: &'a mut W,
1145 }
1146 impl<'a> _RdWrnW<'a> {
1147 # [ doc = r" Writes raw `bits` to the field" ]
1148 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1149 const MASK: u8 = 1;
1150 const OFFSET: u8 = 10;
1151 self.register.bits &= !((MASK as u32) << OFFSET);
1152 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1153 self.register
1154 }
1155 }
1156 # [ doc = r" Proxy" ]
1157 pub struct _Sadd8W<'a> {
1158 register: &'a mut W,
1159 }
1160 impl<'a> _Sadd8W<'a> {
1161 # [ doc = r" Writes raw `bits` to the field" ]
1162 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1163 const MASK: u8 = 3;
1164 const OFFSET: u8 = 8;
1165 self.register.bits &= !((MASK as u32) << OFFSET);
1166 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1167 self.register
1168 }
1169 }
1170 # [ doc = r" Proxy" ]
1171 pub struct _Sadd1W<'a> {
1172 register: &'a mut W,
1173 }
1174 impl<'a> _Sadd1W<'a> {
1175 # [ doc = r" Writes raw `bits` to the field" ]
1176 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1177 const MASK: u8 = 127;
1178 const OFFSET: u8 = 1;
1179 self.register.bits &= !((MASK as u32) << OFFSET);
1180 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1181 self.register
1182 }
1183 }
1184 # [ doc = r" Proxy" ]
1185 pub struct _Sadd0W<'a> {
1186 register: &'a mut W,
1187 }
1188 impl<'a> _Sadd0W<'a> {
1189 # [ doc = r" Writes raw `bits` to the field" ]
1190 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1191 const MASK: u8 = 1;
1192 const OFFSET: u8 = 0;
1193 self.register.bits &= !((MASK as u32) << OFFSET);
1194 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1195 self.register
1196 }
1197 }
1198 impl R {
1199 # [ doc = r" Value of the register as raw bits" ]
1200 pub fn bits(&self) -> u32 {
1201 self.bits
1202 }
1203 fn _pecbyte(&self) -> u8 {
1204 const MASK: u8 = 1;
1205 const OFFSET: u8 = 26;
1206 ((self.bits >> OFFSET) & MASK as u32) as u8
1207 }
1208 # [ doc = "Bit 26 - Packet error checking byte" ]
1209 pub fn pecbyte(&self) -> PecbyteR {
1210 PecbyteR { bits: self._pecbyte() }
1211 }
1212 fn _autoend(&self) -> u8 {
1213 const MASK: u8 = 1;
1214 const OFFSET: u8 = 25;
1215 ((self.bits >> OFFSET) & MASK as u32) as u8
1216 }
1217 # [ doc = "Bit 25 - Automatic end mode (master mode)" ]
1218 pub fn autoend(&self) -> AutoendR {
1219 AutoendR { bits: self._autoend() }
1220 }
1221 fn _reload(&self) -> u8 {
1222 const MASK: u8 = 1;
1223 const OFFSET: u8 = 24;
1224 ((self.bits >> OFFSET) & MASK as u32) as u8
1225 }
1226 # [ doc = "Bit 24 - NBYTES reload mode" ]
1227 pub fn reload(&self) -> ReloadR {
1228 ReloadR { bits: self._reload() }
1229 }
1230 fn _nbytes(&self) -> u8 {
1231 const MASK: u8 = 255;
1232 const OFFSET: u8 = 16;
1233 ((self.bits >> OFFSET) & MASK as u32) as u8
1234 }
1235 # [ doc = "Bits 16:23 - Number of bytes" ]
1236 pub fn nbytes(&self) -> NbytesR {
1237 NbytesR { bits: self._nbytes() }
1238 }
1239 fn _nack(&self) -> u8 {
1240 const MASK: u8 = 1;
1241 const OFFSET: u8 = 15;
1242 ((self.bits >> OFFSET) & MASK as u32) as u8
1243 }
1244 # [ doc = "Bit 15 - NACK generation (slave mode)" ]
1245 pub fn nack(&self) -> NackR {
1246 NackR { bits: self._nack() }
1247 }
1248 fn _stop(&self) -> u8 {
1249 const MASK: u8 = 1;
1250 const OFFSET: u8 = 14;
1251 ((self.bits >> OFFSET) & MASK as u32) as u8
1252 }
1253 # [ doc = "Bit 14 - Stop generation (master mode)" ]
1254 pub fn stop(&self) -> StopR {
1255 StopR { bits: self._stop() }
1256 }
1257 fn _start(&self) -> u8 {
1258 const MASK: u8 = 1;
1259 const OFFSET: u8 = 13;
1260 ((self.bits >> OFFSET) & MASK as u32) as u8
1261 }
1262 # [ doc = "Bit 13 - Start generation" ]
1263 pub fn start(&self) -> StartR {
1264 StartR { bits: self._start() }
1265 }
1266 fn _head10r(&self) -> u8 {
1267 const MASK: u8 = 1;
1268 const OFFSET: u8 = 12;
1269 ((self.bits >> OFFSET) & MASK as u32) as u8
1270 }
1271 # [ doc = "Bit 12 - 10-bit address header only read direction (master receiver mode)" ]
1272 pub fn head10r(&self) -> Head10rR {
1273 Head10rR { bits: self._head10r() }
1274 }
1275 fn _add10(&self) -> u8 {
1276 const MASK: u8 = 1;
1277 const OFFSET: u8 = 11;
1278 ((self.bits >> OFFSET) & MASK as u32) as u8
1279 }
1280 # [ doc = "Bit 11 - 10-bit addressing mode (master mode)" ]
1281 pub fn add10(&self) -> Add10R {
1282 Add10R { bits: self._add10() }
1283 }
1284 fn _rd_wrn(&self) -> u8 {
1285 const MASK: u8 = 1;
1286 const OFFSET: u8 = 10;
1287 ((self.bits >> OFFSET) & MASK as u32) as u8
1288 }
1289 # [ doc = "Bit 10 - Transfer direction (master mode)" ]
1290 pub fn rd_wrn(&self) -> RdWrnR {
1291 RdWrnR { bits: self._rd_wrn() }
1292 }
1293 fn _sadd8(&self) -> u8 {
1294 const MASK: u8 = 3;
1295 const OFFSET: u8 = 8;
1296 ((self.bits >> OFFSET) & MASK as u32) as u8
1297 }
1298 # [ doc = "Bits 8:9 - Slave address bit 9:8 (master mode)" ]
1299 pub fn sadd8(&self) -> Sadd8R {
1300 Sadd8R { bits: self._sadd8() }
1301 }
1302 fn _sadd1(&self) -> u8 {
1303 const MASK: u8 = 127;
1304 const OFFSET: u8 = 1;
1305 ((self.bits >> OFFSET) & MASK as u32) as u8
1306 }
1307 # [ doc = "Bits 1:7 - Slave address bit 7:1 (master mode)" ]
1308 pub fn sadd1(&self) -> Sadd1R {
1309 Sadd1R { bits: self._sadd1() }
1310 }
1311 fn _sadd0(&self) -> u8 {
1312 const MASK: u8 = 1;
1313 const OFFSET: u8 = 0;
1314 ((self.bits >> OFFSET) & MASK as u32) as u8
1315 }
1316 # [ doc = "Bit 0 - Slave address bit 0 (master mode)" ]
1317 pub fn sadd0(&self) -> Sadd0R {
1318 Sadd0R { bits: self._sadd0() }
1319 }
1320 }
1321 impl W {
1322 # [ doc = r" Reset value of the register" ]
1323 pub fn reset_value() -> W {
1324 W { bits: 0 }
1325 }
1326 # [ doc = r" Writes raw `bits` to the register" ]
1327 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1328 self.bits = bits;
1329 self
1330 }
1331 # [ doc = "Bit 26 - Packet error checking byte" ]
1332 pub fn pecbyte(&mut self) -> _PecbyteW {
1333 _PecbyteW { register: self }
1334 }
1335 # [ doc = "Bit 25 - Automatic end mode (master mode)" ]
1336 pub fn autoend(&mut self) -> _AutoendW {
1337 _AutoendW { register: self }
1338 }
1339 # [ doc = "Bit 24 - NBYTES reload mode" ]
1340 pub fn reload(&mut self) -> _ReloadW {
1341 _ReloadW { register: self }
1342 }
1343 # [ doc = "Bits 16:23 - Number of bytes" ]
1344 pub fn nbytes(&mut self) -> _NbytesW {
1345 _NbytesW { register: self }
1346 }
1347 # [ doc = "Bit 15 - NACK generation (slave mode)" ]
1348 pub fn nack(&mut self) -> _NackW {
1349 _NackW { register: self }
1350 }
1351 # [ doc = "Bit 14 - Stop generation (master mode)" ]
1352 pub fn stop(&mut self) -> _StopW {
1353 _StopW { register: self }
1354 }
1355 # [ doc = "Bit 13 - Start generation" ]
1356 pub fn start(&mut self) -> _StartW {
1357 _StartW { register: self }
1358 }
1359 # [ doc = "Bit 12 - 10-bit address header only read direction (master receiver mode)" ]
1360 pub fn head10r(&mut self) -> _Head10rW {
1361 _Head10rW { register: self }
1362 }
1363 # [ doc = "Bit 11 - 10-bit addressing mode (master mode)" ]
1364 pub fn add10(&mut self) -> _Add10W {
1365 _Add10W { register: self }
1366 }
1367 # [ doc = "Bit 10 - Transfer direction (master mode)" ]
1368 pub fn rd_wrn(&mut self) -> _RdWrnW {
1369 _RdWrnW { register: self }
1370 }
1371 # [ doc = "Bits 8:9 - Slave address bit 9:8 (master mode)" ]
1372 pub fn sadd8(&mut self) -> _Sadd8W {
1373 _Sadd8W { register: self }
1374 }
1375 # [ doc = "Bits 1:7 - Slave address bit 7:1 (master mode)" ]
1376 pub fn sadd1(&mut self) -> _Sadd1W {
1377 _Sadd1W { register: self }
1378 }
1379 # [ doc = "Bit 0 - Slave address bit 0 (master mode)" ]
1380 pub fn sadd0(&mut self) -> _Sadd0W {
1381 _Sadd0W { register: self }
1382 }
1383 }
1384}
1385
1386# [ doc = "Own address register 1" ]
1387# [ repr ( C ) ]
1388pub struct Oar1 {
1389 register: ::volatile_register::RW<u32>,
1390}
1391
1392# [ doc = "Own address register 1" ]
1393pub mod oar1 {
1394 # [ doc = r" Value read from the register" ]
1395 pub struct R {
1396 bits: u32,
1397 }
1398 # [ doc = r" Value to write to the register" ]
1399 pub struct W {
1400 bits: u32,
1401 }
1402 impl super::Oar1 {
1403 # [ doc = r" Modifies the contents of the register" ]
1404 pub fn modify<F>(&mut self, f: F)
1405 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
1406 {
1407 let bits = self.register.read();
1408 let r = R { bits: bits };
1409 let mut w = W { bits: bits };
1410 f(&r, &mut w);
1411 self.register.write(w.bits);
1412 }
1413 # [ doc = r" Reads the contents of the register" ]
1414 pub fn read(&self) -> R {
1415 R { bits: self.register.read() }
1416 }
1417 # [ doc = r" Writes to the register" ]
1418 pub fn write<F>(&mut self, f: F)
1419 where F: FnOnce(&mut W) -> &mut W
1420 {
1421 let mut w = W::reset_value();
1422 f(&mut w);
1423 self.register.write(w.bits);
1424 }
1425 }
1426 # [ doc = "Value of the field OA1_0" ]
1427 pub struct Oa10R {
1428 bits: u8,
1429 }
1430 impl Oa10R {
1431 # [ doc = r" Value of the field as raw bits" ]
1432 pub fn bits(&self) -> u8 {
1433 self.bits
1434 }
1435 }
1436 # [ doc = "Value of the field OA1_1" ]
1437 pub struct Oa11R {
1438 bits: u8,
1439 }
1440 impl Oa11R {
1441 # [ doc = r" Value of the field as raw bits" ]
1442 pub fn bits(&self) -> u8 {
1443 self.bits
1444 }
1445 }
1446 # [ doc = "Value of the field OA1_8" ]
1447 pub struct Oa18R {
1448 bits: u8,
1449 }
1450 impl Oa18R {
1451 # [ doc = r" Value of the field as raw bits" ]
1452 pub fn bits(&self) -> u8 {
1453 self.bits
1454 }
1455 }
1456 # [ doc = "Value of the field OA1MODE" ]
1457 pub struct Oa1modeR {
1458 bits: u8,
1459 }
1460 impl Oa1modeR {
1461 # [ doc = r" Value of the field as raw bits" ]
1462 pub fn bits(&self) -> u8 {
1463 self.bits
1464 }
1465 }
1466 # [ doc = "Value of the field OA1EN" ]
1467 pub struct Oa1enR {
1468 bits: u8,
1469 }
1470 impl Oa1enR {
1471 # [ doc = r" Value of the field as raw bits" ]
1472 pub fn bits(&self) -> u8 {
1473 self.bits
1474 }
1475 }
1476 # [ doc = r" Proxy" ]
1477 pub struct _Oa10W<'a> {
1478 register: &'a mut W,
1479 }
1480 impl<'a> _Oa10W<'a> {
1481 # [ doc = r" Writes raw `bits` to the field" ]
1482 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1483 const MASK: u8 = 1;
1484 const OFFSET: u8 = 0;
1485 self.register.bits &= !((MASK as u32) << OFFSET);
1486 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1487 self.register
1488 }
1489 }
1490 # [ doc = r" Proxy" ]
1491 pub struct _Oa11W<'a> {
1492 register: &'a mut W,
1493 }
1494 impl<'a> _Oa11W<'a> {
1495 # [ doc = r" Writes raw `bits` to the field" ]
1496 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1497 const MASK: u8 = 127;
1498 const OFFSET: u8 = 1;
1499 self.register.bits &= !((MASK as u32) << OFFSET);
1500 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1501 self.register
1502 }
1503 }
1504 # [ doc = r" Proxy" ]
1505 pub struct _Oa18W<'a> {
1506 register: &'a mut W,
1507 }
1508 impl<'a> _Oa18W<'a> {
1509 # [ doc = r" Writes raw `bits` to the field" ]
1510 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1511 const MASK: u8 = 3;
1512 const OFFSET: u8 = 8;
1513 self.register.bits &= !((MASK as u32) << OFFSET);
1514 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1515 self.register
1516 }
1517 }
1518 # [ doc = r" Proxy" ]
1519 pub struct _Oa1modeW<'a> {
1520 register: &'a mut W,
1521 }
1522 impl<'a> _Oa1modeW<'a> {
1523 # [ doc = r" Writes raw `bits` to the field" ]
1524 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1525 const MASK: u8 = 1;
1526 const OFFSET: u8 = 10;
1527 self.register.bits &= !((MASK as u32) << OFFSET);
1528 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1529 self.register
1530 }
1531 }
1532 # [ doc = r" Proxy" ]
1533 pub struct _Oa1enW<'a> {
1534 register: &'a mut W,
1535 }
1536 impl<'a> _Oa1enW<'a> {
1537 # [ doc = r" Writes raw `bits` to the field" ]
1538 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1539 const MASK: u8 = 1;
1540 const OFFSET: u8 = 15;
1541 self.register.bits &= !((MASK as u32) << OFFSET);
1542 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1543 self.register
1544 }
1545 }
1546 impl R {
1547 # [ doc = r" Value of the register as raw bits" ]
1548 pub fn bits(&self) -> u32 {
1549 self.bits
1550 }
1551 fn _oa1_0(&self) -> u8 {
1552 const MASK: u8 = 1;
1553 const OFFSET: u8 = 0;
1554 ((self.bits >> OFFSET) & MASK as u32) as u8
1555 }
1556 # [ doc = "Bit 0 - Interface address" ]
1557 pub fn oa1_0(&self) -> Oa10R {
1558 Oa10R { bits: self._oa1_0() }
1559 }
1560 fn _oa1_1(&self) -> u8 {
1561 const MASK: u8 = 127;
1562 const OFFSET: u8 = 1;
1563 ((self.bits >> OFFSET) & MASK as u32) as u8
1564 }
1565 # [ doc = "Bits 1:7 - Interface address" ]
1566 pub fn oa1_1(&self) -> Oa11R {
1567 Oa11R { bits: self._oa1_1() }
1568 }
1569 fn _oa1_8(&self) -> u8 {
1570 const MASK: u8 = 3;
1571 const OFFSET: u8 = 8;
1572 ((self.bits >> OFFSET) & MASK as u32) as u8
1573 }
1574 # [ doc = "Bits 8:9 - Interface address" ]
1575 pub fn oa1_8(&self) -> Oa18R {
1576 Oa18R { bits: self._oa1_8() }
1577 }
1578 fn _oa1mode(&self) -> u8 {
1579 const MASK: u8 = 1;
1580 const OFFSET: u8 = 10;
1581 ((self.bits >> OFFSET) & MASK as u32) as u8
1582 }
1583 # [ doc = "Bit 10 - Own Address 1 10-bit mode" ]
1584 pub fn oa1mode(&self) -> Oa1modeR {
1585 Oa1modeR { bits: self._oa1mode() }
1586 }
1587 fn _oa1en(&self) -> u8 {
1588 const MASK: u8 = 1;
1589 const OFFSET: u8 = 15;
1590 ((self.bits >> OFFSET) & MASK as u32) as u8
1591 }
1592 # [ doc = "Bit 15 - Own Address 1 enable" ]
1593 pub fn oa1en(&self) -> Oa1enR {
1594 Oa1enR { bits: self._oa1en() }
1595 }
1596 }
1597 impl W {
1598 # [ doc = r" Reset value of the register" ]
1599 pub fn reset_value() -> W {
1600 W { bits: 0 }
1601 }
1602 # [ doc = r" Writes raw `bits` to the register" ]
1603 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1604 self.bits = bits;
1605 self
1606 }
1607 # [ doc = "Bit 0 - Interface address" ]
1608 pub fn oa1_0(&mut self) -> _Oa10W {
1609 _Oa10W { register: self }
1610 }
1611 # [ doc = "Bits 1:7 - Interface address" ]
1612 pub fn oa1_1(&mut self) -> _Oa11W {
1613 _Oa11W { register: self }
1614 }
1615 # [ doc = "Bits 8:9 - Interface address" ]
1616 pub fn oa1_8(&mut self) -> _Oa18W {
1617 _Oa18W { register: self }
1618 }
1619 # [ doc = "Bit 10 - Own Address 1 10-bit mode" ]
1620 pub fn oa1mode(&mut self) -> _Oa1modeW {
1621 _Oa1modeW { register: self }
1622 }
1623 # [ doc = "Bit 15 - Own Address 1 enable" ]
1624 pub fn oa1en(&mut self) -> _Oa1enW {
1625 _Oa1enW { register: self }
1626 }
1627 }
1628}
1629
1630# [ doc = "Own address register 2" ]
1631# [ repr ( C ) ]
1632pub struct Oar2 {
1633 register: ::volatile_register::RW<u32>,
1634}
1635
1636# [ doc = "Own address register 2" ]
1637pub mod oar2 {
1638 # [ doc = r" Value read from the register" ]
1639 pub struct R {
1640 bits: u32,
1641 }
1642 # [ doc = r" Value to write to the register" ]
1643 pub struct W {
1644 bits: u32,
1645 }
1646 impl super::Oar2 {
1647 # [ doc = r" Modifies the contents of the register" ]
1648 pub fn modify<F>(&mut self, f: F)
1649 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
1650 {
1651 let bits = self.register.read();
1652 let r = R { bits: bits };
1653 let mut w = W { bits: bits };
1654 f(&r, &mut w);
1655 self.register.write(w.bits);
1656 }
1657 # [ doc = r" Reads the contents of the register" ]
1658 pub fn read(&self) -> R {
1659 R { bits: self.register.read() }
1660 }
1661 # [ doc = r" Writes to the register" ]
1662 pub fn write<F>(&mut self, f: F)
1663 where F: FnOnce(&mut W) -> &mut W
1664 {
1665 let mut w = W::reset_value();
1666 f(&mut w);
1667 self.register.write(w.bits);
1668 }
1669 }
1670 # [ doc = "Value of the field OA2" ]
1671 pub struct Oa2R {
1672 bits: u8,
1673 }
1674 impl Oa2R {
1675 # [ doc = r" Value of the field as raw bits" ]
1676 pub fn bits(&self) -> u8 {
1677 self.bits
1678 }
1679 }
1680 # [ doc = "Value of the field OA2MSK" ]
1681 pub struct Oa2mskR {
1682 bits: u8,
1683 }
1684 impl Oa2mskR {
1685 # [ doc = r" Value of the field as raw bits" ]
1686 pub fn bits(&self) -> u8 {
1687 self.bits
1688 }
1689 }
1690 # [ doc = "Value of the field OA2EN" ]
1691 pub struct Oa2enR {
1692 bits: u8,
1693 }
1694 impl Oa2enR {
1695 # [ doc = r" Value of the field as raw bits" ]
1696 pub fn bits(&self) -> u8 {
1697 self.bits
1698 }
1699 }
1700 # [ doc = r" Proxy" ]
1701 pub struct _Oa2W<'a> {
1702 register: &'a mut W,
1703 }
1704 impl<'a> _Oa2W<'a> {
1705 # [ doc = r" Writes raw `bits` to the field" ]
1706 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1707 const MASK: u8 = 127;
1708 const OFFSET: u8 = 1;
1709 self.register.bits &= !((MASK as u32) << OFFSET);
1710 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1711 self.register
1712 }
1713 }
1714 # [ doc = r" Proxy" ]
1715 pub struct _Oa2mskW<'a> {
1716 register: &'a mut W,
1717 }
1718 impl<'a> _Oa2mskW<'a> {
1719 # [ doc = r" Writes raw `bits` to the field" ]
1720 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1721 const MASK: u8 = 7;
1722 const OFFSET: u8 = 8;
1723 self.register.bits &= !((MASK as u32) << OFFSET);
1724 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1725 self.register
1726 }
1727 }
1728 # [ doc = r" Proxy" ]
1729 pub struct _Oa2enW<'a> {
1730 register: &'a mut W,
1731 }
1732 impl<'a> _Oa2enW<'a> {
1733 # [ doc = r" Writes raw `bits` to the field" ]
1734 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1735 const MASK: u8 = 1;
1736 const OFFSET: u8 = 15;
1737 self.register.bits &= !((MASK as u32) << OFFSET);
1738 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1739 self.register
1740 }
1741 }
1742 impl R {
1743 # [ doc = r" Value of the register as raw bits" ]
1744 pub fn bits(&self) -> u32 {
1745 self.bits
1746 }
1747 fn _oa2(&self) -> u8 {
1748 const MASK: u8 = 127;
1749 const OFFSET: u8 = 1;
1750 ((self.bits >> OFFSET) & MASK as u32) as u8
1751 }
1752 # [ doc = "Bits 1:7 - Interface address" ]
1753 pub fn oa2(&self) -> Oa2R {
1754 Oa2R { bits: self._oa2() }
1755 }
1756 fn _oa2msk(&self) -> u8 {
1757 const MASK: u8 = 7;
1758 const OFFSET: u8 = 8;
1759 ((self.bits >> OFFSET) & MASK as u32) as u8
1760 }
1761 # [ doc = "Bits 8:10 - Own Address 2 masks" ]
1762 pub fn oa2msk(&self) -> Oa2mskR {
1763 Oa2mskR { bits: self._oa2msk() }
1764 }
1765 fn _oa2en(&self) -> u8 {
1766 const MASK: u8 = 1;
1767 const OFFSET: u8 = 15;
1768 ((self.bits >> OFFSET) & MASK as u32) as u8
1769 }
1770 # [ doc = "Bit 15 - Own Address 2 enable" ]
1771 pub fn oa2en(&self) -> Oa2enR {
1772 Oa2enR { bits: self._oa2en() }
1773 }
1774 }
1775 impl W {
1776 # [ doc = r" Reset value of the register" ]
1777 pub fn reset_value() -> W {
1778 W { bits: 0 }
1779 }
1780 # [ doc = r" Writes raw `bits` to the register" ]
1781 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1782 self.bits = bits;
1783 self
1784 }
1785 # [ doc = "Bits 1:7 - Interface address" ]
1786 pub fn oa2(&mut self) -> _Oa2W {
1787 _Oa2W { register: self }
1788 }
1789 # [ doc = "Bits 8:10 - Own Address 2 masks" ]
1790 pub fn oa2msk(&mut self) -> _Oa2mskW {
1791 _Oa2mskW { register: self }
1792 }
1793 # [ doc = "Bit 15 - Own Address 2 enable" ]
1794 pub fn oa2en(&mut self) -> _Oa2enW {
1795 _Oa2enW { register: self }
1796 }
1797 }
1798}
1799
1800# [ doc = "Timing register" ]
1801# [ repr ( C ) ]
1802pub struct Timingr {
1803 register: ::volatile_register::RW<u32>,
1804}
1805
1806# [ doc = "Timing register" ]
1807pub mod timingr {
1808 # [ doc = r" Value read from the register" ]
1809 pub struct R {
1810 bits: u32,
1811 }
1812 # [ doc = r" Value to write to the register" ]
1813 pub struct W {
1814 bits: u32,
1815 }
1816 impl super::Timingr {
1817 # [ doc = r" Modifies the contents of the register" ]
1818 pub fn modify<F>(&mut self, f: F)
1819 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
1820 {
1821 let bits = self.register.read();
1822 let r = R { bits: bits };
1823 let mut w = W { bits: bits };
1824 f(&r, &mut w);
1825 self.register.write(w.bits);
1826 }
1827 # [ doc = r" Reads the contents of the register" ]
1828 pub fn read(&self) -> R {
1829 R { bits: self.register.read() }
1830 }
1831 # [ doc = r" Writes to the register" ]
1832 pub fn write<F>(&mut self, f: F)
1833 where F: FnOnce(&mut W) -> &mut W
1834 {
1835 let mut w = W::reset_value();
1836 f(&mut w);
1837 self.register.write(w.bits);
1838 }
1839 }
1840 # [ doc = "Value of the field SCLL" ]
1841 pub struct ScllR {
1842 bits: u8,
1843 }
1844 impl ScllR {
1845 # [ doc = r" Value of the field as raw bits" ]
1846 pub fn bits(&self) -> u8 {
1847 self.bits
1848 }
1849 }
1850 # [ doc = "Value of the field SCLH" ]
1851 pub struct SclhR {
1852 bits: u8,
1853 }
1854 impl SclhR {
1855 # [ doc = r" Value of the field as raw bits" ]
1856 pub fn bits(&self) -> u8 {
1857 self.bits
1858 }
1859 }
1860 # [ doc = "Value of the field SDADEL" ]
1861 pub struct SdadelR {
1862 bits: u8,
1863 }
1864 impl SdadelR {
1865 # [ doc = r" Value of the field as raw bits" ]
1866 pub fn bits(&self) -> u8 {
1867 self.bits
1868 }
1869 }
1870 # [ doc = "Value of the field SCLDEL" ]
1871 pub struct ScldelR {
1872 bits: u8,
1873 }
1874 impl ScldelR {
1875 # [ doc = r" Value of the field as raw bits" ]
1876 pub fn bits(&self) -> u8 {
1877 self.bits
1878 }
1879 }
1880 # [ doc = "Value of the field PRESC" ]
1881 pub struct PrescR {
1882 bits: u8,
1883 }
1884 impl PrescR {
1885 # [ doc = r" Value of the field as raw bits" ]
1886 pub fn bits(&self) -> u8 {
1887 self.bits
1888 }
1889 }
1890 # [ doc = r" Proxy" ]
1891 pub struct _ScllW<'a> {
1892 register: &'a mut W,
1893 }
1894 impl<'a> _ScllW<'a> {
1895 # [ doc = r" Writes raw `bits` to the field" ]
1896 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1897 const MASK: u8 = 255;
1898 const OFFSET: u8 = 0;
1899 self.register.bits &= !((MASK as u32) << OFFSET);
1900 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1901 self.register
1902 }
1903 }
1904 # [ doc = r" Proxy" ]
1905 pub struct _SclhW<'a> {
1906 register: &'a mut W,
1907 }
1908 impl<'a> _SclhW<'a> {
1909 # [ doc = r" Writes raw `bits` to the field" ]
1910 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1911 const MASK: u8 = 255;
1912 const OFFSET: u8 = 8;
1913 self.register.bits &= !((MASK as u32) << OFFSET);
1914 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1915 self.register
1916 }
1917 }
1918 # [ doc = r" Proxy" ]
1919 pub struct _SdadelW<'a> {
1920 register: &'a mut W,
1921 }
1922 impl<'a> _SdadelW<'a> {
1923 # [ doc = r" Writes raw `bits` to the field" ]
1924 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1925 const MASK: u8 = 15;
1926 const OFFSET: u8 = 16;
1927 self.register.bits &= !((MASK as u32) << OFFSET);
1928 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1929 self.register
1930 }
1931 }
1932 # [ doc = r" Proxy" ]
1933 pub struct _ScldelW<'a> {
1934 register: &'a mut W,
1935 }
1936 impl<'a> _ScldelW<'a> {
1937 # [ doc = r" Writes raw `bits` to the field" ]
1938 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1939 const MASK: u8 = 15;
1940 const OFFSET: u8 = 20;
1941 self.register.bits &= !((MASK as u32) << OFFSET);
1942 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1943 self.register
1944 }
1945 }
1946 # [ doc = r" Proxy" ]
1947 pub struct _PrescW<'a> {
1948 register: &'a mut W,
1949 }
1950 impl<'a> _PrescW<'a> {
1951 # [ doc = r" Writes raw `bits` to the field" ]
1952 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1953 const MASK: u8 = 15;
1954 const OFFSET: u8 = 28;
1955 self.register.bits &= !((MASK as u32) << OFFSET);
1956 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1957 self.register
1958 }
1959 }
1960 impl R {
1961 # [ doc = r" Value of the register as raw bits" ]
1962 pub fn bits(&self) -> u32 {
1963 self.bits
1964 }
1965 fn _scll(&self) -> u8 {
1966 const MASK: u8 = 255;
1967 const OFFSET: u8 = 0;
1968 ((self.bits >> OFFSET) & MASK as u32) as u8
1969 }
1970 # [ doc = "Bits 0:7 - SCL low period (master mode)" ]
1971 pub fn scll(&self) -> ScllR {
1972 ScllR { bits: self._scll() }
1973 }
1974 fn _sclh(&self) -> u8 {
1975 const MASK: u8 = 255;
1976 const OFFSET: u8 = 8;
1977 ((self.bits >> OFFSET) & MASK as u32) as u8
1978 }
1979 # [ doc = "Bits 8:15 - SCL high period (master mode)" ]
1980 pub fn sclh(&self) -> SclhR {
1981 SclhR { bits: self._sclh() }
1982 }
1983 fn _sdadel(&self) -> u8 {
1984 const MASK: u8 = 15;
1985 const OFFSET: u8 = 16;
1986 ((self.bits >> OFFSET) & MASK as u32) as u8
1987 }
1988 # [ doc = "Bits 16:19 - Data hold time" ]
1989 pub fn sdadel(&self) -> SdadelR {
1990 SdadelR { bits: self._sdadel() }
1991 }
1992 fn _scldel(&self) -> u8 {
1993 const MASK: u8 = 15;
1994 const OFFSET: u8 = 20;
1995 ((self.bits >> OFFSET) & MASK as u32) as u8
1996 }
1997 # [ doc = "Bits 20:23 - Data setup time" ]
1998 pub fn scldel(&self) -> ScldelR {
1999 ScldelR { bits: self._scldel() }
2000 }
2001 fn _presc(&self) -> u8 {
2002 const MASK: u8 = 15;
2003 const OFFSET: u8 = 28;
2004 ((self.bits >> OFFSET) & MASK as u32) as u8
2005 }
2006 # [ doc = "Bits 28:31 - Timing prescaler" ]
2007 pub fn presc(&self) -> PrescR {
2008 PrescR { bits: self._presc() }
2009 }
2010 }
2011 impl W {
2012 # [ doc = r" Reset value of the register" ]
2013 pub fn reset_value() -> W {
2014 W { bits: 0 }
2015 }
2016 # [ doc = r" Writes raw `bits` to the register" ]
2017 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
2018 self.bits = bits;
2019 self
2020 }
2021 # [ doc = "Bits 0:7 - SCL low period (master mode)" ]
2022 pub fn scll(&mut self) -> _ScllW {
2023 _ScllW { register: self }
2024 }
2025 # [ doc = "Bits 8:15 - SCL high period (master mode)" ]
2026 pub fn sclh(&mut self) -> _SclhW {
2027 _SclhW { register: self }
2028 }
2029 # [ doc = "Bits 16:19 - Data hold time" ]
2030 pub fn sdadel(&mut self) -> _SdadelW {
2031 _SdadelW { register: self }
2032 }
2033 # [ doc = "Bits 20:23 - Data setup time" ]
2034 pub fn scldel(&mut self) -> _ScldelW {
2035 _ScldelW { register: self }
2036 }
2037 # [ doc = "Bits 28:31 - Timing prescaler" ]
2038 pub fn presc(&mut self) -> _PrescW {
2039 _PrescW { register: self }
2040 }
2041 }
2042}
2043
2044# [ doc = "Status register 1" ]
2045# [ repr ( C ) ]
2046pub struct Timeoutr {
2047 register: ::volatile_register::RW<u32>,
2048}
2049
2050# [ doc = "Status register 1" ]
2051pub mod timeoutr {
2052 # [ doc = r" Value read from the register" ]
2053 pub struct R {
2054 bits: u32,
2055 }
2056 # [ doc = r" Value to write to the register" ]
2057 pub struct W {
2058 bits: u32,
2059 }
2060 impl super::Timeoutr {
2061 # [ doc = r" Modifies the contents of the register" ]
2062 pub fn modify<F>(&mut self, f: F)
2063 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
2064 {
2065 let bits = self.register.read();
2066 let r = R { bits: bits };
2067 let mut w = W { bits: bits };
2068 f(&r, &mut w);
2069 self.register.write(w.bits);
2070 }
2071 # [ doc = r" Reads the contents of the register" ]
2072 pub fn read(&self) -> R {
2073 R { bits: self.register.read() }
2074 }
2075 # [ doc = r" Writes to the register" ]
2076 pub fn write<F>(&mut self, f: F)
2077 where F: FnOnce(&mut W) -> &mut W
2078 {
2079 let mut w = W::reset_value();
2080 f(&mut w);
2081 self.register.write(w.bits);
2082 }
2083 }
2084 # [ doc = "Value of the field TIMEOUTA" ]
2085 pub struct TimeoutaR {
2086 bits: u16,
2087 }
2088 impl TimeoutaR {
2089 # [ doc = r" Value of the field as raw bits" ]
2090 pub fn bits(&self) -> u16 {
2091 self.bits
2092 }
2093 }
2094 # [ doc = "Value of the field TIDLE" ]
2095 pub struct TidleR {
2096 bits: u8,
2097 }
2098 impl TidleR {
2099 # [ doc = r" Value of the field as raw bits" ]
2100 pub fn bits(&self) -> u8 {
2101 self.bits
2102 }
2103 }
2104 # [ doc = "Value of the field TIMOUTEN" ]
2105 pub struct TimoutenR {
2106 bits: u8,
2107 }
2108 impl TimoutenR {
2109 # [ doc = r" Value of the field as raw bits" ]
2110 pub fn bits(&self) -> u8 {
2111 self.bits
2112 }
2113 }
2114 # [ doc = "Value of the field TIMEOUTB" ]
2115 pub struct TimeoutbR {
2116 bits: u16,
2117 }
2118 impl TimeoutbR {
2119 # [ doc = r" Value of the field as raw bits" ]
2120 pub fn bits(&self) -> u16 {
2121 self.bits
2122 }
2123 }
2124 # [ doc = "Value of the field TEXTEN" ]
2125 pub struct TextenR {
2126 bits: u8,
2127 }
2128 impl TextenR {
2129 # [ doc = r" Value of the field as raw bits" ]
2130 pub fn bits(&self) -> u8 {
2131 self.bits
2132 }
2133 }
2134 # [ doc = r" Proxy" ]
2135 pub struct _TimeoutaW<'a> {
2136 register: &'a mut W,
2137 }
2138 impl<'a> _TimeoutaW<'a> {
2139 # [ doc = r" Writes raw `bits` to the field" ]
2140 pub unsafe fn bits(self, bits: u16) -> &'a mut W {
2141 const MASK: u16 = 4095;
2142 const OFFSET: u8 = 0;
2143 self.register.bits &= !((MASK as u32) << OFFSET);
2144 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2145 self.register
2146 }
2147 }
2148 # [ doc = r" Proxy" ]
2149 pub struct _TidleW<'a> {
2150 register: &'a mut W,
2151 }
2152 impl<'a> _TidleW<'a> {
2153 # [ doc = r" Writes raw `bits` to the field" ]
2154 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2155 const MASK: u8 = 1;
2156 const OFFSET: u8 = 12;
2157 self.register.bits &= !((MASK as u32) << OFFSET);
2158 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2159 self.register
2160 }
2161 }
2162 # [ doc = r" Proxy" ]
2163 pub struct _TimoutenW<'a> {
2164 register: &'a mut W,
2165 }
2166 impl<'a> _TimoutenW<'a> {
2167 # [ doc = r" Writes raw `bits` to the field" ]
2168 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2169 const MASK: u8 = 1;
2170 const OFFSET: u8 = 15;
2171 self.register.bits &= !((MASK as u32) << OFFSET);
2172 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2173 self.register
2174 }
2175 }
2176 # [ doc = r" Proxy" ]
2177 pub struct _TimeoutbW<'a> {
2178 register: &'a mut W,
2179 }
2180 impl<'a> _TimeoutbW<'a> {
2181 # [ doc = r" Writes raw `bits` to the field" ]
2182 pub unsafe fn bits(self, bits: u16) -> &'a mut W {
2183 const MASK: u16 = 4095;
2184 const OFFSET: u8 = 16;
2185 self.register.bits &= !((MASK as u32) << OFFSET);
2186 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2187 self.register
2188 }
2189 }
2190 # [ doc = r" Proxy" ]
2191 pub struct _TextenW<'a> {
2192 register: &'a mut W,
2193 }
2194 impl<'a> _TextenW<'a> {
2195 # [ doc = r" Writes raw `bits` to the field" ]
2196 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2197 const MASK: u8 = 1;
2198 const OFFSET: u8 = 31;
2199 self.register.bits &= !((MASK as u32) << OFFSET);
2200 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2201 self.register
2202 }
2203 }
2204 impl R {
2205 # [ doc = r" Value of the register as raw bits" ]
2206 pub fn bits(&self) -> u32 {
2207 self.bits
2208 }
2209 fn _timeouta(&self) -> u16 {
2210 const MASK: u16 = 4095;
2211 const OFFSET: u8 = 0;
2212 ((self.bits >> OFFSET) & MASK as u32) as u16
2213 }
2214 # [ doc = "Bits 0:11 - Bus timeout A" ]
2215 pub fn timeouta(&self) -> TimeoutaR {
2216 TimeoutaR { bits: self._timeouta() }
2217 }
2218 fn _tidle(&self) -> u8 {
2219 const MASK: u8 = 1;
2220 const OFFSET: u8 = 12;
2221 ((self.bits >> OFFSET) & MASK as u32) as u8
2222 }
2223 # [ doc = "Bit 12 - Idle clock timeout detection" ]
2224 pub fn tidle(&self) -> TidleR {
2225 TidleR { bits: self._tidle() }
2226 }
2227 fn _timouten(&self) -> u8 {
2228 const MASK: u8 = 1;
2229 const OFFSET: u8 = 15;
2230 ((self.bits >> OFFSET) & MASK as u32) as u8
2231 }
2232 # [ doc = "Bit 15 - Clock timeout enable" ]
2233 pub fn timouten(&self) -> TimoutenR {
2234 TimoutenR { bits: self._timouten() }
2235 }
2236 fn _timeoutb(&self) -> u16 {
2237 const MASK: u16 = 4095;
2238 const OFFSET: u8 = 16;
2239 ((self.bits >> OFFSET) & MASK as u32) as u16
2240 }
2241 # [ doc = "Bits 16:27 - Bus timeout B" ]
2242 pub fn timeoutb(&self) -> TimeoutbR {
2243 TimeoutbR { bits: self._timeoutb() }
2244 }
2245 fn _texten(&self) -> u8 {
2246 const MASK: u8 = 1;
2247 const OFFSET: u8 = 31;
2248 ((self.bits >> OFFSET) & MASK as u32) as u8
2249 }
2250 # [ doc = "Bit 31 - Extended clock timeout enable" ]
2251 pub fn texten(&self) -> TextenR {
2252 TextenR { bits: self._texten() }
2253 }
2254 }
2255 impl W {
2256 # [ doc = r" Reset value of the register" ]
2257 pub fn reset_value() -> W {
2258 W { bits: 0 }
2259 }
2260 # [ doc = r" Writes raw `bits` to the register" ]
2261 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
2262 self.bits = bits;
2263 self
2264 }
2265 # [ doc = "Bits 0:11 - Bus timeout A" ]
2266 pub fn timeouta(&mut self) -> _TimeoutaW {
2267 _TimeoutaW { register: self }
2268 }
2269 # [ doc = "Bit 12 - Idle clock timeout detection" ]
2270 pub fn tidle(&mut self) -> _TidleW {
2271 _TidleW { register: self }
2272 }
2273 # [ doc = "Bit 15 - Clock timeout enable" ]
2274 pub fn timouten(&mut self) -> _TimoutenW {
2275 _TimoutenW { register: self }
2276 }
2277 # [ doc = "Bits 16:27 - Bus timeout B" ]
2278 pub fn timeoutb(&mut self) -> _TimeoutbW {
2279 _TimeoutbW { register: self }
2280 }
2281 # [ doc = "Bit 31 - Extended clock timeout enable" ]
2282 pub fn texten(&mut self) -> _TextenW {
2283 _TextenW { register: self }
2284 }
2285 }
2286}
2287
2288# [ doc = "Interrupt and Status register" ]
2289# [ repr ( C ) ]
2290pub struct Isr {
2291 register: ::volatile_register::RW<u32>,
2292}
2293
2294# [ doc = "Interrupt and Status register" ]
2295pub mod isr {
2296 # [ doc = r" Value read from the register" ]
2297 pub struct R {
2298 bits: u32,
2299 }
2300 # [ doc = r" Value to write to the register" ]
2301 pub struct W {
2302 bits: u32,
2303 }
2304 impl super::Isr {
2305 # [ doc = r" Modifies the contents of the register" ]
2306 pub fn modify<F>(&mut self, f: F)
2307 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
2308 {
2309 let bits = self.register.read();
2310 let r = R { bits: bits };
2311 let mut w = W { bits: bits };
2312 f(&r, &mut w);
2313 self.register.write(w.bits);
2314 }
2315 # [ doc = r" Reads the contents of the register" ]
2316 pub fn read(&self) -> R {
2317 R { bits: self.register.read() }
2318 }
2319 # [ doc = r" Writes to the register" ]
2320 pub fn write<F>(&mut self, f: F)
2321 where F: FnOnce(&mut W) -> &mut W
2322 {
2323 let mut w = W::reset_value();
2324 f(&mut w);
2325 self.register.write(w.bits);
2326 }
2327 }
2328 # [ doc = "Value of the field ADDCODE" ]
2329 pub struct AddcodeR {
2330 bits: u8,
2331 }
2332 impl AddcodeR {
2333 # [ doc = r" Value of the field as raw bits" ]
2334 pub fn bits(&self) -> u8 {
2335 self.bits
2336 }
2337 }
2338 # [ doc = "Value of the field DIR" ]
2339 pub struct DirR {
2340 bits: u8,
2341 }
2342 impl DirR {
2343 # [ doc = r" Value of the field as raw bits" ]
2344 pub fn bits(&self) -> u8 {
2345 self.bits
2346 }
2347 }
2348 # [ doc = "Value of the field BUSY" ]
2349 pub struct BusyR {
2350 bits: u8,
2351 }
2352 impl BusyR {
2353 # [ doc = r" Value of the field as raw bits" ]
2354 pub fn bits(&self) -> u8 {
2355 self.bits
2356 }
2357 }
2358 # [ doc = "Value of the field ALERT" ]
2359 pub struct AlertR {
2360 bits: u8,
2361 }
2362 impl AlertR {
2363 # [ doc = r" Value of the field as raw bits" ]
2364 pub fn bits(&self) -> u8 {
2365 self.bits
2366 }
2367 }
2368 # [ doc = "Value of the field TIMEOUT" ]
2369 pub struct TimeoutR {
2370 bits: u8,
2371 }
2372 impl TimeoutR {
2373 # [ doc = r" Value of the field as raw bits" ]
2374 pub fn bits(&self) -> u8 {
2375 self.bits
2376 }
2377 }
2378 # [ doc = "Value of the field PECERR" ]
2379 pub struct PecerrR {
2380 bits: u8,
2381 }
2382 impl PecerrR {
2383 # [ doc = r" Value of the field as raw bits" ]
2384 pub fn bits(&self) -> u8 {
2385 self.bits
2386 }
2387 }
2388 # [ doc = "Value of the field OVR" ]
2389 pub struct OvrR {
2390 bits: u8,
2391 }
2392 impl OvrR {
2393 # [ doc = r" Value of the field as raw bits" ]
2394 pub fn bits(&self) -> u8 {
2395 self.bits
2396 }
2397 }
2398 # [ doc = "Value of the field ARLO" ]
2399 pub struct ArloR {
2400 bits: u8,
2401 }
2402 impl ArloR {
2403 # [ doc = r" Value of the field as raw bits" ]
2404 pub fn bits(&self) -> u8 {
2405 self.bits
2406 }
2407 }
2408 # [ doc = "Value of the field BERR" ]
2409 pub struct BerrR {
2410 bits: u8,
2411 }
2412 impl BerrR {
2413 # [ doc = r" Value of the field as raw bits" ]
2414 pub fn bits(&self) -> u8 {
2415 self.bits
2416 }
2417 }
2418 # [ doc = "Value of the field TCR" ]
2419 pub struct TcrR {
2420 bits: u8,
2421 }
2422 impl TcrR {
2423 # [ doc = r" Value of the field as raw bits" ]
2424 pub fn bits(&self) -> u8 {
2425 self.bits
2426 }
2427 }
2428 # [ doc = "Value of the field TC" ]
2429 pub struct TcR {
2430 bits: u8,
2431 }
2432 impl TcR {
2433 # [ doc = r" Value of the field as raw bits" ]
2434 pub fn bits(&self) -> u8 {
2435 self.bits
2436 }
2437 }
2438 # [ doc = "Value of the field STOPF" ]
2439 pub struct StopfR {
2440 bits: u8,
2441 }
2442 impl StopfR {
2443 # [ doc = r" Value of the field as raw bits" ]
2444 pub fn bits(&self) -> u8 {
2445 self.bits
2446 }
2447 }
2448 # [ doc = "Value of the field NACKF" ]
2449 pub struct NackfR {
2450 bits: u8,
2451 }
2452 impl NackfR {
2453 # [ doc = r" Value of the field as raw bits" ]
2454 pub fn bits(&self) -> u8 {
2455 self.bits
2456 }
2457 }
2458 # [ doc = "Value of the field ADDR" ]
2459 pub struct AddrR {
2460 bits: u8,
2461 }
2462 impl AddrR {
2463 # [ doc = r" Value of the field as raw bits" ]
2464 pub fn bits(&self) -> u8 {
2465 self.bits
2466 }
2467 }
2468 # [ doc = "Value of the field RXNE" ]
2469 pub struct RxneR {
2470 bits: u8,
2471 }
2472 impl RxneR {
2473 # [ doc = r" Value of the field as raw bits" ]
2474 pub fn bits(&self) -> u8 {
2475 self.bits
2476 }
2477 }
2478 # [ doc = "Value of the field TXIS" ]
2479 pub struct TxisR {
2480 bits: u8,
2481 }
2482 impl TxisR {
2483 # [ doc = r" Value of the field as raw bits" ]
2484 pub fn bits(&self) -> u8 {
2485 self.bits
2486 }
2487 }
2488 # [ doc = "Value of the field TXE" ]
2489 pub struct TxeR {
2490 bits: u8,
2491 }
2492 impl TxeR {
2493 # [ doc = r" Value of the field as raw bits" ]
2494 pub fn bits(&self) -> u8 {
2495 self.bits
2496 }
2497 }
2498 # [ doc = r" Proxy" ]
2499 pub struct _TxisW<'a> {
2500 register: &'a mut W,
2501 }
2502 impl<'a> _TxisW<'a> {
2503 # [ doc = r" Writes raw `bits` to the field" ]
2504 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2505 const MASK: u8 = 1;
2506 const OFFSET: u8 = 1;
2507 self.register.bits &= !((MASK as u32) << OFFSET);
2508 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2509 self.register
2510 }
2511 }
2512 # [ doc = r" Proxy" ]
2513 pub struct _TxeW<'a> {
2514 register: &'a mut W,
2515 }
2516 impl<'a> _TxeW<'a> {
2517 # [ doc = r" Writes raw `bits` to the field" ]
2518 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2519 const MASK: u8 = 1;
2520 const OFFSET: u8 = 0;
2521 self.register.bits &= !((MASK as u32) << OFFSET);
2522 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2523 self.register
2524 }
2525 }
2526 impl R {
2527 # [ doc = r" Value of the register as raw bits" ]
2528 pub fn bits(&self) -> u32 {
2529 self.bits
2530 }
2531 fn _addcode(&self) -> u8 {
2532 const MASK: u8 = 127;
2533 const OFFSET: u8 = 17;
2534 ((self.bits >> OFFSET) & MASK as u32) as u8
2535 }
2536 # [ doc = "Bits 17:23 - Address match code (Slave mode)" ]
2537 pub fn addcode(&self) -> AddcodeR {
2538 AddcodeR { bits: self._addcode() }
2539 }
2540 fn _dir(&self) -> u8 {
2541 const MASK: u8 = 1;
2542 const OFFSET: u8 = 16;
2543 ((self.bits >> OFFSET) & MASK as u32) as u8
2544 }
2545 # [ doc = "Bit 16 - Transfer direction (Slave mode)" ]
2546 pub fn dir(&self) -> DirR {
2547 DirR { bits: self._dir() }
2548 }
2549 fn _busy(&self) -> u8 {
2550 const MASK: u8 = 1;
2551 const OFFSET: u8 = 15;
2552 ((self.bits >> OFFSET) & MASK as u32) as u8
2553 }
2554 # [ doc = "Bit 15 - Bus busy" ]
2555 pub fn busy(&self) -> BusyR {
2556 BusyR { bits: self._busy() }
2557 }
2558 fn _alert(&self) -> u8 {
2559 const MASK: u8 = 1;
2560 const OFFSET: u8 = 13;
2561 ((self.bits >> OFFSET) & MASK as u32) as u8
2562 }
2563 # [ doc = "Bit 13 - SMBus alert" ]
2564 pub fn alert(&self) -> AlertR {
2565 AlertR { bits: self._alert() }
2566 }
2567 fn _timeout(&self) -> u8 {
2568 const MASK: u8 = 1;
2569 const OFFSET: u8 = 12;
2570 ((self.bits >> OFFSET) & MASK as u32) as u8
2571 }
2572 # [ doc = "Bit 12 - Timeout or t_low detection flag" ]
2573 pub fn timeout(&self) -> TimeoutR {
2574 TimeoutR { bits: self._timeout() }
2575 }
2576 fn _pecerr(&self) -> u8 {
2577 const MASK: u8 = 1;
2578 const OFFSET: u8 = 11;
2579 ((self.bits >> OFFSET) & MASK as u32) as u8
2580 }
2581 # [ doc = "Bit 11 - PEC Error in reception" ]
2582 pub fn pecerr(&self) -> PecerrR {
2583 PecerrR { bits: self._pecerr() }
2584 }
2585 fn _ovr(&self) -> u8 {
2586 const MASK: u8 = 1;
2587 const OFFSET: u8 = 10;
2588 ((self.bits >> OFFSET) & MASK as u32) as u8
2589 }
2590 # [ doc = "Bit 10 - Overrun/Underrun (slave mode)" ]
2591 pub fn ovr(&self) -> OvrR {
2592 OvrR { bits: self._ovr() }
2593 }
2594 fn _arlo(&self) -> u8 {
2595 const MASK: u8 = 1;
2596 const OFFSET: u8 = 9;
2597 ((self.bits >> OFFSET) & MASK as u32) as u8
2598 }
2599 # [ doc = "Bit 9 - Arbitration lost" ]
2600 pub fn arlo(&self) -> ArloR {
2601 ArloR { bits: self._arlo() }
2602 }
2603 fn _berr(&self) -> u8 {
2604 const MASK: u8 = 1;
2605 const OFFSET: u8 = 8;
2606 ((self.bits >> OFFSET) & MASK as u32) as u8
2607 }
2608 # [ doc = "Bit 8 - Bus error" ]
2609 pub fn berr(&self) -> BerrR {
2610 BerrR { bits: self._berr() }
2611 }
2612 fn _tcr(&self) -> u8 {
2613 const MASK: u8 = 1;
2614 const OFFSET: u8 = 7;
2615 ((self.bits >> OFFSET) & MASK as u32) as u8
2616 }
2617 # [ doc = "Bit 7 - Transfer Complete Reload" ]
2618 pub fn tcr(&self) -> TcrR {
2619 TcrR { bits: self._tcr() }
2620 }
2621 fn _tc(&self) -> u8 {
2622 const MASK: u8 = 1;
2623 const OFFSET: u8 = 6;
2624 ((self.bits >> OFFSET) & MASK as u32) as u8
2625 }
2626 # [ doc = "Bit 6 - Transfer Complete (master mode)" ]
2627 pub fn tc(&self) -> TcR {
2628 TcR { bits: self._tc() }
2629 }
2630 fn _stopf(&self) -> u8 {
2631 const MASK: u8 = 1;
2632 const OFFSET: u8 = 5;
2633 ((self.bits >> OFFSET) & MASK as u32) as u8
2634 }
2635 # [ doc = "Bit 5 - Stop detection flag" ]
2636 pub fn stopf(&self) -> StopfR {
2637 StopfR { bits: self._stopf() }
2638 }
2639 fn _nackf(&self) -> u8 {
2640 const MASK: u8 = 1;
2641 const OFFSET: u8 = 4;
2642 ((self.bits >> OFFSET) & MASK as u32) as u8
2643 }
2644 # [ doc = "Bit 4 - Not acknowledge received flag" ]
2645 pub fn nackf(&self) -> NackfR {
2646 NackfR { bits: self._nackf() }
2647 }
2648 fn _addr(&self) -> u8 {
2649 const MASK: u8 = 1;
2650 const OFFSET: u8 = 3;
2651 ((self.bits >> OFFSET) & MASK as u32) as u8
2652 }
2653 # [ doc = "Bit 3 - Address matched (slave mode)" ]
2654 pub fn addr(&self) -> AddrR {
2655 AddrR { bits: self._addr() }
2656 }
2657 fn _rxne(&self) -> u8 {
2658 const MASK: u8 = 1;
2659 const OFFSET: u8 = 2;
2660 ((self.bits >> OFFSET) & MASK as u32) as u8
2661 }
2662 # [ doc = "Bit 2 - Receive data register not empty (receivers)" ]
2663 pub fn rxne(&self) -> RxneR {
2664 RxneR { bits: self._rxne() }
2665 }
2666 fn _txis(&self) -> u8 {
2667 const MASK: u8 = 1;
2668 const OFFSET: u8 = 1;
2669 ((self.bits >> OFFSET) & MASK as u32) as u8
2670 }
2671 # [ doc = "Bit 1 - Transmit interrupt status (transmitters)" ]
2672 pub fn txis(&self) -> TxisR {
2673 TxisR { bits: self._txis() }
2674 }
2675 fn _txe(&self) -> u8 {
2676 const MASK: u8 = 1;
2677 const OFFSET: u8 = 0;
2678 ((self.bits >> OFFSET) & MASK as u32) as u8
2679 }
2680 # [ doc = "Bit 0 - Transmit data register empty (transmitters)" ]
2681 pub fn txe(&self) -> TxeR {
2682 TxeR { bits: self._txe() }
2683 }
2684 }
2685 impl W {
2686 # [ doc = r" Reset value of the register" ]
2687 pub fn reset_value() -> W {
2688 W { bits: 1 }
2689 }
2690 # [ doc = r" Writes raw `bits` to the register" ]
2691 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
2692 self.bits = bits;
2693 self
2694 }
2695 # [ doc = "Bit 1 - Transmit interrupt status (transmitters)" ]
2696 pub fn txis(&mut self) -> _TxisW {
2697 _TxisW { register: self }
2698 }
2699 # [ doc = "Bit 0 - Transmit data register empty (transmitters)" ]
2700 pub fn txe(&mut self) -> _TxeW {
2701 _TxeW { register: self }
2702 }
2703 }
2704}
2705
2706# [ doc = "Interrupt clear register" ]
2707# [ repr ( C ) ]
2708pub struct Icr {
2709 register: ::volatile_register::WO<u32>,
2710}
2711
2712# [ doc = "Interrupt clear register" ]
2713pub mod icr {
2714 # [ doc = r" Value to write to the register" ]
2715 pub struct W {
2716 bits: u32,
2717 }
2718 impl super::Icr {
2719 # [ doc = r" Writes to the register" ]
2720 pub fn write<F>(&mut self, f: F)
2721 where F: FnOnce(&mut W) -> &mut W
2722 {
2723 let mut w = W::reset_value();
2724 f(&mut w);
2725 self.register.write(w.bits);
2726 }
2727 }
2728 # [ doc = r" Proxy" ]
2729 pub struct _AlertcfW<'a> {
2730 register: &'a mut W,
2731 }
2732 impl<'a> _AlertcfW<'a> {
2733 # [ doc = r" Writes raw `bits` to the field" ]
2734 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2735 const MASK: u8 = 1;
2736 const OFFSET: u8 = 13;
2737 self.register.bits &= !((MASK as u32) << OFFSET);
2738 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2739 self.register
2740 }
2741 }
2742 # [ doc = r" Proxy" ]
2743 pub struct _TimoutcfW<'a> {
2744 register: &'a mut W,
2745 }
2746 impl<'a> _TimoutcfW<'a> {
2747 # [ doc = r" Writes raw `bits` to the field" ]
2748 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2749 const MASK: u8 = 1;
2750 const OFFSET: u8 = 12;
2751 self.register.bits &= !((MASK as u32) << OFFSET);
2752 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2753 self.register
2754 }
2755 }
2756 # [ doc = r" Proxy" ]
2757 pub struct _PeccfW<'a> {
2758 register: &'a mut W,
2759 }
2760 impl<'a> _PeccfW<'a> {
2761 # [ doc = r" Writes raw `bits` to the field" ]
2762 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2763 const MASK: u8 = 1;
2764 const OFFSET: u8 = 11;
2765 self.register.bits &= !((MASK as u32) << OFFSET);
2766 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2767 self.register
2768 }
2769 }
2770 # [ doc = r" Proxy" ]
2771 pub struct _OvrcfW<'a> {
2772 register: &'a mut W,
2773 }
2774 impl<'a> _OvrcfW<'a> {
2775 # [ doc = r" Writes raw `bits` to the field" ]
2776 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2777 const MASK: u8 = 1;
2778 const OFFSET: u8 = 10;
2779 self.register.bits &= !((MASK as u32) << OFFSET);
2780 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2781 self.register
2782 }
2783 }
2784 # [ doc = r" Proxy" ]
2785 pub struct _ArlocfW<'a> {
2786 register: &'a mut W,
2787 }
2788 impl<'a> _ArlocfW<'a> {
2789 # [ doc = r" Writes raw `bits` to the field" ]
2790 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2791 const MASK: u8 = 1;
2792 const OFFSET: u8 = 9;
2793 self.register.bits &= !((MASK as u32) << OFFSET);
2794 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2795 self.register
2796 }
2797 }
2798 # [ doc = r" Proxy" ]
2799 pub struct _BerrcfW<'a> {
2800 register: &'a mut W,
2801 }
2802 impl<'a> _BerrcfW<'a> {
2803 # [ doc = r" Writes raw `bits` to the field" ]
2804 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2805 const MASK: u8 = 1;
2806 const OFFSET: u8 = 8;
2807 self.register.bits &= !((MASK as u32) << OFFSET);
2808 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2809 self.register
2810 }
2811 }
2812 # [ doc = r" Proxy" ]
2813 pub struct _StopcfW<'a> {
2814 register: &'a mut W,
2815 }
2816 impl<'a> _StopcfW<'a> {
2817 # [ doc = r" Writes raw `bits` to the field" ]
2818 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2819 const MASK: u8 = 1;
2820 const OFFSET: u8 = 5;
2821 self.register.bits &= !((MASK as u32) << OFFSET);
2822 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2823 self.register
2824 }
2825 }
2826 # [ doc = r" Proxy" ]
2827 pub struct _NackcfW<'a> {
2828 register: &'a mut W,
2829 }
2830 impl<'a> _NackcfW<'a> {
2831 # [ doc = r" Writes raw `bits` to the field" ]
2832 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2833 const MASK: u8 = 1;
2834 const OFFSET: u8 = 4;
2835 self.register.bits &= !((MASK as u32) << OFFSET);
2836 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2837 self.register
2838 }
2839 }
2840 # [ doc = r" Proxy" ]
2841 pub struct _AddrcfW<'a> {
2842 register: &'a mut W,
2843 }
2844 impl<'a> _AddrcfW<'a> {
2845 # [ doc = r" Writes raw `bits` to the field" ]
2846 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2847 const MASK: u8 = 1;
2848 const OFFSET: u8 = 3;
2849 self.register.bits &= !((MASK as u32) << OFFSET);
2850 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2851 self.register
2852 }
2853 }
2854 impl W {
2855 # [ doc = r" Reset value of the register" ]
2856 pub fn reset_value() -> W {
2857 W { bits: 0 }
2858 }
2859 # [ doc = r" Writes raw `bits` to the register" ]
2860 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
2861 self.bits = bits;
2862 self
2863 }
2864 # [ doc = "Bit 13 - Alert flag clear" ]
2865 pub fn alertcf(&mut self) -> _AlertcfW {
2866 _AlertcfW { register: self }
2867 }
2868 # [ doc = "Bit 12 - Timeout detection flag clear" ]
2869 pub fn timoutcf(&mut self) -> _TimoutcfW {
2870 _TimoutcfW { register: self }
2871 }
2872 # [ doc = "Bit 11 - PEC Error flag clear" ]
2873 pub fn peccf(&mut self) -> _PeccfW {
2874 _PeccfW { register: self }
2875 }
2876 # [ doc = "Bit 10 - Overrun/Underrun flag clear" ]
2877 pub fn ovrcf(&mut self) -> _OvrcfW {
2878 _OvrcfW { register: self }
2879 }
2880 # [ doc = "Bit 9 - Arbitration lost flag clear" ]
2881 pub fn arlocf(&mut self) -> _ArlocfW {
2882 _ArlocfW { register: self }
2883 }
2884 # [ doc = "Bit 8 - Bus error flag clear" ]
2885 pub fn berrcf(&mut self) -> _BerrcfW {
2886 _BerrcfW { register: self }
2887 }
2888 # [ doc = "Bit 5 - Stop detection flag clear" ]
2889 pub fn stopcf(&mut self) -> _StopcfW {
2890 _StopcfW { register: self }
2891 }
2892 # [ doc = "Bit 4 - Not Acknowledge flag clear" ]
2893 pub fn nackcf(&mut self) -> _NackcfW {
2894 _NackcfW { register: self }
2895 }
2896 # [ doc = "Bit 3 - Address Matched flag clear" ]
2897 pub fn addrcf(&mut self) -> _AddrcfW {
2898 _AddrcfW { register: self }
2899 }
2900 }
2901}
2902
2903# [ doc = "PEC register" ]
2904# [ repr ( C ) ]
2905pub struct Pecr {
2906 register: ::volatile_register::RO<u32>,
2907}
2908
2909# [ doc = "PEC register" ]
2910pub mod pecr {
2911 # [ doc = r" Value read from the register" ]
2912 pub struct R {
2913 bits: u32,
2914 }
2915 impl super::Pecr {
2916 # [ doc = r" Reads the contents of the register" ]
2917 pub fn read(&self) -> R {
2918 R { bits: self.register.read() }
2919 }
2920 }
2921 # [ doc = "Value of the field PEC" ]
2922 pub struct PecR {
2923 bits: u8,
2924 }
2925 impl PecR {
2926 # [ doc = r" Value of the field as raw bits" ]
2927 pub fn bits(&self) -> u8 {
2928 self.bits
2929 }
2930 }
2931 impl R {
2932 # [ doc = r" Value of the register as raw bits" ]
2933 pub fn bits(&self) -> u32 {
2934 self.bits
2935 }
2936 fn _pec(&self) -> u8 {
2937 const MASK: u8 = 255;
2938 const OFFSET: u8 = 0;
2939 ((self.bits >> OFFSET) & MASK as u32) as u8
2940 }
2941 # [ doc = "Bits 0:7 - Packet error checking register" ]
2942 pub fn pec(&self) -> PecR {
2943 PecR { bits: self._pec() }
2944 }
2945 }
2946}
2947
2948# [ doc = "Receive data register" ]
2949# [ repr ( C ) ]
2950pub struct Rxdr {
2951 register: ::volatile_register::RO<u32>,
2952}
2953
2954# [ doc = "Receive data register" ]
2955pub mod rxdr {
2956 # [ doc = r" Value read from the register" ]
2957 pub struct R {
2958 bits: u32,
2959 }
2960 impl super::Rxdr {
2961 # [ doc = r" Reads the contents of the register" ]
2962 pub fn read(&self) -> R {
2963 R { bits: self.register.read() }
2964 }
2965 }
2966 # [ doc = "Value of the field RXDATA" ]
2967 pub struct RxdataR {
2968 bits: u8,
2969 }
2970 impl RxdataR {
2971 # [ doc = r" Value of the field as raw bits" ]
2972 pub fn bits(&self) -> u8 {
2973 self.bits
2974 }
2975 }
2976 impl R {
2977 # [ doc = r" Value of the register as raw bits" ]
2978 pub fn bits(&self) -> u32 {
2979 self.bits
2980 }
2981 fn _rxdata(&self) -> u8 {
2982 const MASK: u8 = 255;
2983 const OFFSET: u8 = 0;
2984 ((self.bits >> OFFSET) & MASK as u32) as u8
2985 }
2986 # [ doc = "Bits 0:7 - 8-bit receive data" ]
2987 pub fn rxdata(&self) -> RxdataR {
2988 RxdataR { bits: self._rxdata() }
2989 }
2990 }
2991}
2992
2993# [ doc = "Transmit data register" ]
2994# [ repr ( C ) ]
2995pub struct Txdr {
2996 register: ::volatile_register::RW<u32>,
2997}
2998
2999# [ doc = "Transmit data register" ]
3000pub mod txdr {
3001 # [ doc = r" Value read from the register" ]
3002 pub struct R {
3003 bits: u32,
3004 }
3005 # [ doc = r" Value to write to the register" ]
3006 pub struct W {
3007 bits: u32,
3008 }
3009 impl super::Txdr {
3010 # [ doc = r" Modifies the contents of the register" ]
3011 pub fn modify<F>(&mut self, f: F)
3012 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
3013 {
3014 let bits = self.register.read();
3015 let r = R { bits: bits };
3016 let mut w = W { bits: bits };
3017 f(&r, &mut w);
3018 self.register.write(w.bits);
3019 }
3020 # [ doc = r" Reads the contents of the register" ]
3021 pub fn read(&self) -> R {
3022 R { bits: self.register.read() }
3023 }
3024 # [ doc = r" Writes to the register" ]
3025 pub fn write<F>(&mut self, f: F)
3026 where F: FnOnce(&mut W) -> &mut W
3027 {
3028 let mut w = W::reset_value();
3029 f(&mut w);
3030 self.register.write(w.bits);
3031 }
3032 }
3033 # [ doc = "Value of the field TXDATA" ]
3034 pub struct TxdataR {
3035 bits: u8,
3036 }
3037 impl TxdataR {
3038 # [ doc = r" Value of the field as raw bits" ]
3039 pub fn bits(&self) -> u8 {
3040 self.bits
3041 }
3042 }
3043 # [ doc = r" Proxy" ]
3044 pub struct _TxdataW<'a> {
3045 register: &'a mut W,
3046 }
3047 impl<'a> _TxdataW<'a> {
3048 # [ doc = r" Writes raw `bits` to the field" ]
3049 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3050 const MASK: u8 = 255;
3051 const OFFSET: u8 = 0;
3052 self.register.bits &= !((MASK as u32) << OFFSET);
3053 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3054 self.register
3055 }
3056 }
3057 impl R {
3058 # [ doc = r" Value of the register as raw bits" ]
3059 pub fn bits(&self) -> u32 {
3060 self.bits
3061 }
3062 fn _txdata(&self) -> u8 {
3063 const MASK: u8 = 255;
3064 const OFFSET: u8 = 0;
3065 ((self.bits >> OFFSET) & MASK as u32) as u8
3066 }
3067 # [ doc = "Bits 0:7 - 8-bit transmit data" ]
3068 pub fn txdata(&self) -> TxdataR {
3069 TxdataR { bits: self._txdata() }
3070 }
3071 }
3072 impl W {
3073 # [ doc = r" Reset value of the register" ]
3074 pub fn reset_value() -> W {
3075 W { bits: 0 }
3076 }
3077 # [ doc = r" Writes raw `bits` to the register" ]
3078 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
3079 self.bits = bits;
3080 self
3081 }
3082 # [ doc = "Bits 0:7 - 8-bit transmit data" ]
3083 pub fn txdata(&mut self) -> _TxdataW {
3084 _TxdataW { register: self }
3085 }
3086 }
3087}