1# ! [ doc = "Universal synchronous asynchronous receiver transmitter" ]
2# [ doc = r" Register block" ]
3# [ repr ( C ) ]
4pub struct Usart {
5 # [ doc = "0x00 - Control register 1" ]
6 pub cr1: Cr1,
7 # [ doc = "0x04 - Control register 2" ]
8 pub cr2: Cr2,
9 # [ doc = "0x08 - Control register 3" ]
10 pub cr3: Cr3,
11 # [ doc = "0x0c - Baud rate register" ]
12 pub brr: Brr,
13 # [ doc = "0x10 - Guard time and prescaler register" ]
14 pub gtpr: Gtpr,
15 # [ doc = "0x14 - Receiver timeout register" ]
16 pub rtor: Rtor,
17 # [ doc = "0x18 - Request register" ]
18 pub rqr: Rqr,
19 # [ doc = "0x1c - Interrupt & status register" ]
20 pub isr: Isr,
21 # [ doc = "0x20 - Interrupt flag clear register" ]
22 pub icr: Icr,
23 # [ doc = "0x24 - Receive data register" ]
24 pub rdr: Rdr,
25 # [ doc = "0x28 - Transmit data register" ]
26 pub tdr: Tdr,
27}
28
29# [ doc = "Control register 1" ]
30# [ repr ( C ) ]
31pub struct Cr1 {
32 register: ::volatile_register::RW<u32>,
33}
34
35# [ doc = "Control register 1" ]
36pub mod cr1 {
37 # [ doc = r" Value read from the register" ]
38 pub struct R {
39 bits: u32,
40 }
41 # [ doc = r" Value to write to the register" ]
42 pub struct W {
43 bits: u32,
44 }
45 impl super::Cr1 {
46 # [ doc = r" Modifies the contents of the register" ]
47 pub fn modify<F>(&mut self, f: F)
48 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
49 {
50 let bits = self.register.read();
51 let r = R { bits: bits };
52 let mut w = W { bits: bits };
53 f(&r, &mut w);
54 self.register.write(w.bits);
55 }
56 # [ doc = r" Reads the contents of the register" ]
57 pub fn read(&self) -> R {
58 R { bits: self.register.read() }
59 }
60 # [ doc = r" Writes to the register" ]
61 pub fn write<F>(&mut self, f: F)
62 where F: FnOnce(&mut W) -> &mut W
63 {
64 let mut w = W::reset_value();
65 f(&mut w);
66 self.register.write(w.bits);
67 }
68 }
69 # [ doc = "Value of the field UE" ]
70 pub struct UeR {
71 bits: u8,
72 }
73 impl UeR {
74 # [ doc = r" Value of the field as raw bits" ]
75 pub fn bits(&self) -> u8 {
76 self.bits
77 }
78 }
79 # [ doc = "Value of the field UESM" ]
80 pub struct UesmR {
81 bits: u8,
82 }
83 impl UesmR {
84 # [ doc = r" Value of the field as raw bits" ]
85 pub fn bits(&self) -> u8 {
86 self.bits
87 }
88 }
89 # [ doc = "Value of the field RE" ]
90 pub struct ReR {
91 bits: u8,
92 }
93 impl ReR {
94 # [ doc = r" Value of the field as raw bits" ]
95 pub fn bits(&self) -> u8 {
96 self.bits
97 }
98 }
99 # [ doc = "Value of the field TE" ]
100 pub struct TeR {
101 bits: u8,
102 }
103 impl TeR {
104 # [ doc = r" Value of the field as raw bits" ]
105 pub fn bits(&self) -> u8 {
106 self.bits
107 }
108 }
109 # [ doc = "Value of the field IDLEIE" ]
110 pub struct IdleieR {
111 bits: u8,
112 }
113 impl IdleieR {
114 # [ doc = r" Value of the field as raw bits" ]
115 pub fn bits(&self) -> u8 {
116 self.bits
117 }
118 }
119 # [ doc = "Value of the field RXNEIE" ]
120 pub struct RxneieR {
121 bits: u8,
122 }
123 impl RxneieR {
124 # [ doc = r" Value of the field as raw bits" ]
125 pub fn bits(&self) -> u8 {
126 self.bits
127 }
128 }
129 # [ doc = "Value of the field TCIE" ]
130 pub struct TcieR {
131 bits: u8,
132 }
133 impl TcieR {
134 # [ doc = r" Value of the field as raw bits" ]
135 pub fn bits(&self) -> u8 {
136 self.bits
137 }
138 }
139 # [ doc = "Value of the field TXEIE" ]
140 pub struct TxeieR {
141 bits: u8,
142 }
143 impl TxeieR {
144 # [ doc = r" Value of the field as raw bits" ]
145 pub fn bits(&self) -> u8 {
146 self.bits
147 }
148 }
149 # [ doc = "Value of the field PEIE" ]
150 pub struct PeieR {
151 bits: u8,
152 }
153 impl PeieR {
154 # [ doc = r" Value of the field as raw bits" ]
155 pub fn bits(&self) -> u8 {
156 self.bits
157 }
158 }
159 # [ doc = "Value of the field PS" ]
160 pub struct PsR {
161 bits: u8,
162 }
163 impl PsR {
164 # [ doc = r" Value of the field as raw bits" ]
165 pub fn bits(&self) -> u8 {
166 self.bits
167 }
168 }
169 # [ doc = "Value of the field PCE" ]
170 pub struct PceR {
171 bits: u8,
172 }
173 impl PceR {
174 # [ doc = r" Value of the field as raw bits" ]
175 pub fn bits(&self) -> u8 {
176 self.bits
177 }
178 }
179 # [ doc = "Value of the field WAKE" ]
180 pub struct WakeR {
181 bits: u8,
182 }
183 impl WakeR {
184 # [ doc = r" Value of the field as raw bits" ]
185 pub fn bits(&self) -> u8 {
186 self.bits
187 }
188 }
189 # [ doc = "Value of the field M" ]
190 pub struct MR {
191 bits: u8,
192 }
193 impl MR {
194 # [ doc = r" Value of the field as raw bits" ]
195 pub fn bits(&self) -> u8 {
196 self.bits
197 }
198 }
199 # [ doc = "Value of the field MME" ]
200 pub struct MmeR {
201 bits: u8,
202 }
203 impl MmeR {
204 # [ doc = r" Value of the field as raw bits" ]
205 pub fn bits(&self) -> u8 {
206 self.bits
207 }
208 }
209 # [ doc = "Value of the field CMIE" ]
210 pub struct CmieR {
211 bits: u8,
212 }
213 impl CmieR {
214 # [ doc = r" Value of the field as raw bits" ]
215 pub fn bits(&self) -> u8 {
216 self.bits
217 }
218 }
219 # [ doc = "Value of the field OVER8" ]
220 pub struct Over8R {
221 bits: u8,
222 }
223 impl Over8R {
224 # [ doc = r" Value of the field as raw bits" ]
225 pub fn bits(&self) -> u8 {
226 self.bits
227 }
228 }
229 # [ doc = "Value of the field DEDT" ]
230 pub struct DedtR {
231 bits: u8,
232 }
233 impl DedtR {
234 # [ doc = r" Value of the field as raw bits" ]
235 pub fn bits(&self) -> u8 {
236 self.bits
237 }
238 }
239 # [ doc = "Value of the field DEAT" ]
240 pub struct DeatR {
241 bits: u8,
242 }
243 impl DeatR {
244 # [ doc = r" Value of the field as raw bits" ]
245 pub fn bits(&self) -> u8 {
246 self.bits
247 }
248 }
249 # [ doc = "Value of the field RTOIE" ]
250 pub struct RtoieR {
251 bits: u8,
252 }
253 impl RtoieR {
254 # [ doc = r" Value of the field as raw bits" ]
255 pub fn bits(&self) -> u8 {
256 self.bits
257 }
258 }
259 # [ doc = "Value of the field EOBIE" ]
260 pub struct EobieR {
261 bits: u8,
262 }
263 impl EobieR {
264 # [ doc = r" Value of the field as raw bits" ]
265 pub fn bits(&self) -> u8 {
266 self.bits
267 }
268 }
269 # [ doc = "Value of the field M1" ]
270 pub struct M1R {
271 bits: u8,
272 }
273 impl M1R {
274 # [ doc = r" Value of the field as raw bits" ]
275 pub fn bits(&self) -> u8 {
276 self.bits
277 }
278 }
279 # [ doc = r" Proxy" ]
280 pub struct _UeW<'a> {
281 register: &'a mut W,
282 }
283 impl<'a> _UeW<'a> {
284 # [ doc = r" Writes raw `bits` to the field" ]
285 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
286 const MASK: u8 = 1;
287 const OFFSET: u8 = 0;
288 self.register.bits &= !((MASK as u32) << OFFSET);
289 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
290 self.register
291 }
292 }
293 # [ doc = r" Proxy" ]
294 pub struct _UesmW<'a> {
295 register: &'a mut W,
296 }
297 impl<'a> _UesmW<'a> {
298 # [ doc = r" Writes raw `bits` to the field" ]
299 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
300 const MASK: u8 = 1;
301 const OFFSET: u8 = 1;
302 self.register.bits &= !((MASK as u32) << OFFSET);
303 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
304 self.register
305 }
306 }
307 # [ doc = r" Proxy" ]
308 pub struct _ReW<'a> {
309 register: &'a mut W,
310 }
311 impl<'a> _ReW<'a> {
312 # [ doc = r" Writes raw `bits` to the field" ]
313 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
314 const MASK: u8 = 1;
315 const OFFSET: u8 = 2;
316 self.register.bits &= !((MASK as u32) << OFFSET);
317 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
318 self.register
319 }
320 }
321 # [ doc = r" Proxy" ]
322 pub struct _TeW<'a> {
323 register: &'a mut W,
324 }
325 impl<'a> _TeW<'a> {
326 # [ doc = r" Writes raw `bits` to the field" ]
327 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
328 const MASK: u8 = 1;
329 const OFFSET: u8 = 3;
330 self.register.bits &= !((MASK as u32) << OFFSET);
331 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
332 self.register
333 }
334 }
335 # [ doc = r" Proxy" ]
336 pub struct _IdleieW<'a> {
337 register: &'a mut W,
338 }
339 impl<'a> _IdleieW<'a> {
340 # [ doc = r" Writes raw `bits` to the field" ]
341 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
342 const MASK: u8 = 1;
343 const OFFSET: u8 = 4;
344 self.register.bits &= !((MASK as u32) << OFFSET);
345 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
346 self.register
347 }
348 }
349 # [ doc = r" Proxy" ]
350 pub struct _RxneieW<'a> {
351 register: &'a mut W,
352 }
353 impl<'a> _RxneieW<'a> {
354 # [ doc = r" Writes raw `bits` to the field" ]
355 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
356 const MASK: u8 = 1;
357 const OFFSET: u8 = 5;
358 self.register.bits &= !((MASK as u32) << OFFSET);
359 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
360 self.register
361 }
362 }
363 # [ doc = r" Proxy" ]
364 pub struct _TcieW<'a> {
365 register: &'a mut W,
366 }
367 impl<'a> _TcieW<'a> {
368 # [ doc = r" Writes raw `bits` to the field" ]
369 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
370 const MASK: u8 = 1;
371 const OFFSET: u8 = 6;
372 self.register.bits &= !((MASK as u32) << OFFSET);
373 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
374 self.register
375 }
376 }
377 # [ doc = r" Proxy" ]
378 pub struct _TxeieW<'a> {
379 register: &'a mut W,
380 }
381 impl<'a> _TxeieW<'a> {
382 # [ doc = r" Writes raw `bits` to the field" ]
383 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
384 const MASK: u8 = 1;
385 const OFFSET: u8 = 7;
386 self.register.bits &= !((MASK as u32) << OFFSET);
387 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
388 self.register
389 }
390 }
391 # [ doc = r" Proxy" ]
392 pub struct _PeieW<'a> {
393 register: &'a mut W,
394 }
395 impl<'a> _PeieW<'a> {
396 # [ doc = r" Writes raw `bits` to the field" ]
397 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
398 const MASK: u8 = 1;
399 const OFFSET: u8 = 8;
400 self.register.bits &= !((MASK as u32) << OFFSET);
401 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
402 self.register
403 }
404 }
405 # [ doc = r" Proxy" ]
406 pub struct _PsW<'a> {
407 register: &'a mut W,
408 }
409 impl<'a> _PsW<'a> {
410 # [ doc = r" Writes raw `bits` to the field" ]
411 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
412 const MASK: u8 = 1;
413 const OFFSET: u8 = 9;
414 self.register.bits &= !((MASK as u32) << OFFSET);
415 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
416 self.register
417 }
418 }
419 # [ doc = r" Proxy" ]
420 pub struct _PceW<'a> {
421 register: &'a mut W,
422 }
423 impl<'a> _PceW<'a> {
424 # [ doc = r" Writes raw `bits` to the field" ]
425 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
426 const MASK: u8 = 1;
427 const OFFSET: u8 = 10;
428 self.register.bits &= !((MASK as u32) << OFFSET);
429 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
430 self.register
431 }
432 }
433 # [ doc = r" Proxy" ]
434 pub struct _WakeW<'a> {
435 register: &'a mut W,
436 }
437 impl<'a> _WakeW<'a> {
438 # [ doc = r" Writes raw `bits` to the field" ]
439 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
440 const MASK: u8 = 1;
441 const OFFSET: u8 = 11;
442 self.register.bits &= !((MASK as u32) << OFFSET);
443 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
444 self.register
445 }
446 }
447 # [ doc = r" Proxy" ]
448 pub struct _MW<'a> {
449 register: &'a mut W,
450 }
451 impl<'a> _MW<'a> {
452 # [ doc = r" Writes raw `bits` to the field" ]
453 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
454 const MASK: u8 = 1;
455 const OFFSET: u8 = 12;
456 self.register.bits &= !((MASK as u32) << OFFSET);
457 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
458 self.register
459 }
460 }
461 # [ doc = r" Proxy" ]
462 pub struct _MmeW<'a> {
463 register: &'a mut W,
464 }
465 impl<'a> _MmeW<'a> {
466 # [ doc = r" Writes raw `bits` to the field" ]
467 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
468 const MASK: u8 = 1;
469 const OFFSET: u8 = 13;
470 self.register.bits &= !((MASK as u32) << OFFSET);
471 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
472 self.register
473 }
474 }
475 # [ doc = r" Proxy" ]
476 pub struct _CmieW<'a> {
477 register: &'a mut W,
478 }
479 impl<'a> _CmieW<'a> {
480 # [ doc = r" Writes raw `bits` to the field" ]
481 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
482 const MASK: u8 = 1;
483 const OFFSET: u8 = 14;
484 self.register.bits &= !((MASK as u32) << OFFSET);
485 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
486 self.register
487 }
488 }
489 # [ doc = r" Proxy" ]
490 pub struct _Over8W<'a> {
491 register: &'a mut W,
492 }
493 impl<'a> _Over8W<'a> {
494 # [ doc = r" Writes raw `bits` to the field" ]
495 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
496 const MASK: u8 = 1;
497 const OFFSET: u8 = 15;
498 self.register.bits &= !((MASK as u32) << OFFSET);
499 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
500 self.register
501 }
502 }
503 # [ doc = r" Proxy" ]
504 pub struct _DedtW<'a> {
505 register: &'a mut W,
506 }
507 impl<'a> _DedtW<'a> {
508 # [ doc = r" Writes raw `bits` to the field" ]
509 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
510 const MASK: u8 = 31;
511 const OFFSET: u8 = 16;
512 self.register.bits &= !((MASK as u32) << OFFSET);
513 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
514 self.register
515 }
516 }
517 # [ doc = r" Proxy" ]
518 pub struct _DeatW<'a> {
519 register: &'a mut W,
520 }
521 impl<'a> _DeatW<'a> {
522 # [ doc = r" Writes raw `bits` to the field" ]
523 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
524 const MASK: u8 = 31;
525 const OFFSET: u8 = 21;
526 self.register.bits &= !((MASK as u32) << OFFSET);
527 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
528 self.register
529 }
530 }
531 # [ doc = r" Proxy" ]
532 pub struct _RtoieW<'a> {
533 register: &'a mut W,
534 }
535 impl<'a> _RtoieW<'a> {
536 # [ doc = r" Writes raw `bits` to the field" ]
537 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
538 const MASK: u8 = 1;
539 const OFFSET: u8 = 26;
540 self.register.bits &= !((MASK as u32) << OFFSET);
541 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
542 self.register
543 }
544 }
545 # [ doc = r" Proxy" ]
546 pub struct _EobieW<'a> {
547 register: &'a mut W,
548 }
549 impl<'a> _EobieW<'a> {
550 # [ doc = r" Writes raw `bits` to the field" ]
551 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
552 const MASK: u8 = 1;
553 const OFFSET: u8 = 27;
554 self.register.bits &= !((MASK as u32) << OFFSET);
555 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
556 self.register
557 }
558 }
559 # [ doc = r" Proxy" ]
560 pub struct _M1W<'a> {
561 register: &'a mut W,
562 }
563 impl<'a> _M1W<'a> {
564 # [ doc = r" Writes raw `bits` to the field" ]
565 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
566 const MASK: u8 = 1;
567 const OFFSET: u8 = 28;
568 self.register.bits &= !((MASK as u32) << OFFSET);
569 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
570 self.register
571 }
572 }
573 impl R {
574 # [ doc = r" Value of the register as raw bits" ]
575 pub fn bits(&self) -> u32 {
576 self.bits
577 }
578 fn _ue(&self) -> u8 {
579 const MASK: u8 = 1;
580 const OFFSET: u8 = 0;
581 ((self.bits >> OFFSET) & MASK as u32) as u8
582 }
583 # [ doc = "Bit 0 - USART enable" ]
584 pub fn ue(&self) -> UeR {
585 UeR { bits: self._ue() }
586 }
587 fn _uesm(&self) -> u8 {
588 const MASK: u8 = 1;
589 const OFFSET: u8 = 1;
590 ((self.bits >> OFFSET) & MASK as u32) as u8
591 }
592 # [ doc = "Bit 1 - USART enable in Stop mode" ]
593 pub fn uesm(&self) -> UesmR {
594 UesmR { bits: self._uesm() }
595 }
596 fn _re(&self) -> u8 {
597 const MASK: u8 = 1;
598 const OFFSET: u8 = 2;
599 ((self.bits >> OFFSET) & MASK as u32) as u8
600 }
601 # [ doc = "Bit 2 - Receiver enable" ]
602 pub fn re(&self) -> ReR {
603 ReR { bits: self._re() }
604 }
605 fn _te(&self) -> u8 {
606 const MASK: u8 = 1;
607 const OFFSET: u8 = 3;
608 ((self.bits >> OFFSET) & MASK as u32) as u8
609 }
610 # [ doc = "Bit 3 - Transmitter enable" ]
611 pub fn te(&self) -> TeR {
612 TeR { bits: self._te() }
613 }
614 fn _idleie(&self) -> u8 {
615 const MASK: u8 = 1;
616 const OFFSET: u8 = 4;
617 ((self.bits >> OFFSET) & MASK as u32) as u8
618 }
619 # [ doc = "Bit 4 - IDLE interrupt enable" ]
620 pub fn idleie(&self) -> IdleieR {
621 IdleieR { bits: self._idleie() }
622 }
623 fn _rxneie(&self) -> u8 {
624 const MASK: u8 = 1;
625 const OFFSET: u8 = 5;
626 ((self.bits >> OFFSET) & MASK as u32) as u8
627 }
628 # [ doc = "Bit 5 - RXNE interrupt enable" ]
629 pub fn rxneie(&self) -> RxneieR {
630 RxneieR { bits: self._rxneie() }
631 }
632 fn _tcie(&self) -> u8 {
633 const MASK: u8 = 1;
634 const OFFSET: u8 = 6;
635 ((self.bits >> OFFSET) & MASK as u32) as u8
636 }
637 # [ doc = "Bit 6 - Transmission complete interrupt enable" ]
638 pub fn tcie(&self) -> TcieR {
639 TcieR { bits: self._tcie() }
640 }
641 fn _txeie(&self) -> u8 {
642 const MASK: u8 = 1;
643 const OFFSET: u8 = 7;
644 ((self.bits >> OFFSET) & MASK as u32) as u8
645 }
646 # [ doc = "Bit 7 - interrupt enable" ]
647 pub fn txeie(&self) -> TxeieR {
648 TxeieR { bits: self._txeie() }
649 }
650 fn _peie(&self) -> u8 {
651 const MASK: u8 = 1;
652 const OFFSET: u8 = 8;
653 ((self.bits >> OFFSET) & MASK as u32) as u8
654 }
655 # [ doc = "Bit 8 - PE interrupt enable" ]
656 pub fn peie(&self) -> PeieR {
657 PeieR { bits: self._peie() }
658 }
659 fn _ps(&self) -> u8 {
660 const MASK: u8 = 1;
661 const OFFSET: u8 = 9;
662 ((self.bits >> OFFSET) & MASK as u32) as u8
663 }
664 # [ doc = "Bit 9 - Parity selection" ]
665 pub fn ps(&self) -> PsR {
666 PsR { bits: self._ps() }
667 }
668 fn _pce(&self) -> u8 {
669 const MASK: u8 = 1;
670 const OFFSET: u8 = 10;
671 ((self.bits >> OFFSET) & MASK as u32) as u8
672 }
673 # [ doc = "Bit 10 - Parity control enable" ]
674 pub fn pce(&self) -> PceR {
675 PceR { bits: self._pce() }
676 }
677 fn _wake(&self) -> u8 {
678 const MASK: u8 = 1;
679 const OFFSET: u8 = 11;
680 ((self.bits >> OFFSET) & MASK as u32) as u8
681 }
682 # [ doc = "Bit 11 - Receiver wakeup method" ]
683 pub fn wake(&self) -> WakeR {
684 WakeR { bits: self._wake() }
685 }
686 fn _m(&self) -> u8 {
687 const MASK: u8 = 1;
688 const OFFSET: u8 = 12;
689 ((self.bits >> OFFSET) & MASK as u32) as u8
690 }
691 # [ doc = "Bit 12 - Word length" ]
692 pub fn m(&self) -> MR {
693 MR { bits: self._m() }
694 }
695 fn _mme(&self) -> u8 {
696 const MASK: u8 = 1;
697 const OFFSET: u8 = 13;
698 ((self.bits >> OFFSET) & MASK as u32) as u8
699 }
700 # [ doc = "Bit 13 - Mute mode enable" ]
701 pub fn mme(&self) -> MmeR {
702 MmeR { bits: self._mme() }
703 }
704 fn _cmie(&self) -> u8 {
705 const MASK: u8 = 1;
706 const OFFSET: u8 = 14;
707 ((self.bits >> OFFSET) & MASK as u32) as u8
708 }
709 # [ doc = "Bit 14 - Character match interrupt enable" ]
710 pub fn cmie(&self) -> CmieR {
711 CmieR { bits: self._cmie() }
712 }
713 fn _over8(&self) -> u8 {
714 const MASK: u8 = 1;
715 const OFFSET: u8 = 15;
716 ((self.bits >> OFFSET) & MASK as u32) as u8
717 }
718 # [ doc = "Bit 15 - Oversampling mode" ]
719 pub fn over8(&self) -> Over8R {
720 Over8R { bits: self._over8() }
721 }
722 fn _dedt(&self) -> u8 {
723 const MASK: u8 = 31;
724 const OFFSET: u8 = 16;
725 ((self.bits >> OFFSET) & MASK as u32) as u8
726 }
727 # [ doc = "Bits 16:20 - Driver Enable deassertion time" ]
728 pub fn dedt(&self) -> DedtR {
729 DedtR { bits: self._dedt() }
730 }
731 fn _deat(&self) -> u8 {
732 const MASK: u8 = 31;
733 const OFFSET: u8 = 21;
734 ((self.bits >> OFFSET) & MASK as u32) as u8
735 }
736 # [ doc = "Bits 21:25 - Driver Enable assertion time" ]
737 pub fn deat(&self) -> DeatR {
738 DeatR { bits: self._deat() }
739 }
740 fn _rtoie(&self) -> u8 {
741 const MASK: u8 = 1;
742 const OFFSET: u8 = 26;
743 ((self.bits >> OFFSET) & MASK as u32) as u8
744 }
745 # [ doc = "Bit 26 - Receiver timeout interrupt enable" ]
746 pub fn rtoie(&self) -> RtoieR {
747 RtoieR { bits: self._rtoie() }
748 }
749 fn _eobie(&self) -> u8 {
750 const MASK: u8 = 1;
751 const OFFSET: u8 = 27;
752 ((self.bits >> OFFSET) & MASK as u32) as u8
753 }
754 # [ doc = "Bit 27 - End of Block interrupt enable" ]
755 pub fn eobie(&self) -> EobieR {
756 EobieR { bits: self._eobie() }
757 }
758 fn _m1(&self) -> u8 {
759 const MASK: u8 = 1;
760 const OFFSET: u8 = 28;
761 ((self.bits >> OFFSET) & MASK as u32) as u8
762 }
763 # [ doc = "Bit 28 - Word length" ]
764 pub fn m1(&self) -> M1R {
765 M1R { bits: self._m1() }
766 }
767 }
768 impl W {
769 # [ doc = r" Reset value of the register" ]
770 pub fn reset_value() -> W {
771 W { bits: 0 }
772 }
773 # [ doc = r" Writes raw `bits` to the register" ]
774 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
775 self.bits = bits;
776 self
777 }
778 # [ doc = "Bit 0 - USART enable" ]
779 pub fn ue(&mut self) -> _UeW {
780 _UeW { register: self }
781 }
782 # [ doc = "Bit 1 - USART enable in Stop mode" ]
783 pub fn uesm(&mut self) -> _UesmW {
784 _UesmW { register: self }
785 }
786 # [ doc = "Bit 2 - Receiver enable" ]
787 pub fn re(&mut self) -> _ReW {
788 _ReW { register: self }
789 }
790 # [ doc = "Bit 3 - Transmitter enable" ]
791 pub fn te(&mut self) -> _TeW {
792 _TeW { register: self }
793 }
794 # [ doc = "Bit 4 - IDLE interrupt enable" ]
795 pub fn idleie(&mut self) -> _IdleieW {
796 _IdleieW { register: self }
797 }
798 # [ doc = "Bit 5 - RXNE interrupt enable" ]
799 pub fn rxneie(&mut self) -> _RxneieW {
800 _RxneieW { register: self }
801 }
802 # [ doc = "Bit 6 - Transmission complete interrupt enable" ]
803 pub fn tcie(&mut self) -> _TcieW {
804 _TcieW { register: self }
805 }
806 # [ doc = "Bit 7 - interrupt enable" ]
807 pub fn txeie(&mut self) -> _TxeieW {
808 _TxeieW { register: self }
809 }
810 # [ doc = "Bit 8 - PE interrupt enable" ]
811 pub fn peie(&mut self) -> _PeieW {
812 _PeieW { register: self }
813 }
814 # [ doc = "Bit 9 - Parity selection" ]
815 pub fn ps(&mut self) -> _PsW {
816 _PsW { register: self }
817 }
818 # [ doc = "Bit 10 - Parity control enable" ]
819 pub fn pce(&mut self) -> _PceW {
820 _PceW { register: self }
821 }
822 # [ doc = "Bit 11 - Receiver wakeup method" ]
823 pub fn wake(&mut self) -> _WakeW {
824 _WakeW { register: self }
825 }
826 # [ doc = "Bit 12 - Word length" ]
827 pub fn m(&mut self) -> _MW {
828 _MW { register: self }
829 }
830 # [ doc = "Bit 13 - Mute mode enable" ]
831 pub fn mme(&mut self) -> _MmeW {
832 _MmeW { register: self }
833 }
834 # [ doc = "Bit 14 - Character match interrupt enable" ]
835 pub fn cmie(&mut self) -> _CmieW {
836 _CmieW { register: self }
837 }
838 # [ doc = "Bit 15 - Oversampling mode" ]
839 pub fn over8(&mut self) -> _Over8W {
840 _Over8W { register: self }
841 }
842 # [ doc = "Bits 16:20 - Driver Enable deassertion time" ]
843 pub fn dedt(&mut self) -> _DedtW {
844 _DedtW { register: self }
845 }
846 # [ doc = "Bits 21:25 - Driver Enable assertion time" ]
847 pub fn deat(&mut self) -> _DeatW {
848 _DeatW { register: self }
849 }
850 # [ doc = "Bit 26 - Receiver timeout interrupt enable" ]
851 pub fn rtoie(&mut self) -> _RtoieW {
852 _RtoieW { register: self }
853 }
854 # [ doc = "Bit 27 - End of Block interrupt enable" ]
855 pub fn eobie(&mut self) -> _EobieW {
856 _EobieW { register: self }
857 }
858 # [ doc = "Bit 28 - Word length" ]
859 pub fn m1(&mut self) -> _M1W {
860 _M1W { register: self }
861 }
862 }
863}
864
865# [ doc = "Control register 2" ]
866# [ repr ( C ) ]
867pub struct Cr2 {
868 register: ::volatile_register::RW<u32>,
869}
870
871# [ doc = "Control register 2" ]
872pub mod cr2 {
873 # [ doc = r" Value read from the register" ]
874 pub struct R {
875 bits: u32,
876 }
877 # [ doc = r" Value to write to the register" ]
878 pub struct W {
879 bits: u32,
880 }
881 impl super::Cr2 {
882 # [ doc = r" Modifies the contents of the register" ]
883 pub fn modify<F>(&mut self, f: F)
884 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
885 {
886 let bits = self.register.read();
887 let r = R { bits: bits };
888 let mut w = W { bits: bits };
889 f(&r, &mut w);
890 self.register.write(w.bits);
891 }
892 # [ doc = r" Reads the contents of the register" ]
893 pub fn read(&self) -> R {
894 R { bits: self.register.read() }
895 }
896 # [ doc = r" Writes to the register" ]
897 pub fn write<F>(&mut self, f: F)
898 where F: FnOnce(&mut W) -> &mut W
899 {
900 let mut w = W::reset_value();
901 f(&mut w);
902 self.register.write(w.bits);
903 }
904 }
905 # [ doc = "Value of the field ADD4" ]
906 pub struct Add4R {
907 bits: u8,
908 }
909 impl Add4R {
910 # [ doc = r" Value of the field as raw bits" ]
911 pub fn bits(&self) -> u8 {
912 self.bits
913 }
914 }
915 # [ doc = "Value of the field ADD0" ]
916 pub struct Add0R {
917 bits: u8,
918 }
919 impl Add0R {
920 # [ doc = r" Value of the field as raw bits" ]
921 pub fn bits(&self) -> u8 {
922 self.bits
923 }
924 }
925 # [ doc = "Value of the field RTOEN" ]
926 pub struct RtoenR {
927 bits: u8,
928 }
929 impl RtoenR {
930 # [ doc = r" Value of the field as raw bits" ]
931 pub fn bits(&self) -> u8 {
932 self.bits
933 }
934 }
935 # [ doc = "Value of the field ABRMOD" ]
936 pub struct AbrmodR {
937 bits: u8,
938 }
939 impl AbrmodR {
940 # [ doc = r" Value of the field as raw bits" ]
941 pub fn bits(&self) -> u8 {
942 self.bits
943 }
944 }
945 # [ doc = "Value of the field ABREN" ]
946 pub struct AbrenR {
947 bits: u8,
948 }
949 impl AbrenR {
950 # [ doc = r" Value of the field as raw bits" ]
951 pub fn bits(&self) -> u8 {
952 self.bits
953 }
954 }
955 # [ doc = "Value of the field MSBFIRST" ]
956 pub struct MsbfirstR {
957 bits: u8,
958 }
959 impl MsbfirstR {
960 # [ doc = r" Value of the field as raw bits" ]
961 pub fn bits(&self) -> u8 {
962 self.bits
963 }
964 }
965 # [ doc = "Value of the field DATAINV" ]
966 pub struct DatainvR {
967 bits: u8,
968 }
969 impl DatainvR {
970 # [ doc = r" Value of the field as raw bits" ]
971 pub fn bits(&self) -> u8 {
972 self.bits
973 }
974 }
975 # [ doc = "Value of the field TXINV" ]
976 pub struct TxinvR {
977 bits: u8,
978 }
979 impl TxinvR {
980 # [ doc = r" Value of the field as raw bits" ]
981 pub fn bits(&self) -> u8 {
982 self.bits
983 }
984 }
985 # [ doc = "Value of the field RXINV" ]
986 pub struct RxinvR {
987 bits: u8,
988 }
989 impl RxinvR {
990 # [ doc = r" Value of the field as raw bits" ]
991 pub fn bits(&self) -> u8 {
992 self.bits
993 }
994 }
995 # [ doc = "Value of the field SWAP" ]
996 pub struct SwapR {
997 bits: u8,
998 }
999 impl SwapR {
1000 # [ doc = r" Value of the field as raw bits" ]
1001 pub fn bits(&self) -> u8 {
1002 self.bits
1003 }
1004 }
1005 # [ doc = "Value of the field LINEN" ]
1006 pub struct LinenR {
1007 bits: u8,
1008 }
1009 impl LinenR {
1010 # [ doc = r" Value of the field as raw bits" ]
1011 pub fn bits(&self) -> u8 {
1012 self.bits
1013 }
1014 }
1015 # [ doc = "Value of the field STOP" ]
1016 pub struct StopR {
1017 bits: u8,
1018 }
1019 impl StopR {
1020 # [ doc = r" Value of the field as raw bits" ]
1021 pub fn bits(&self) -> u8 {
1022 self.bits
1023 }
1024 }
1025 # [ doc = "Value of the field CLKEN" ]
1026 pub struct ClkenR {
1027 bits: u8,
1028 }
1029 impl ClkenR {
1030 # [ doc = r" Value of the field as raw bits" ]
1031 pub fn bits(&self) -> u8 {
1032 self.bits
1033 }
1034 }
1035 # [ doc = "Value of the field CPOL" ]
1036 pub struct CpolR {
1037 bits: u8,
1038 }
1039 impl CpolR {
1040 # [ doc = r" Value of the field as raw bits" ]
1041 pub fn bits(&self) -> u8 {
1042 self.bits
1043 }
1044 }
1045 # [ doc = "Value of the field CPHA" ]
1046 pub struct CphaR {
1047 bits: u8,
1048 }
1049 impl CphaR {
1050 # [ doc = r" Value of the field as raw bits" ]
1051 pub fn bits(&self) -> u8 {
1052 self.bits
1053 }
1054 }
1055 # [ doc = "Value of the field LBCL" ]
1056 pub struct LbclR {
1057 bits: u8,
1058 }
1059 impl LbclR {
1060 # [ doc = r" Value of the field as raw bits" ]
1061 pub fn bits(&self) -> u8 {
1062 self.bits
1063 }
1064 }
1065 # [ doc = "Value of the field LBDIE" ]
1066 pub struct LbdieR {
1067 bits: u8,
1068 }
1069 impl LbdieR {
1070 # [ doc = r" Value of the field as raw bits" ]
1071 pub fn bits(&self) -> u8 {
1072 self.bits
1073 }
1074 }
1075 # [ doc = "Value of the field LBDL" ]
1076 pub struct LbdlR {
1077 bits: u8,
1078 }
1079 impl LbdlR {
1080 # [ doc = r" Value of the field as raw bits" ]
1081 pub fn bits(&self) -> u8 {
1082 self.bits
1083 }
1084 }
1085 # [ doc = "Value of the field ADDM7" ]
1086 pub struct Addm7R {
1087 bits: u8,
1088 }
1089 impl Addm7R {
1090 # [ doc = r" Value of the field as raw bits" ]
1091 pub fn bits(&self) -> u8 {
1092 self.bits
1093 }
1094 }
1095 # [ doc = r" Proxy" ]
1096 pub struct _Add4W<'a> {
1097 register: &'a mut W,
1098 }
1099 impl<'a> _Add4W<'a> {
1100 # [ doc = r" Writes raw `bits` to the field" ]
1101 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1102 const MASK: u8 = 15;
1103 const OFFSET: u8 = 28;
1104 self.register.bits &= !((MASK as u32) << OFFSET);
1105 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1106 self.register
1107 }
1108 }
1109 # [ doc = r" Proxy" ]
1110 pub struct _Add0W<'a> {
1111 register: &'a mut W,
1112 }
1113 impl<'a> _Add0W<'a> {
1114 # [ doc = r" Writes raw `bits` to the field" ]
1115 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1116 const MASK: u8 = 15;
1117 const OFFSET: u8 = 24;
1118 self.register.bits &= !((MASK as u32) << OFFSET);
1119 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1120 self.register
1121 }
1122 }
1123 # [ doc = r" Proxy" ]
1124 pub struct _RtoenW<'a> {
1125 register: &'a mut W,
1126 }
1127 impl<'a> _RtoenW<'a> {
1128 # [ doc = r" Writes raw `bits` to the field" ]
1129 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1130 const MASK: u8 = 1;
1131 const OFFSET: u8 = 23;
1132 self.register.bits &= !((MASK as u32) << OFFSET);
1133 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1134 self.register
1135 }
1136 }
1137 # [ doc = r" Proxy" ]
1138 pub struct _AbrmodW<'a> {
1139 register: &'a mut W,
1140 }
1141 impl<'a> _AbrmodW<'a> {
1142 # [ doc = r" Writes raw `bits` to the field" ]
1143 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1144 const MASK: u8 = 3;
1145 const OFFSET: u8 = 21;
1146 self.register.bits &= !((MASK as u32) << OFFSET);
1147 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1148 self.register
1149 }
1150 }
1151 # [ doc = r" Proxy" ]
1152 pub struct _AbrenW<'a> {
1153 register: &'a mut W,
1154 }
1155 impl<'a> _AbrenW<'a> {
1156 # [ doc = r" Writes raw `bits` to the field" ]
1157 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1158 const MASK: u8 = 1;
1159 const OFFSET: u8 = 20;
1160 self.register.bits &= !((MASK as u32) << OFFSET);
1161 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1162 self.register
1163 }
1164 }
1165 # [ doc = r" Proxy" ]
1166 pub struct _MsbfirstW<'a> {
1167 register: &'a mut W,
1168 }
1169 impl<'a> _MsbfirstW<'a> {
1170 # [ doc = r" Writes raw `bits` to the field" ]
1171 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1172 const MASK: u8 = 1;
1173 const OFFSET: u8 = 19;
1174 self.register.bits &= !((MASK as u32) << OFFSET);
1175 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1176 self.register
1177 }
1178 }
1179 # [ doc = r" Proxy" ]
1180 pub struct _DatainvW<'a> {
1181 register: &'a mut W,
1182 }
1183 impl<'a> _DatainvW<'a> {
1184 # [ doc = r" Writes raw `bits` to the field" ]
1185 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1186 const MASK: u8 = 1;
1187 const OFFSET: u8 = 18;
1188 self.register.bits &= !((MASK as u32) << OFFSET);
1189 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1190 self.register
1191 }
1192 }
1193 # [ doc = r" Proxy" ]
1194 pub struct _TxinvW<'a> {
1195 register: &'a mut W,
1196 }
1197 impl<'a> _TxinvW<'a> {
1198 # [ doc = r" Writes raw `bits` to the field" ]
1199 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1200 const MASK: u8 = 1;
1201 const OFFSET: u8 = 17;
1202 self.register.bits &= !((MASK as u32) << OFFSET);
1203 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1204 self.register
1205 }
1206 }
1207 # [ doc = r" Proxy" ]
1208 pub struct _RxinvW<'a> {
1209 register: &'a mut W,
1210 }
1211 impl<'a> _RxinvW<'a> {
1212 # [ doc = r" Writes raw `bits` to the field" ]
1213 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1214 const MASK: u8 = 1;
1215 const OFFSET: u8 = 16;
1216 self.register.bits &= !((MASK as u32) << OFFSET);
1217 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1218 self.register
1219 }
1220 }
1221 # [ doc = r" Proxy" ]
1222 pub struct _SwapW<'a> {
1223 register: &'a mut W,
1224 }
1225 impl<'a> _SwapW<'a> {
1226 # [ doc = r" Writes raw `bits` to the field" ]
1227 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1228 const MASK: u8 = 1;
1229 const OFFSET: u8 = 15;
1230 self.register.bits &= !((MASK as u32) << OFFSET);
1231 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1232 self.register
1233 }
1234 }
1235 # [ doc = r" Proxy" ]
1236 pub struct _LinenW<'a> {
1237 register: &'a mut W,
1238 }
1239 impl<'a> _LinenW<'a> {
1240 # [ doc = r" Writes raw `bits` to the field" ]
1241 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1242 const MASK: u8 = 1;
1243 const OFFSET: u8 = 14;
1244 self.register.bits &= !((MASK as u32) << OFFSET);
1245 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1246 self.register
1247 }
1248 }
1249 # [ doc = r" Proxy" ]
1250 pub struct _StopW<'a> {
1251 register: &'a mut W,
1252 }
1253 impl<'a> _StopW<'a> {
1254 # [ doc = r" Writes raw `bits` to the field" ]
1255 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1256 const MASK: u8 = 3;
1257 const OFFSET: u8 = 12;
1258 self.register.bits &= !((MASK as u32) << OFFSET);
1259 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1260 self.register
1261 }
1262 }
1263 # [ doc = r" Proxy" ]
1264 pub struct _ClkenW<'a> {
1265 register: &'a mut W,
1266 }
1267 impl<'a> _ClkenW<'a> {
1268 # [ doc = r" Writes raw `bits` to the field" ]
1269 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1270 const MASK: u8 = 1;
1271 const OFFSET: u8 = 11;
1272 self.register.bits &= !((MASK as u32) << OFFSET);
1273 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1274 self.register
1275 }
1276 }
1277 # [ doc = r" Proxy" ]
1278 pub struct _CpolW<'a> {
1279 register: &'a mut W,
1280 }
1281 impl<'a> _CpolW<'a> {
1282 # [ doc = r" Writes raw `bits` to the field" ]
1283 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1284 const MASK: u8 = 1;
1285 const OFFSET: u8 = 10;
1286 self.register.bits &= !((MASK as u32) << OFFSET);
1287 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1288 self.register
1289 }
1290 }
1291 # [ doc = r" Proxy" ]
1292 pub struct _CphaW<'a> {
1293 register: &'a mut W,
1294 }
1295 impl<'a> _CphaW<'a> {
1296 # [ doc = r" Writes raw `bits` to the field" ]
1297 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1298 const MASK: u8 = 1;
1299 const OFFSET: u8 = 9;
1300 self.register.bits &= !((MASK as u32) << OFFSET);
1301 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1302 self.register
1303 }
1304 }
1305 # [ doc = r" Proxy" ]
1306 pub struct _LbclW<'a> {
1307 register: &'a mut W,
1308 }
1309 impl<'a> _LbclW<'a> {
1310 # [ doc = r" Writes raw `bits` to the field" ]
1311 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1312 const MASK: u8 = 1;
1313 const OFFSET: u8 = 8;
1314 self.register.bits &= !((MASK as u32) << OFFSET);
1315 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1316 self.register
1317 }
1318 }
1319 # [ doc = r" Proxy" ]
1320 pub struct _LbdieW<'a> {
1321 register: &'a mut W,
1322 }
1323 impl<'a> _LbdieW<'a> {
1324 # [ doc = r" Writes raw `bits` to the field" ]
1325 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1326 const MASK: u8 = 1;
1327 const OFFSET: u8 = 6;
1328 self.register.bits &= !((MASK as u32) << OFFSET);
1329 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1330 self.register
1331 }
1332 }
1333 # [ doc = r" Proxy" ]
1334 pub struct _LbdlW<'a> {
1335 register: &'a mut W,
1336 }
1337 impl<'a> _LbdlW<'a> {
1338 # [ doc = r" Writes raw `bits` to the field" ]
1339 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1340 const MASK: u8 = 1;
1341 const OFFSET: u8 = 5;
1342 self.register.bits &= !((MASK as u32) << OFFSET);
1343 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1344 self.register
1345 }
1346 }
1347 # [ doc = r" Proxy" ]
1348 pub struct _Addm7W<'a> {
1349 register: &'a mut W,
1350 }
1351 impl<'a> _Addm7W<'a> {
1352 # [ doc = r" Writes raw `bits` to the field" ]
1353 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1354 const MASK: u8 = 1;
1355 const OFFSET: u8 = 4;
1356 self.register.bits &= !((MASK as u32) << OFFSET);
1357 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1358 self.register
1359 }
1360 }
1361 impl R {
1362 # [ doc = r" Value of the register as raw bits" ]
1363 pub fn bits(&self) -> u32 {
1364 self.bits
1365 }
1366 fn _add4(&self) -> u8 {
1367 const MASK: u8 = 15;
1368 const OFFSET: u8 = 28;
1369 ((self.bits >> OFFSET) & MASK as u32) as u8
1370 }
1371 # [ doc = "Bits 28:31 - Address of the USART node" ]
1372 pub fn add4(&self) -> Add4R {
1373 Add4R { bits: self._add4() }
1374 }
1375 fn _add0(&self) -> u8 {
1376 const MASK: u8 = 15;
1377 const OFFSET: u8 = 24;
1378 ((self.bits >> OFFSET) & MASK as u32) as u8
1379 }
1380 # [ doc = "Bits 24:27 - Address of the USART node" ]
1381 pub fn add0(&self) -> Add0R {
1382 Add0R { bits: self._add0() }
1383 }
1384 fn _rtoen(&self) -> u8 {
1385 const MASK: u8 = 1;
1386 const OFFSET: u8 = 23;
1387 ((self.bits >> OFFSET) & MASK as u32) as u8
1388 }
1389 # [ doc = "Bit 23 - Receiver timeout enable" ]
1390 pub fn rtoen(&self) -> RtoenR {
1391 RtoenR { bits: self._rtoen() }
1392 }
1393 fn _abrmod(&self) -> u8 {
1394 const MASK: u8 = 3;
1395 const OFFSET: u8 = 21;
1396 ((self.bits >> OFFSET) & MASK as u32) as u8
1397 }
1398 # [ doc = "Bits 21:22 - Auto baud rate mode" ]
1399 pub fn abrmod(&self) -> AbrmodR {
1400 AbrmodR { bits: self._abrmod() }
1401 }
1402 fn _abren(&self) -> u8 {
1403 const MASK: u8 = 1;
1404 const OFFSET: u8 = 20;
1405 ((self.bits >> OFFSET) & MASK as u32) as u8
1406 }
1407 # [ doc = "Bit 20 - Auto baud rate enable" ]
1408 pub fn abren(&self) -> AbrenR {
1409 AbrenR { bits: self._abren() }
1410 }
1411 fn _msbfirst(&self) -> u8 {
1412 const MASK: u8 = 1;
1413 const OFFSET: u8 = 19;
1414 ((self.bits >> OFFSET) & MASK as u32) as u8
1415 }
1416 # [ doc = "Bit 19 - Most significant bit first" ]
1417 pub fn msbfirst(&self) -> MsbfirstR {
1418 MsbfirstR { bits: self._msbfirst() }
1419 }
1420 fn _datainv(&self) -> u8 {
1421 const MASK: u8 = 1;
1422 const OFFSET: u8 = 18;
1423 ((self.bits >> OFFSET) & MASK as u32) as u8
1424 }
1425 # [ doc = "Bit 18 - Binary data inversion" ]
1426 pub fn datainv(&self) -> DatainvR {
1427 DatainvR { bits: self._datainv() }
1428 }
1429 fn _txinv(&self) -> u8 {
1430 const MASK: u8 = 1;
1431 const OFFSET: u8 = 17;
1432 ((self.bits >> OFFSET) & MASK as u32) as u8
1433 }
1434 # [ doc = "Bit 17 - TX pin active level inversion" ]
1435 pub fn txinv(&self) -> TxinvR {
1436 TxinvR { bits: self._txinv() }
1437 }
1438 fn _rxinv(&self) -> u8 {
1439 const MASK: u8 = 1;
1440 const OFFSET: u8 = 16;
1441 ((self.bits >> OFFSET) & MASK as u32) as u8
1442 }
1443 # [ doc = "Bit 16 - RX pin active level inversion" ]
1444 pub fn rxinv(&self) -> RxinvR {
1445 RxinvR { bits: self._rxinv() }
1446 }
1447 fn _swap(&self) -> u8 {
1448 const MASK: u8 = 1;
1449 const OFFSET: u8 = 15;
1450 ((self.bits >> OFFSET) & MASK as u32) as u8
1451 }
1452 # [ doc = "Bit 15 - Swap TX/RX pins" ]
1453 pub fn swap(&self) -> SwapR {
1454 SwapR { bits: self._swap() }
1455 }
1456 fn _linen(&self) -> u8 {
1457 const MASK: u8 = 1;
1458 const OFFSET: u8 = 14;
1459 ((self.bits >> OFFSET) & MASK as u32) as u8
1460 }
1461 # [ doc = "Bit 14 - LIN mode enable" ]
1462 pub fn linen(&self) -> LinenR {
1463 LinenR { bits: self._linen() }
1464 }
1465 fn _stop(&self) -> u8 {
1466 const MASK: u8 = 3;
1467 const OFFSET: u8 = 12;
1468 ((self.bits >> OFFSET) & MASK as u32) as u8
1469 }
1470 # [ doc = "Bits 12:13 - STOP bits" ]
1471 pub fn stop(&self) -> StopR {
1472 StopR { bits: self._stop() }
1473 }
1474 fn _clken(&self) -> u8 {
1475 const MASK: u8 = 1;
1476 const OFFSET: u8 = 11;
1477 ((self.bits >> OFFSET) & MASK as u32) as u8
1478 }
1479 # [ doc = "Bit 11 - Clock enable" ]
1480 pub fn clken(&self) -> ClkenR {
1481 ClkenR { bits: self._clken() }
1482 }
1483 fn _cpol(&self) -> u8 {
1484 const MASK: u8 = 1;
1485 const OFFSET: u8 = 10;
1486 ((self.bits >> OFFSET) & MASK as u32) as u8
1487 }
1488 # [ doc = "Bit 10 - Clock polarity" ]
1489 pub fn cpol(&self) -> CpolR {
1490 CpolR { bits: self._cpol() }
1491 }
1492 fn _cpha(&self) -> u8 {
1493 const MASK: u8 = 1;
1494 const OFFSET: u8 = 9;
1495 ((self.bits >> OFFSET) & MASK as u32) as u8
1496 }
1497 # [ doc = "Bit 9 - Clock phase" ]
1498 pub fn cpha(&self) -> CphaR {
1499 CphaR { bits: self._cpha() }
1500 }
1501 fn _lbcl(&self) -> u8 {
1502 const MASK: u8 = 1;
1503 const OFFSET: u8 = 8;
1504 ((self.bits >> OFFSET) & MASK as u32) as u8
1505 }
1506 # [ doc = "Bit 8 - Last bit clock pulse" ]
1507 pub fn lbcl(&self) -> LbclR {
1508 LbclR { bits: self._lbcl() }
1509 }
1510 fn _lbdie(&self) -> u8 {
1511 const MASK: u8 = 1;
1512 const OFFSET: u8 = 6;
1513 ((self.bits >> OFFSET) & MASK as u32) as u8
1514 }
1515 # [ doc = "Bit 6 - LIN break detection interrupt enable" ]
1516 pub fn lbdie(&self) -> LbdieR {
1517 LbdieR { bits: self._lbdie() }
1518 }
1519 fn _lbdl(&self) -> u8 {
1520 const MASK: u8 = 1;
1521 const OFFSET: u8 = 5;
1522 ((self.bits >> OFFSET) & MASK as u32) as u8
1523 }
1524 # [ doc = "Bit 5 - LIN break detection length" ]
1525 pub fn lbdl(&self) -> LbdlR {
1526 LbdlR { bits: self._lbdl() }
1527 }
1528 fn _addm7(&self) -> u8 {
1529 const MASK: u8 = 1;
1530 const OFFSET: u8 = 4;
1531 ((self.bits >> OFFSET) & MASK as u32) as u8
1532 }
1533 # [ doc = "Bit 4 - 7-bit Address Detection/4-bit Address Detection" ]
1534 pub fn addm7(&self) -> Addm7R {
1535 Addm7R { bits: self._addm7() }
1536 }
1537 }
1538 impl W {
1539 # [ doc = r" Reset value of the register" ]
1540 pub fn reset_value() -> W {
1541 W { bits: 0 }
1542 }
1543 # [ doc = r" Writes raw `bits` to the register" ]
1544 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1545 self.bits = bits;
1546 self
1547 }
1548 # [ doc = "Bits 28:31 - Address of the USART node" ]
1549 pub fn add4(&mut self) -> _Add4W {
1550 _Add4W { register: self }
1551 }
1552 # [ doc = "Bits 24:27 - Address of the USART node" ]
1553 pub fn add0(&mut self) -> _Add0W {
1554 _Add0W { register: self }
1555 }
1556 # [ doc = "Bit 23 - Receiver timeout enable" ]
1557 pub fn rtoen(&mut self) -> _RtoenW {
1558 _RtoenW { register: self }
1559 }
1560 # [ doc = "Bits 21:22 - Auto baud rate mode" ]
1561 pub fn abrmod(&mut self) -> _AbrmodW {
1562 _AbrmodW { register: self }
1563 }
1564 # [ doc = "Bit 20 - Auto baud rate enable" ]
1565 pub fn abren(&mut self) -> _AbrenW {
1566 _AbrenW { register: self }
1567 }
1568 # [ doc = "Bit 19 - Most significant bit first" ]
1569 pub fn msbfirst(&mut self) -> _MsbfirstW {
1570 _MsbfirstW { register: self }
1571 }
1572 # [ doc = "Bit 18 - Binary data inversion" ]
1573 pub fn datainv(&mut self) -> _DatainvW {
1574 _DatainvW { register: self }
1575 }
1576 # [ doc = "Bit 17 - TX pin active level inversion" ]
1577 pub fn txinv(&mut self) -> _TxinvW {
1578 _TxinvW { register: self }
1579 }
1580 # [ doc = "Bit 16 - RX pin active level inversion" ]
1581 pub fn rxinv(&mut self) -> _RxinvW {
1582 _RxinvW { register: self }
1583 }
1584 # [ doc = "Bit 15 - Swap TX/RX pins" ]
1585 pub fn swap(&mut self) -> _SwapW {
1586 _SwapW { register: self }
1587 }
1588 # [ doc = "Bit 14 - LIN mode enable" ]
1589 pub fn linen(&mut self) -> _LinenW {
1590 _LinenW { register: self }
1591 }
1592 # [ doc = "Bits 12:13 - STOP bits" ]
1593 pub fn stop(&mut self) -> _StopW {
1594 _StopW { register: self }
1595 }
1596 # [ doc = "Bit 11 - Clock enable" ]
1597 pub fn clken(&mut self) -> _ClkenW {
1598 _ClkenW { register: self }
1599 }
1600 # [ doc = "Bit 10 - Clock polarity" ]
1601 pub fn cpol(&mut self) -> _CpolW {
1602 _CpolW { register: self }
1603 }
1604 # [ doc = "Bit 9 - Clock phase" ]
1605 pub fn cpha(&mut self) -> _CphaW {
1606 _CphaW { register: self }
1607 }
1608 # [ doc = "Bit 8 - Last bit clock pulse" ]
1609 pub fn lbcl(&mut self) -> _LbclW {
1610 _LbclW { register: self }
1611 }
1612 # [ doc = "Bit 6 - LIN break detection interrupt enable" ]
1613 pub fn lbdie(&mut self) -> _LbdieW {
1614 _LbdieW { register: self }
1615 }
1616 # [ doc = "Bit 5 - LIN break detection length" ]
1617 pub fn lbdl(&mut self) -> _LbdlW {
1618 _LbdlW { register: self }
1619 }
1620 # [ doc = "Bit 4 - 7-bit Address Detection/4-bit Address Detection" ]
1621 pub fn addm7(&mut self) -> _Addm7W {
1622 _Addm7W { register: self }
1623 }
1624 }
1625}
1626
1627# [ doc = "Control register 3" ]
1628# [ repr ( C ) ]
1629pub struct Cr3 {
1630 register: ::volatile_register::RW<u32>,
1631}
1632
1633# [ doc = "Control register 3" ]
1634pub mod cr3 {
1635 # [ doc = r" Value read from the register" ]
1636 pub struct R {
1637 bits: u32,
1638 }
1639 # [ doc = r" Value to write to the register" ]
1640 pub struct W {
1641 bits: u32,
1642 }
1643 impl super::Cr3 {
1644 # [ doc = r" Modifies the contents of the register" ]
1645 pub fn modify<F>(&mut self, f: F)
1646 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
1647 {
1648 let bits = self.register.read();
1649 let r = R { bits: bits };
1650 let mut w = W { bits: bits };
1651 f(&r, &mut w);
1652 self.register.write(w.bits);
1653 }
1654 # [ doc = r" Reads the contents of the register" ]
1655 pub fn read(&self) -> R {
1656 R { bits: self.register.read() }
1657 }
1658 # [ doc = r" Writes to the register" ]
1659 pub fn write<F>(&mut self, f: F)
1660 where F: FnOnce(&mut W) -> &mut W
1661 {
1662 let mut w = W::reset_value();
1663 f(&mut w);
1664 self.register.write(w.bits);
1665 }
1666 }
1667 # [ doc = "Value of the field WUFIE" ]
1668 pub struct WufieR {
1669 bits: u8,
1670 }
1671 impl WufieR {
1672 # [ doc = r" Value of the field as raw bits" ]
1673 pub fn bits(&self) -> u8 {
1674 self.bits
1675 }
1676 }
1677 # [ doc = "Value of the field WUS" ]
1678 pub struct WusR {
1679 bits: u8,
1680 }
1681 impl WusR {
1682 # [ doc = r" Value of the field as raw bits" ]
1683 pub fn bits(&self) -> u8 {
1684 self.bits
1685 }
1686 }
1687 # [ doc = "Value of the field SCARCNT" ]
1688 pub struct ScarcntR {
1689 bits: u8,
1690 }
1691 impl ScarcntR {
1692 # [ doc = r" Value of the field as raw bits" ]
1693 pub fn bits(&self) -> u8 {
1694 self.bits
1695 }
1696 }
1697 # [ doc = "Value of the field DEP" ]
1698 pub struct DepR {
1699 bits: u8,
1700 }
1701 impl DepR {
1702 # [ doc = r" Value of the field as raw bits" ]
1703 pub fn bits(&self) -> u8 {
1704 self.bits
1705 }
1706 }
1707 # [ doc = "Value of the field DEM" ]
1708 pub struct DemR {
1709 bits: u8,
1710 }
1711 impl DemR {
1712 # [ doc = r" Value of the field as raw bits" ]
1713 pub fn bits(&self) -> u8 {
1714 self.bits
1715 }
1716 }
1717 # [ doc = "Value of the field DDRE" ]
1718 pub struct DdreR {
1719 bits: u8,
1720 }
1721 impl DdreR {
1722 # [ doc = r" Value of the field as raw bits" ]
1723 pub fn bits(&self) -> u8 {
1724 self.bits
1725 }
1726 }
1727 # [ doc = "Value of the field OVRDIS" ]
1728 pub struct OvrdisR {
1729 bits: u8,
1730 }
1731 impl OvrdisR {
1732 # [ doc = r" Value of the field as raw bits" ]
1733 pub fn bits(&self) -> u8 {
1734 self.bits
1735 }
1736 }
1737 # [ doc = "Value of the field ONEBIT" ]
1738 pub struct OnebitR {
1739 bits: u8,
1740 }
1741 impl OnebitR {
1742 # [ doc = r" Value of the field as raw bits" ]
1743 pub fn bits(&self) -> u8 {
1744 self.bits
1745 }
1746 }
1747 # [ doc = "Value of the field CTSIE" ]
1748 pub struct CtsieR {
1749 bits: u8,
1750 }
1751 impl CtsieR {
1752 # [ doc = r" Value of the field as raw bits" ]
1753 pub fn bits(&self) -> u8 {
1754 self.bits
1755 }
1756 }
1757 # [ doc = "Value of the field CTSE" ]
1758 pub struct CtseR {
1759 bits: u8,
1760 }
1761 impl CtseR {
1762 # [ doc = r" Value of the field as raw bits" ]
1763 pub fn bits(&self) -> u8 {
1764 self.bits
1765 }
1766 }
1767 # [ doc = "Value of the field RTSE" ]
1768 pub struct RtseR {
1769 bits: u8,
1770 }
1771 impl RtseR {
1772 # [ doc = r" Value of the field as raw bits" ]
1773 pub fn bits(&self) -> u8 {
1774 self.bits
1775 }
1776 }
1777 # [ doc = "Value of the field DMAT" ]
1778 pub struct DmatR {
1779 bits: u8,
1780 }
1781 impl DmatR {
1782 # [ doc = r" Value of the field as raw bits" ]
1783 pub fn bits(&self) -> u8 {
1784 self.bits
1785 }
1786 }
1787 # [ doc = "Value of the field DMAR" ]
1788 pub struct DmarR {
1789 bits: u8,
1790 }
1791 impl DmarR {
1792 # [ doc = r" Value of the field as raw bits" ]
1793 pub fn bits(&self) -> u8 {
1794 self.bits
1795 }
1796 }
1797 # [ doc = "Value of the field SCEN" ]
1798 pub struct ScenR {
1799 bits: u8,
1800 }
1801 impl ScenR {
1802 # [ doc = r" Value of the field as raw bits" ]
1803 pub fn bits(&self) -> u8 {
1804 self.bits
1805 }
1806 }
1807 # [ doc = "Value of the field NACK" ]
1808 pub struct NackR {
1809 bits: u8,
1810 }
1811 impl NackR {
1812 # [ doc = r" Value of the field as raw bits" ]
1813 pub fn bits(&self) -> u8 {
1814 self.bits
1815 }
1816 }
1817 # [ doc = "Value of the field HDSEL" ]
1818 pub struct HdselR {
1819 bits: u8,
1820 }
1821 impl HdselR {
1822 # [ doc = r" Value of the field as raw bits" ]
1823 pub fn bits(&self) -> u8 {
1824 self.bits
1825 }
1826 }
1827 # [ doc = "Value of the field IRLP" ]
1828 pub struct IrlpR {
1829 bits: u8,
1830 }
1831 impl IrlpR {
1832 # [ doc = r" Value of the field as raw bits" ]
1833 pub fn bits(&self) -> u8 {
1834 self.bits
1835 }
1836 }
1837 # [ doc = "Value of the field IREN" ]
1838 pub struct IrenR {
1839 bits: u8,
1840 }
1841 impl IrenR {
1842 # [ doc = r" Value of the field as raw bits" ]
1843 pub fn bits(&self) -> u8 {
1844 self.bits
1845 }
1846 }
1847 # [ doc = "Value of the field EIE" ]
1848 pub struct EieR {
1849 bits: u8,
1850 }
1851 impl EieR {
1852 # [ doc = r" Value of the field as raw bits" ]
1853 pub fn bits(&self) -> u8 {
1854 self.bits
1855 }
1856 }
1857 # [ doc = r" Proxy" ]
1858 pub struct _WufieW<'a> {
1859 register: &'a mut W,
1860 }
1861 impl<'a> _WufieW<'a> {
1862 # [ doc = r" Writes raw `bits` to the field" ]
1863 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1864 const MASK: u8 = 1;
1865 const OFFSET: u8 = 22;
1866 self.register.bits &= !((MASK as u32) << OFFSET);
1867 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1868 self.register
1869 }
1870 }
1871 # [ doc = r" Proxy" ]
1872 pub struct _WusW<'a> {
1873 register: &'a mut W,
1874 }
1875 impl<'a> _WusW<'a> {
1876 # [ doc = r" Writes raw `bits` to the field" ]
1877 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1878 const MASK: u8 = 3;
1879 const OFFSET: u8 = 20;
1880 self.register.bits &= !((MASK as u32) << OFFSET);
1881 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1882 self.register
1883 }
1884 }
1885 # [ doc = r" Proxy" ]
1886 pub struct _ScarcntW<'a> {
1887 register: &'a mut W,
1888 }
1889 impl<'a> _ScarcntW<'a> {
1890 # [ doc = r" Writes raw `bits` to the field" ]
1891 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1892 const MASK: u8 = 7;
1893 const OFFSET: u8 = 17;
1894 self.register.bits &= !((MASK as u32) << OFFSET);
1895 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1896 self.register
1897 }
1898 }
1899 # [ doc = r" Proxy" ]
1900 pub struct _DepW<'a> {
1901 register: &'a mut W,
1902 }
1903 impl<'a> _DepW<'a> {
1904 # [ doc = r" Writes raw `bits` to the field" ]
1905 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1906 const MASK: u8 = 1;
1907 const OFFSET: u8 = 15;
1908 self.register.bits &= !((MASK as u32) << OFFSET);
1909 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1910 self.register
1911 }
1912 }
1913 # [ doc = r" Proxy" ]
1914 pub struct _DemW<'a> {
1915 register: &'a mut W,
1916 }
1917 impl<'a> _DemW<'a> {
1918 # [ doc = r" Writes raw `bits` to the field" ]
1919 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1920 const MASK: u8 = 1;
1921 const OFFSET: u8 = 14;
1922 self.register.bits &= !((MASK as u32) << OFFSET);
1923 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1924 self.register
1925 }
1926 }
1927 # [ doc = r" Proxy" ]
1928 pub struct _DdreW<'a> {
1929 register: &'a mut W,
1930 }
1931 impl<'a> _DdreW<'a> {
1932 # [ doc = r" Writes raw `bits` to the field" ]
1933 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1934 const MASK: u8 = 1;
1935 const OFFSET: u8 = 13;
1936 self.register.bits &= !((MASK as u32) << OFFSET);
1937 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1938 self.register
1939 }
1940 }
1941 # [ doc = r" Proxy" ]
1942 pub struct _OvrdisW<'a> {
1943 register: &'a mut W,
1944 }
1945 impl<'a> _OvrdisW<'a> {
1946 # [ doc = r" Writes raw `bits` to the field" ]
1947 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1948 const MASK: u8 = 1;
1949 const OFFSET: u8 = 12;
1950 self.register.bits &= !((MASK as u32) << OFFSET);
1951 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1952 self.register
1953 }
1954 }
1955 # [ doc = r" Proxy" ]
1956 pub struct _OnebitW<'a> {
1957 register: &'a mut W,
1958 }
1959 impl<'a> _OnebitW<'a> {
1960 # [ doc = r" Writes raw `bits` to the field" ]
1961 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1962 const MASK: u8 = 1;
1963 const OFFSET: u8 = 11;
1964 self.register.bits &= !((MASK as u32) << OFFSET);
1965 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1966 self.register
1967 }
1968 }
1969 # [ doc = r" Proxy" ]
1970 pub struct _CtsieW<'a> {
1971 register: &'a mut W,
1972 }
1973 impl<'a> _CtsieW<'a> {
1974 # [ doc = r" Writes raw `bits` to the field" ]
1975 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1976 const MASK: u8 = 1;
1977 const OFFSET: u8 = 10;
1978 self.register.bits &= !((MASK as u32) << OFFSET);
1979 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1980 self.register
1981 }
1982 }
1983 # [ doc = r" Proxy" ]
1984 pub struct _CtseW<'a> {
1985 register: &'a mut W,
1986 }
1987 impl<'a> _CtseW<'a> {
1988 # [ doc = r" Writes raw `bits` to the field" ]
1989 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1990 const MASK: u8 = 1;
1991 const OFFSET: u8 = 9;
1992 self.register.bits &= !((MASK as u32) << OFFSET);
1993 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1994 self.register
1995 }
1996 }
1997 # [ doc = r" Proxy" ]
1998 pub struct _RtseW<'a> {
1999 register: &'a mut W,
2000 }
2001 impl<'a> _RtseW<'a> {
2002 # [ doc = r" Writes raw `bits` to the field" ]
2003 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2004 const MASK: u8 = 1;
2005 const OFFSET: u8 = 8;
2006 self.register.bits &= !((MASK as u32) << OFFSET);
2007 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2008 self.register
2009 }
2010 }
2011 # [ doc = r" Proxy" ]
2012 pub struct _DmatW<'a> {
2013 register: &'a mut W,
2014 }
2015 impl<'a> _DmatW<'a> {
2016 # [ doc = r" Writes raw `bits` to the field" ]
2017 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2018 const MASK: u8 = 1;
2019 const OFFSET: u8 = 7;
2020 self.register.bits &= !((MASK as u32) << OFFSET);
2021 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2022 self.register
2023 }
2024 }
2025 # [ doc = r" Proxy" ]
2026 pub struct _DmarW<'a> {
2027 register: &'a mut W,
2028 }
2029 impl<'a> _DmarW<'a> {
2030 # [ doc = r" Writes raw `bits` to the field" ]
2031 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2032 const MASK: u8 = 1;
2033 const OFFSET: u8 = 6;
2034 self.register.bits &= !((MASK as u32) << OFFSET);
2035 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2036 self.register
2037 }
2038 }
2039 # [ doc = r" Proxy" ]
2040 pub struct _ScenW<'a> {
2041 register: &'a mut W,
2042 }
2043 impl<'a> _ScenW<'a> {
2044 # [ doc = r" Writes raw `bits` to the field" ]
2045 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2046 const MASK: u8 = 1;
2047 const OFFSET: u8 = 5;
2048 self.register.bits &= !((MASK as u32) << OFFSET);
2049 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2050 self.register
2051 }
2052 }
2053 # [ doc = r" Proxy" ]
2054 pub struct _NackW<'a> {
2055 register: &'a mut W,
2056 }
2057 impl<'a> _NackW<'a> {
2058 # [ doc = r" Writes raw `bits` to the field" ]
2059 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2060 const MASK: u8 = 1;
2061 const OFFSET: u8 = 4;
2062 self.register.bits &= !((MASK as u32) << OFFSET);
2063 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2064 self.register
2065 }
2066 }
2067 # [ doc = r" Proxy" ]
2068 pub struct _HdselW<'a> {
2069 register: &'a mut W,
2070 }
2071 impl<'a> _HdselW<'a> {
2072 # [ doc = r" Writes raw `bits` to the field" ]
2073 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2074 const MASK: u8 = 1;
2075 const OFFSET: u8 = 3;
2076 self.register.bits &= !((MASK as u32) << OFFSET);
2077 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2078 self.register
2079 }
2080 }
2081 # [ doc = r" Proxy" ]
2082 pub struct _IrlpW<'a> {
2083 register: &'a mut W,
2084 }
2085 impl<'a> _IrlpW<'a> {
2086 # [ doc = r" Writes raw `bits` to the field" ]
2087 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2088 const MASK: u8 = 1;
2089 const OFFSET: u8 = 2;
2090 self.register.bits &= !((MASK as u32) << OFFSET);
2091 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2092 self.register
2093 }
2094 }
2095 # [ doc = r" Proxy" ]
2096 pub struct _IrenW<'a> {
2097 register: &'a mut W,
2098 }
2099 impl<'a> _IrenW<'a> {
2100 # [ doc = r" Writes raw `bits` to the field" ]
2101 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2102 const MASK: u8 = 1;
2103 const OFFSET: u8 = 1;
2104 self.register.bits &= !((MASK as u32) << OFFSET);
2105 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2106 self.register
2107 }
2108 }
2109 # [ doc = r" Proxy" ]
2110 pub struct _EieW<'a> {
2111 register: &'a mut W,
2112 }
2113 impl<'a> _EieW<'a> {
2114 # [ doc = r" Writes raw `bits` to the field" ]
2115 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2116 const MASK: u8 = 1;
2117 const OFFSET: u8 = 0;
2118 self.register.bits &= !((MASK as u32) << OFFSET);
2119 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2120 self.register
2121 }
2122 }
2123 impl R {
2124 # [ doc = r" Value of the register as raw bits" ]
2125 pub fn bits(&self) -> u32 {
2126 self.bits
2127 }
2128 fn _wufie(&self) -> u8 {
2129 const MASK: u8 = 1;
2130 const OFFSET: u8 = 22;
2131 ((self.bits >> OFFSET) & MASK as u32) as u8
2132 }
2133 # [ doc = "Bit 22 - Wakeup from Stop mode interrupt enable" ]
2134 pub fn wufie(&self) -> WufieR {
2135 WufieR { bits: self._wufie() }
2136 }
2137 fn _wus(&self) -> u8 {
2138 const MASK: u8 = 3;
2139 const OFFSET: u8 = 20;
2140 ((self.bits >> OFFSET) & MASK as u32) as u8
2141 }
2142 # [ doc = "Bits 20:21 - Wakeup from Stop mode interrupt flag selection" ]
2143 pub fn wus(&self) -> WusR {
2144 WusR { bits: self._wus() }
2145 }
2146 fn _scarcnt(&self) -> u8 {
2147 const MASK: u8 = 7;
2148 const OFFSET: u8 = 17;
2149 ((self.bits >> OFFSET) & MASK as u32) as u8
2150 }
2151 # [ doc = "Bits 17:19 - Smartcard auto-retry count" ]
2152 pub fn scarcnt(&self) -> ScarcntR {
2153 ScarcntR { bits: self._scarcnt() }
2154 }
2155 fn _dep(&self) -> u8 {
2156 const MASK: u8 = 1;
2157 const OFFSET: u8 = 15;
2158 ((self.bits >> OFFSET) & MASK as u32) as u8
2159 }
2160 # [ doc = "Bit 15 - Driver enable polarity selection" ]
2161 pub fn dep(&self) -> DepR {
2162 DepR { bits: self._dep() }
2163 }
2164 fn _dem(&self) -> u8 {
2165 const MASK: u8 = 1;
2166 const OFFSET: u8 = 14;
2167 ((self.bits >> OFFSET) & MASK as u32) as u8
2168 }
2169 # [ doc = "Bit 14 - Driver enable mode" ]
2170 pub fn dem(&self) -> DemR {
2171 DemR { bits: self._dem() }
2172 }
2173 fn _ddre(&self) -> u8 {
2174 const MASK: u8 = 1;
2175 const OFFSET: u8 = 13;
2176 ((self.bits >> OFFSET) & MASK as u32) as u8
2177 }
2178 # [ doc = "Bit 13 - DMA Disable on Reception Error" ]
2179 pub fn ddre(&self) -> DdreR {
2180 DdreR { bits: self._ddre() }
2181 }
2182 fn _ovrdis(&self) -> u8 {
2183 const MASK: u8 = 1;
2184 const OFFSET: u8 = 12;
2185 ((self.bits >> OFFSET) & MASK as u32) as u8
2186 }
2187 # [ doc = "Bit 12 - Overrun Disable" ]
2188 pub fn ovrdis(&self) -> OvrdisR {
2189 OvrdisR { bits: self._ovrdis() }
2190 }
2191 fn _onebit(&self) -> u8 {
2192 const MASK: u8 = 1;
2193 const OFFSET: u8 = 11;
2194 ((self.bits >> OFFSET) & MASK as u32) as u8
2195 }
2196 # [ doc = "Bit 11 - One sample bit method enable" ]
2197 pub fn onebit(&self) -> OnebitR {
2198 OnebitR { bits: self._onebit() }
2199 }
2200 fn _ctsie(&self) -> u8 {
2201 const MASK: u8 = 1;
2202 const OFFSET: u8 = 10;
2203 ((self.bits >> OFFSET) & MASK as u32) as u8
2204 }
2205 # [ doc = "Bit 10 - CTS interrupt enable" ]
2206 pub fn ctsie(&self) -> CtsieR {
2207 CtsieR { bits: self._ctsie() }
2208 }
2209 fn _ctse(&self) -> u8 {
2210 const MASK: u8 = 1;
2211 const OFFSET: u8 = 9;
2212 ((self.bits >> OFFSET) & MASK as u32) as u8
2213 }
2214 # [ doc = "Bit 9 - CTS enable" ]
2215 pub fn ctse(&self) -> CtseR {
2216 CtseR { bits: self._ctse() }
2217 }
2218 fn _rtse(&self) -> u8 {
2219 const MASK: u8 = 1;
2220 const OFFSET: u8 = 8;
2221 ((self.bits >> OFFSET) & MASK as u32) as u8
2222 }
2223 # [ doc = "Bit 8 - RTS enable" ]
2224 pub fn rtse(&self) -> RtseR {
2225 RtseR { bits: self._rtse() }
2226 }
2227 fn _dmat(&self) -> u8 {
2228 const MASK: u8 = 1;
2229 const OFFSET: u8 = 7;
2230 ((self.bits >> OFFSET) & MASK as u32) as u8
2231 }
2232 # [ doc = "Bit 7 - DMA enable transmitter" ]
2233 pub fn dmat(&self) -> DmatR {
2234 DmatR { bits: self._dmat() }
2235 }
2236 fn _dmar(&self) -> u8 {
2237 const MASK: u8 = 1;
2238 const OFFSET: u8 = 6;
2239 ((self.bits >> OFFSET) & MASK as u32) as u8
2240 }
2241 # [ doc = "Bit 6 - DMA enable receiver" ]
2242 pub fn dmar(&self) -> DmarR {
2243 DmarR { bits: self._dmar() }
2244 }
2245 fn _scen(&self) -> u8 {
2246 const MASK: u8 = 1;
2247 const OFFSET: u8 = 5;
2248 ((self.bits >> OFFSET) & MASK as u32) as u8
2249 }
2250 # [ doc = "Bit 5 - Smartcard mode enable" ]
2251 pub fn scen(&self) -> ScenR {
2252 ScenR { bits: self._scen() }
2253 }
2254 fn _nack(&self) -> u8 {
2255 const MASK: u8 = 1;
2256 const OFFSET: u8 = 4;
2257 ((self.bits >> OFFSET) & MASK as u32) as u8
2258 }
2259 # [ doc = "Bit 4 - Smartcard NACK enable" ]
2260 pub fn nack(&self) -> NackR {
2261 NackR { bits: self._nack() }
2262 }
2263 fn _hdsel(&self) -> u8 {
2264 const MASK: u8 = 1;
2265 const OFFSET: u8 = 3;
2266 ((self.bits >> OFFSET) & MASK as u32) as u8
2267 }
2268 # [ doc = "Bit 3 - Half-duplex selection" ]
2269 pub fn hdsel(&self) -> HdselR {
2270 HdselR { bits: self._hdsel() }
2271 }
2272 fn _irlp(&self) -> u8 {
2273 const MASK: u8 = 1;
2274 const OFFSET: u8 = 2;
2275 ((self.bits >> OFFSET) & MASK as u32) as u8
2276 }
2277 # [ doc = "Bit 2 - IrDA low-power" ]
2278 pub fn irlp(&self) -> IrlpR {
2279 IrlpR { bits: self._irlp() }
2280 }
2281 fn _iren(&self) -> u8 {
2282 const MASK: u8 = 1;
2283 const OFFSET: u8 = 1;
2284 ((self.bits >> OFFSET) & MASK as u32) as u8
2285 }
2286 # [ doc = "Bit 1 - IrDA mode enable" ]
2287 pub fn iren(&self) -> IrenR {
2288 IrenR { bits: self._iren() }
2289 }
2290 fn _eie(&self) -> u8 {
2291 const MASK: u8 = 1;
2292 const OFFSET: u8 = 0;
2293 ((self.bits >> OFFSET) & MASK as u32) as u8
2294 }
2295 # [ doc = "Bit 0 - Error interrupt enable" ]
2296 pub fn eie(&self) -> EieR {
2297 EieR { bits: self._eie() }
2298 }
2299 }
2300 impl W {
2301 # [ doc = r" Reset value of the register" ]
2302 pub fn reset_value() -> W {
2303 W { bits: 0 }
2304 }
2305 # [ doc = r" Writes raw `bits` to the register" ]
2306 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
2307 self.bits = bits;
2308 self
2309 }
2310 # [ doc = "Bit 22 - Wakeup from Stop mode interrupt enable" ]
2311 pub fn wufie(&mut self) -> _WufieW {
2312 _WufieW { register: self }
2313 }
2314 # [ doc = "Bits 20:21 - Wakeup from Stop mode interrupt flag selection" ]
2315 pub fn wus(&mut self) -> _WusW {
2316 _WusW { register: self }
2317 }
2318 # [ doc = "Bits 17:19 - Smartcard auto-retry count" ]
2319 pub fn scarcnt(&mut self) -> _ScarcntW {
2320 _ScarcntW { register: self }
2321 }
2322 # [ doc = "Bit 15 - Driver enable polarity selection" ]
2323 pub fn dep(&mut self) -> _DepW {
2324 _DepW { register: self }
2325 }
2326 # [ doc = "Bit 14 - Driver enable mode" ]
2327 pub fn dem(&mut self) -> _DemW {
2328 _DemW { register: self }
2329 }
2330 # [ doc = "Bit 13 - DMA Disable on Reception Error" ]
2331 pub fn ddre(&mut self) -> _DdreW {
2332 _DdreW { register: self }
2333 }
2334 # [ doc = "Bit 12 - Overrun Disable" ]
2335 pub fn ovrdis(&mut self) -> _OvrdisW {
2336 _OvrdisW { register: self }
2337 }
2338 # [ doc = "Bit 11 - One sample bit method enable" ]
2339 pub fn onebit(&mut self) -> _OnebitW {
2340 _OnebitW { register: self }
2341 }
2342 # [ doc = "Bit 10 - CTS interrupt enable" ]
2343 pub fn ctsie(&mut self) -> _CtsieW {
2344 _CtsieW { register: self }
2345 }
2346 # [ doc = "Bit 9 - CTS enable" ]
2347 pub fn ctse(&mut self) -> _CtseW {
2348 _CtseW { register: self }
2349 }
2350 # [ doc = "Bit 8 - RTS enable" ]
2351 pub fn rtse(&mut self) -> _RtseW {
2352 _RtseW { register: self }
2353 }
2354 # [ doc = "Bit 7 - DMA enable transmitter" ]
2355 pub fn dmat(&mut self) -> _DmatW {
2356 _DmatW { register: self }
2357 }
2358 # [ doc = "Bit 6 - DMA enable receiver" ]
2359 pub fn dmar(&mut self) -> _DmarW {
2360 _DmarW { register: self }
2361 }
2362 # [ doc = "Bit 5 - Smartcard mode enable" ]
2363 pub fn scen(&mut self) -> _ScenW {
2364 _ScenW { register: self }
2365 }
2366 # [ doc = "Bit 4 - Smartcard NACK enable" ]
2367 pub fn nack(&mut self) -> _NackW {
2368 _NackW { register: self }
2369 }
2370 # [ doc = "Bit 3 - Half-duplex selection" ]
2371 pub fn hdsel(&mut self) -> _HdselW {
2372 _HdselW { register: self }
2373 }
2374 # [ doc = "Bit 2 - IrDA low-power" ]
2375 pub fn irlp(&mut self) -> _IrlpW {
2376 _IrlpW { register: self }
2377 }
2378 # [ doc = "Bit 1 - IrDA mode enable" ]
2379 pub fn iren(&mut self) -> _IrenW {
2380 _IrenW { register: self }
2381 }
2382 # [ doc = "Bit 0 - Error interrupt enable" ]
2383 pub fn eie(&mut self) -> _EieW {
2384 _EieW { register: self }
2385 }
2386 }
2387}
2388
2389# [ doc = "Baud rate register" ]
2390# [ repr ( C ) ]
2391pub struct Brr {
2392 register: ::volatile_register::RW<u32>,
2393}
2394
2395# [ doc = "Baud rate register" ]
2396pub mod brr {
2397 # [ doc = r" Value read from the register" ]
2398 pub struct R {
2399 bits: u32,
2400 }
2401 # [ doc = r" Value to write to the register" ]
2402 pub struct W {
2403 bits: u32,
2404 }
2405 impl super::Brr {
2406 # [ doc = r" Modifies the contents of the register" ]
2407 pub fn modify<F>(&mut self, f: F)
2408 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
2409 {
2410 let bits = self.register.read();
2411 let r = R { bits: bits };
2412 let mut w = W { bits: bits };
2413 f(&r, &mut w);
2414 self.register.write(w.bits);
2415 }
2416 # [ doc = r" Reads the contents of the register" ]
2417 pub fn read(&self) -> R {
2418 R { bits: self.register.read() }
2419 }
2420 # [ doc = r" Writes to the register" ]
2421 pub fn write<F>(&mut self, f: F)
2422 where F: FnOnce(&mut W) -> &mut W
2423 {
2424 let mut w = W::reset_value();
2425 f(&mut w);
2426 self.register.write(w.bits);
2427 }
2428 }
2429 # [ doc = "Value of the field DIV_Mantissa" ]
2430 pub struct DivMantissaR {
2431 bits: u16,
2432 }
2433 impl DivMantissaR {
2434 # [ doc = r" Value of the field as raw bits" ]
2435 pub fn bits(&self) -> u16 {
2436 self.bits
2437 }
2438 }
2439 # [ doc = "Value of the field DIV_Fraction" ]
2440 pub struct DivFractionR {
2441 bits: u8,
2442 }
2443 impl DivFractionR {
2444 # [ doc = r" Value of the field as raw bits" ]
2445 pub fn bits(&self) -> u8 {
2446 self.bits
2447 }
2448 }
2449 # [ doc = r" Proxy" ]
2450 pub struct _DivMantissaW<'a> {
2451 register: &'a mut W,
2452 }
2453 impl<'a> _DivMantissaW<'a> {
2454 # [ doc = r" Writes raw `bits` to the field" ]
2455 pub unsafe fn bits(self, bits: u16) -> &'a mut W {
2456 const MASK: u16 = 4095;
2457 const OFFSET: u8 = 4;
2458 self.register.bits &= !((MASK as u32) << OFFSET);
2459 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2460 self.register
2461 }
2462 }
2463 # [ doc = r" Proxy" ]
2464 pub struct _DivFractionW<'a> {
2465 register: &'a mut W,
2466 }
2467 impl<'a> _DivFractionW<'a> {
2468 # [ doc = r" Writes raw `bits` to the field" ]
2469 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2470 const MASK: u8 = 15;
2471 const OFFSET: u8 = 0;
2472 self.register.bits &= !((MASK as u32) << OFFSET);
2473 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2474 self.register
2475 }
2476 }
2477 impl R {
2478 # [ doc = r" Value of the register as raw bits" ]
2479 pub fn bits(&self) -> u32 {
2480 self.bits
2481 }
2482 fn _div_mantissa(&self) -> u16 {
2483 const MASK: u16 = 4095;
2484 const OFFSET: u8 = 4;
2485 ((self.bits >> OFFSET) & MASK as u32) as u16
2486 }
2487 # [ doc = "Bits 4:15 - mantissa of USARTDIV" ]
2488 pub fn div_mantissa(&self) -> DivMantissaR {
2489 DivMantissaR { bits: self._div_mantissa() }
2490 }
2491 fn _div_fraction(&self) -> u8 {
2492 const MASK: u8 = 15;
2493 const OFFSET: u8 = 0;
2494 ((self.bits >> OFFSET) & MASK as u32) as u8
2495 }
2496 # [ doc = "Bits 0:3 - fraction of USARTDIV" ]
2497 pub fn div_fraction(&self) -> DivFractionR {
2498 DivFractionR { bits: self._div_fraction() }
2499 }
2500 }
2501 impl W {
2502 # [ doc = r" Reset value of the register" ]
2503 pub fn reset_value() -> W {
2504 W { bits: 0 }
2505 }
2506 # [ doc = r" Writes raw `bits` to the register" ]
2507 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
2508 self.bits = bits;
2509 self
2510 }
2511 # [ doc = "Bits 4:15 - mantissa of USARTDIV" ]
2512 pub fn div_mantissa(&mut self) -> _DivMantissaW {
2513 _DivMantissaW { register: self }
2514 }
2515 # [ doc = "Bits 0:3 - fraction of USARTDIV" ]
2516 pub fn div_fraction(&mut self) -> _DivFractionW {
2517 _DivFractionW { register: self }
2518 }
2519 }
2520}
2521
2522# [ doc = "Guard time and prescaler register" ]
2523# [ repr ( C ) ]
2524pub struct Gtpr {
2525 register: ::volatile_register::RW<u32>,
2526}
2527
2528# [ doc = "Guard time and prescaler register" ]
2529pub mod gtpr {
2530 # [ doc = r" Value read from the register" ]
2531 pub struct R {
2532 bits: u32,
2533 }
2534 # [ doc = r" Value to write to the register" ]
2535 pub struct W {
2536 bits: u32,
2537 }
2538 impl super::Gtpr {
2539 # [ doc = r" Modifies the contents of the register" ]
2540 pub fn modify<F>(&mut self, f: F)
2541 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
2542 {
2543 let bits = self.register.read();
2544 let r = R { bits: bits };
2545 let mut w = W { bits: bits };
2546 f(&r, &mut w);
2547 self.register.write(w.bits);
2548 }
2549 # [ doc = r" Reads the contents of the register" ]
2550 pub fn read(&self) -> R {
2551 R { bits: self.register.read() }
2552 }
2553 # [ doc = r" Writes to the register" ]
2554 pub fn write<F>(&mut self, f: F)
2555 where F: FnOnce(&mut W) -> &mut W
2556 {
2557 let mut w = W::reset_value();
2558 f(&mut w);
2559 self.register.write(w.bits);
2560 }
2561 }
2562 # [ doc = "Value of the field GT" ]
2563 pub struct GtR {
2564 bits: u8,
2565 }
2566 impl GtR {
2567 # [ doc = r" Value of the field as raw bits" ]
2568 pub fn bits(&self) -> u8 {
2569 self.bits
2570 }
2571 }
2572 # [ doc = "Value of the field PSC" ]
2573 pub struct PscR {
2574 bits: u8,
2575 }
2576 impl PscR {
2577 # [ doc = r" Value of the field as raw bits" ]
2578 pub fn bits(&self) -> u8 {
2579 self.bits
2580 }
2581 }
2582 # [ doc = r" Proxy" ]
2583 pub struct _GtW<'a> {
2584 register: &'a mut W,
2585 }
2586 impl<'a> _GtW<'a> {
2587 # [ doc = r" Writes raw `bits` to the field" ]
2588 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2589 const MASK: u8 = 255;
2590 const OFFSET: u8 = 8;
2591 self.register.bits &= !((MASK as u32) << OFFSET);
2592 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2593 self.register
2594 }
2595 }
2596 # [ doc = r" Proxy" ]
2597 pub struct _PscW<'a> {
2598 register: &'a mut W,
2599 }
2600 impl<'a> _PscW<'a> {
2601 # [ doc = r" Writes raw `bits` to the field" ]
2602 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2603 const MASK: u8 = 255;
2604 const OFFSET: u8 = 0;
2605 self.register.bits &= !((MASK as u32) << OFFSET);
2606 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2607 self.register
2608 }
2609 }
2610 impl R {
2611 # [ doc = r" Value of the register as raw bits" ]
2612 pub fn bits(&self) -> u32 {
2613 self.bits
2614 }
2615 fn _gt(&self) -> u8 {
2616 const MASK: u8 = 255;
2617 const OFFSET: u8 = 8;
2618 ((self.bits >> OFFSET) & MASK as u32) as u8
2619 }
2620 # [ doc = "Bits 8:15 - Guard time value" ]
2621 pub fn gt(&self) -> GtR {
2622 GtR { bits: self._gt() }
2623 }
2624 fn _psc(&self) -> u8 {
2625 const MASK: u8 = 255;
2626 const OFFSET: u8 = 0;
2627 ((self.bits >> OFFSET) & MASK as u32) as u8
2628 }
2629 # [ doc = "Bits 0:7 - Prescaler value" ]
2630 pub fn psc(&self) -> PscR {
2631 PscR { bits: self._psc() }
2632 }
2633 }
2634 impl W {
2635 # [ doc = r" Reset value of the register" ]
2636 pub fn reset_value() -> W {
2637 W { bits: 0 }
2638 }
2639 # [ doc = r" Writes raw `bits` to the register" ]
2640 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
2641 self.bits = bits;
2642 self
2643 }
2644 # [ doc = "Bits 8:15 - Guard time value" ]
2645 pub fn gt(&mut self) -> _GtW {
2646 _GtW { register: self }
2647 }
2648 # [ doc = "Bits 0:7 - Prescaler value" ]
2649 pub fn psc(&mut self) -> _PscW {
2650 _PscW { register: self }
2651 }
2652 }
2653}
2654
2655# [ doc = "Receiver timeout register" ]
2656# [ repr ( C ) ]
2657pub struct Rtor {
2658 register: ::volatile_register::RW<u32>,
2659}
2660
2661# [ doc = "Receiver timeout register" ]
2662pub mod rtor {
2663 # [ doc = r" Value read from the register" ]
2664 pub struct R {
2665 bits: u32,
2666 }
2667 # [ doc = r" Value to write to the register" ]
2668 pub struct W {
2669 bits: u32,
2670 }
2671 impl super::Rtor {
2672 # [ doc = r" Modifies the contents of the register" ]
2673 pub fn modify<F>(&mut self, f: F)
2674 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
2675 {
2676 let bits = self.register.read();
2677 let r = R { bits: bits };
2678 let mut w = W { bits: bits };
2679 f(&r, &mut w);
2680 self.register.write(w.bits);
2681 }
2682 # [ doc = r" Reads the contents of the register" ]
2683 pub fn read(&self) -> R {
2684 R { bits: self.register.read() }
2685 }
2686 # [ doc = r" Writes to the register" ]
2687 pub fn write<F>(&mut self, f: F)
2688 where F: FnOnce(&mut W) -> &mut W
2689 {
2690 let mut w = W::reset_value();
2691 f(&mut w);
2692 self.register.write(w.bits);
2693 }
2694 }
2695 # [ doc = "Value of the field BLEN" ]
2696 pub struct BlenR {
2697 bits: u8,
2698 }
2699 impl BlenR {
2700 # [ doc = r" Value of the field as raw bits" ]
2701 pub fn bits(&self) -> u8 {
2702 self.bits
2703 }
2704 }
2705 # [ doc = "Value of the field RTO" ]
2706 pub struct RtoR {
2707 bits: u32,
2708 }
2709 impl RtoR {
2710 # [ doc = r" Value of the field as raw bits" ]
2711 pub fn bits(&self) -> u32 {
2712 self.bits
2713 }
2714 }
2715 # [ doc = r" Proxy" ]
2716 pub struct _BlenW<'a> {
2717 register: &'a mut W,
2718 }
2719 impl<'a> _BlenW<'a> {
2720 # [ doc = r" Writes raw `bits` to the field" ]
2721 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2722 const MASK: u8 = 255;
2723 const OFFSET: u8 = 24;
2724 self.register.bits &= !((MASK as u32) << OFFSET);
2725 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2726 self.register
2727 }
2728 }
2729 # [ doc = r" Proxy" ]
2730 pub struct _RtoW<'a> {
2731 register: &'a mut W,
2732 }
2733 impl<'a> _RtoW<'a> {
2734 # [ doc = r" Writes raw `bits` to the field" ]
2735 pub unsafe fn bits(self, bits: u32) -> &'a mut W {
2736 const MASK: u32 = 16777215;
2737 const OFFSET: u8 = 0;
2738 self.register.bits &= !((MASK as u32) << OFFSET);
2739 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2740 self.register
2741 }
2742 }
2743 impl R {
2744 # [ doc = r" Value of the register as raw bits" ]
2745 pub fn bits(&self) -> u32 {
2746 self.bits
2747 }
2748 fn _blen(&self) -> u8 {
2749 const MASK: u8 = 255;
2750 const OFFSET: u8 = 24;
2751 ((self.bits >> OFFSET) & MASK as u32) as u8
2752 }
2753 # [ doc = "Bits 24:31 - Block Length" ]
2754 pub fn blen(&self) -> BlenR {
2755 BlenR { bits: self._blen() }
2756 }
2757 fn _rto(&self) -> u32 {
2758 const MASK: u32 = 16777215;
2759 const OFFSET: u8 = 0;
2760 ((self.bits >> OFFSET) & MASK as u32) as u32
2761 }
2762 # [ doc = "Bits 0:23 - Receiver timeout value" ]
2763 pub fn rto(&self) -> RtoR {
2764 RtoR { bits: self._rto() }
2765 }
2766 }
2767 impl W {
2768 # [ doc = r" Reset value of the register" ]
2769 pub fn reset_value() -> W {
2770 W { bits: 0 }
2771 }
2772 # [ doc = r" Writes raw `bits` to the register" ]
2773 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
2774 self.bits = bits;
2775 self
2776 }
2777 # [ doc = "Bits 24:31 - Block Length" ]
2778 pub fn blen(&mut self) -> _BlenW {
2779 _BlenW { register: self }
2780 }
2781 # [ doc = "Bits 0:23 - Receiver timeout value" ]
2782 pub fn rto(&mut self) -> _RtoW {
2783 _RtoW { register: self }
2784 }
2785 }
2786}
2787
2788# [ doc = "Request register" ]
2789# [ repr ( C ) ]
2790pub struct Rqr {
2791 register: ::volatile_register::RW<u32>,
2792}
2793
2794# [ doc = "Request register" ]
2795pub mod rqr {
2796 # [ doc = r" Value read from the register" ]
2797 pub struct R {
2798 bits: u32,
2799 }
2800 # [ doc = r" Value to write to the register" ]
2801 pub struct W {
2802 bits: u32,
2803 }
2804 impl super::Rqr {
2805 # [ doc = r" Modifies the contents of the register" ]
2806 pub fn modify<F>(&mut self, f: F)
2807 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
2808 {
2809 let bits = self.register.read();
2810 let r = R { bits: bits };
2811 let mut w = W { bits: bits };
2812 f(&r, &mut w);
2813 self.register.write(w.bits);
2814 }
2815 # [ doc = r" Reads the contents of the register" ]
2816 pub fn read(&self) -> R {
2817 R { bits: self.register.read() }
2818 }
2819 # [ doc = r" Writes to the register" ]
2820 pub fn write<F>(&mut self, f: F)
2821 where F: FnOnce(&mut W) -> &mut W
2822 {
2823 let mut w = W::reset_value();
2824 f(&mut w);
2825 self.register.write(w.bits);
2826 }
2827 }
2828 # [ doc = "Value of the field TXFRQ" ]
2829 pub struct TxfrqR {
2830 bits: u8,
2831 }
2832 impl TxfrqR {
2833 # [ doc = r" Value of the field as raw bits" ]
2834 pub fn bits(&self) -> u8 {
2835 self.bits
2836 }
2837 }
2838 # [ doc = "Value of the field RXFRQ" ]
2839 pub struct RxfrqR {
2840 bits: u8,
2841 }
2842 impl RxfrqR {
2843 # [ doc = r" Value of the field as raw bits" ]
2844 pub fn bits(&self) -> u8 {
2845 self.bits
2846 }
2847 }
2848 # [ doc = "Value of the field MMRQ" ]
2849 pub struct MmrqR {
2850 bits: u8,
2851 }
2852 impl MmrqR {
2853 # [ doc = r" Value of the field as raw bits" ]
2854 pub fn bits(&self) -> u8 {
2855 self.bits
2856 }
2857 }
2858 # [ doc = "Value of the field SBKRQ" ]
2859 pub struct SbkrqR {
2860 bits: u8,
2861 }
2862 impl SbkrqR {
2863 # [ doc = r" Value of the field as raw bits" ]
2864 pub fn bits(&self) -> u8 {
2865 self.bits
2866 }
2867 }
2868 # [ doc = "Value of the field ABRRQ" ]
2869 pub struct AbrrqR {
2870 bits: u8,
2871 }
2872 impl AbrrqR {
2873 # [ doc = r" Value of the field as raw bits" ]
2874 pub fn bits(&self) -> u8 {
2875 self.bits
2876 }
2877 }
2878 # [ doc = r" Proxy" ]
2879 pub struct _TxfrqW<'a> {
2880 register: &'a mut W,
2881 }
2882 impl<'a> _TxfrqW<'a> {
2883 # [ doc = r" Writes raw `bits` to the field" ]
2884 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2885 const MASK: u8 = 1;
2886 const OFFSET: u8 = 4;
2887 self.register.bits &= !((MASK as u32) << OFFSET);
2888 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2889 self.register
2890 }
2891 }
2892 # [ doc = r" Proxy" ]
2893 pub struct _RxfrqW<'a> {
2894 register: &'a mut W,
2895 }
2896 impl<'a> _RxfrqW<'a> {
2897 # [ doc = r" Writes raw `bits` to the field" ]
2898 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2899 const MASK: u8 = 1;
2900 const OFFSET: u8 = 3;
2901 self.register.bits &= !((MASK as u32) << OFFSET);
2902 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2903 self.register
2904 }
2905 }
2906 # [ doc = r" Proxy" ]
2907 pub struct _MmrqW<'a> {
2908 register: &'a mut W,
2909 }
2910 impl<'a> _MmrqW<'a> {
2911 # [ doc = r" Writes raw `bits` to the field" ]
2912 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2913 const MASK: u8 = 1;
2914 const OFFSET: u8 = 2;
2915 self.register.bits &= !((MASK as u32) << OFFSET);
2916 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2917 self.register
2918 }
2919 }
2920 # [ doc = r" Proxy" ]
2921 pub struct _SbkrqW<'a> {
2922 register: &'a mut W,
2923 }
2924 impl<'a> _SbkrqW<'a> {
2925 # [ doc = r" Writes raw `bits` to the field" ]
2926 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2927 const MASK: u8 = 1;
2928 const OFFSET: u8 = 1;
2929 self.register.bits &= !((MASK as u32) << OFFSET);
2930 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2931 self.register
2932 }
2933 }
2934 # [ doc = r" Proxy" ]
2935 pub struct _AbrrqW<'a> {
2936 register: &'a mut W,
2937 }
2938 impl<'a> _AbrrqW<'a> {
2939 # [ doc = r" Writes raw `bits` to the field" ]
2940 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2941 const MASK: u8 = 1;
2942 const OFFSET: u8 = 0;
2943 self.register.bits &= !((MASK as u32) << OFFSET);
2944 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2945 self.register
2946 }
2947 }
2948 impl R {
2949 # [ doc = r" Value of the register as raw bits" ]
2950 pub fn bits(&self) -> u32 {
2951 self.bits
2952 }
2953 fn _txfrq(&self) -> u8 {
2954 const MASK: u8 = 1;
2955 const OFFSET: u8 = 4;
2956 ((self.bits >> OFFSET) & MASK as u32) as u8
2957 }
2958 # [ doc = "Bit 4 - Transmit data flush request" ]
2959 pub fn txfrq(&self) -> TxfrqR {
2960 TxfrqR { bits: self._txfrq() }
2961 }
2962 fn _rxfrq(&self) -> u8 {
2963 const MASK: u8 = 1;
2964 const OFFSET: u8 = 3;
2965 ((self.bits >> OFFSET) & MASK as u32) as u8
2966 }
2967 # [ doc = "Bit 3 - Receive data flush request" ]
2968 pub fn rxfrq(&self) -> RxfrqR {
2969 RxfrqR { bits: self._rxfrq() }
2970 }
2971 fn _mmrq(&self) -> u8 {
2972 const MASK: u8 = 1;
2973 const OFFSET: u8 = 2;
2974 ((self.bits >> OFFSET) & MASK as u32) as u8
2975 }
2976 # [ doc = "Bit 2 - Mute mode request" ]
2977 pub fn mmrq(&self) -> MmrqR {
2978 MmrqR { bits: self._mmrq() }
2979 }
2980 fn _sbkrq(&self) -> u8 {
2981 const MASK: u8 = 1;
2982 const OFFSET: u8 = 1;
2983 ((self.bits >> OFFSET) & MASK as u32) as u8
2984 }
2985 # [ doc = "Bit 1 - Send break request" ]
2986 pub fn sbkrq(&self) -> SbkrqR {
2987 SbkrqR { bits: self._sbkrq() }
2988 }
2989 fn _abrrq(&self) -> u8 {
2990 const MASK: u8 = 1;
2991 const OFFSET: u8 = 0;
2992 ((self.bits >> OFFSET) & MASK as u32) as u8
2993 }
2994 # [ doc = "Bit 0 - Auto baud rate request" ]
2995 pub fn abrrq(&self) -> AbrrqR {
2996 AbrrqR { bits: self._abrrq() }
2997 }
2998 }
2999 impl W {
3000 # [ doc = r" Reset value of the register" ]
3001 pub fn reset_value() -> W {
3002 W { bits: 0 }
3003 }
3004 # [ doc = r" Writes raw `bits` to the register" ]
3005 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
3006 self.bits = bits;
3007 self
3008 }
3009 # [ doc = "Bit 4 - Transmit data flush request" ]
3010 pub fn txfrq(&mut self) -> _TxfrqW {
3011 _TxfrqW { register: self }
3012 }
3013 # [ doc = "Bit 3 - Receive data flush request" ]
3014 pub fn rxfrq(&mut self) -> _RxfrqW {
3015 _RxfrqW { register: self }
3016 }
3017 # [ doc = "Bit 2 - Mute mode request" ]
3018 pub fn mmrq(&mut self) -> _MmrqW {
3019 _MmrqW { register: self }
3020 }
3021 # [ doc = "Bit 1 - Send break request" ]
3022 pub fn sbkrq(&mut self) -> _SbkrqW {
3023 _SbkrqW { register: self }
3024 }
3025 # [ doc = "Bit 0 - Auto baud rate request" ]
3026 pub fn abrrq(&mut self) -> _AbrrqW {
3027 _AbrrqW { register: self }
3028 }
3029 }
3030}
3031
3032# [ doc = "Interrupt & status register" ]
3033# [ repr ( C ) ]
3034pub struct Isr {
3035 register: ::volatile_register::RO<u32>,
3036}
3037
3038# [ doc = "Interrupt & status register" ]
3039pub mod isr {
3040 # [ doc = r" Value read from the register" ]
3041 pub struct R {
3042 bits: u32,
3043 }
3044 impl super::Isr {
3045 # [ doc = r" Reads the contents of the register" ]
3046 pub fn read(&self) -> R {
3047 R { bits: self.register.read() }
3048 }
3049 }
3050 # [ doc = "Value of the field REACK" ]
3051 pub struct ReackR {
3052 bits: u8,
3053 }
3054 impl ReackR {
3055 # [ doc = r" Value of the field as raw bits" ]
3056 pub fn bits(&self) -> u8 {
3057 self.bits
3058 }
3059 }
3060 # [ doc = "Value of the field TEACK" ]
3061 pub struct TeackR {
3062 bits: u8,
3063 }
3064 impl TeackR {
3065 # [ doc = r" Value of the field as raw bits" ]
3066 pub fn bits(&self) -> u8 {
3067 self.bits
3068 }
3069 }
3070 # [ doc = "Value of the field WUF" ]
3071 pub struct WufR {
3072 bits: u8,
3073 }
3074 impl WufR {
3075 # [ doc = r" Value of the field as raw bits" ]
3076 pub fn bits(&self) -> u8 {
3077 self.bits
3078 }
3079 }
3080 # [ doc = "Value of the field RWU" ]
3081 pub struct RwuR {
3082 bits: u8,
3083 }
3084 impl RwuR {
3085 # [ doc = r" Value of the field as raw bits" ]
3086 pub fn bits(&self) -> u8 {
3087 self.bits
3088 }
3089 }
3090 # [ doc = "Value of the field SBKF" ]
3091 pub struct SbkfR {
3092 bits: u8,
3093 }
3094 impl SbkfR {
3095 # [ doc = r" Value of the field as raw bits" ]
3096 pub fn bits(&self) -> u8 {
3097 self.bits
3098 }
3099 }
3100 # [ doc = "Value of the field CMF" ]
3101 pub struct CmfR {
3102 bits: u8,
3103 }
3104 impl CmfR {
3105 # [ doc = r" Value of the field as raw bits" ]
3106 pub fn bits(&self) -> u8 {
3107 self.bits
3108 }
3109 }
3110 # [ doc = "Value of the field BUSY" ]
3111 pub struct BusyR {
3112 bits: u8,
3113 }
3114 impl BusyR {
3115 # [ doc = r" Value of the field as raw bits" ]
3116 pub fn bits(&self) -> u8 {
3117 self.bits
3118 }
3119 }
3120 # [ doc = "Value of the field ABRF" ]
3121 pub struct AbrfR {
3122 bits: u8,
3123 }
3124 impl AbrfR {
3125 # [ doc = r" Value of the field as raw bits" ]
3126 pub fn bits(&self) -> u8 {
3127 self.bits
3128 }
3129 }
3130 # [ doc = "Value of the field ABRE" ]
3131 pub struct AbreR {
3132 bits: u8,
3133 }
3134 impl AbreR {
3135 # [ doc = r" Value of the field as raw bits" ]
3136 pub fn bits(&self) -> u8 {
3137 self.bits
3138 }
3139 }
3140 # [ doc = "Value of the field EOBF" ]
3141 pub struct EobfR {
3142 bits: u8,
3143 }
3144 impl EobfR {
3145 # [ doc = r" Value of the field as raw bits" ]
3146 pub fn bits(&self) -> u8 {
3147 self.bits
3148 }
3149 }
3150 # [ doc = "Value of the field RTOF" ]
3151 pub struct RtofR {
3152 bits: u8,
3153 }
3154 impl RtofR {
3155 # [ doc = r" Value of the field as raw bits" ]
3156 pub fn bits(&self) -> u8 {
3157 self.bits
3158 }
3159 }
3160 # [ doc = "Value of the field CTS" ]
3161 pub struct CtsR {
3162 bits: u8,
3163 }
3164 impl CtsR {
3165 # [ doc = r" Value of the field as raw bits" ]
3166 pub fn bits(&self) -> u8 {
3167 self.bits
3168 }
3169 }
3170 # [ doc = "Value of the field CTSIF" ]
3171 pub struct CtsifR {
3172 bits: u8,
3173 }
3174 impl CtsifR {
3175 # [ doc = r" Value of the field as raw bits" ]
3176 pub fn bits(&self) -> u8 {
3177 self.bits
3178 }
3179 }
3180 # [ doc = "Value of the field LBDF" ]
3181 pub struct LbdfR {
3182 bits: u8,
3183 }
3184 impl LbdfR {
3185 # [ doc = r" Value of the field as raw bits" ]
3186 pub fn bits(&self) -> u8 {
3187 self.bits
3188 }
3189 }
3190 # [ doc = "Value of the field TXE" ]
3191 pub struct TxeR {
3192 bits: u8,
3193 }
3194 impl TxeR {
3195 # [ doc = r" Value of the field as raw bits" ]
3196 pub fn bits(&self) -> u8 {
3197 self.bits
3198 }
3199 }
3200 # [ doc = "Value of the field TC" ]
3201 pub struct TcR {
3202 bits: u8,
3203 }
3204 impl TcR {
3205 # [ doc = r" Value of the field as raw bits" ]
3206 pub fn bits(&self) -> u8 {
3207 self.bits
3208 }
3209 }
3210 # [ doc = "Value of the field RXNE" ]
3211 pub struct RxneR {
3212 bits: u8,
3213 }
3214 impl RxneR {
3215 # [ doc = r" Value of the field as raw bits" ]
3216 pub fn bits(&self) -> u8 {
3217 self.bits
3218 }
3219 }
3220 # [ doc = "Value of the field IDLE" ]
3221 pub struct IdleR {
3222 bits: u8,
3223 }
3224 impl IdleR {
3225 # [ doc = r" Value of the field as raw bits" ]
3226 pub fn bits(&self) -> u8 {
3227 self.bits
3228 }
3229 }
3230 # [ doc = "Value of the field ORE" ]
3231 pub struct OreR {
3232 bits: u8,
3233 }
3234 impl OreR {
3235 # [ doc = r" Value of the field as raw bits" ]
3236 pub fn bits(&self) -> u8 {
3237 self.bits
3238 }
3239 }
3240 # [ doc = "Value of the field NF" ]
3241 pub struct NfR {
3242 bits: u8,
3243 }
3244 impl NfR {
3245 # [ doc = r" Value of the field as raw bits" ]
3246 pub fn bits(&self) -> u8 {
3247 self.bits
3248 }
3249 }
3250 # [ doc = "Value of the field FE" ]
3251 pub struct FeR {
3252 bits: u8,
3253 }
3254 impl FeR {
3255 # [ doc = r" Value of the field as raw bits" ]
3256 pub fn bits(&self) -> u8 {
3257 self.bits
3258 }
3259 }
3260 # [ doc = "Value of the field PE" ]
3261 pub struct PeR {
3262 bits: u8,
3263 }
3264 impl PeR {
3265 # [ doc = r" Value of the field as raw bits" ]
3266 pub fn bits(&self) -> u8 {
3267 self.bits
3268 }
3269 }
3270 impl R {
3271 # [ doc = r" Value of the register as raw bits" ]
3272 pub fn bits(&self) -> u32 {
3273 self.bits
3274 }
3275 fn _reack(&self) -> u8 {
3276 const MASK: u8 = 1;
3277 const OFFSET: u8 = 22;
3278 ((self.bits >> OFFSET) & MASK as u32) as u8
3279 }
3280 # [ doc = "Bit 22 - Receive enable acknowledge flag" ]
3281 pub fn reack(&self) -> ReackR {
3282 ReackR { bits: self._reack() }
3283 }
3284 fn _teack(&self) -> u8 {
3285 const MASK: u8 = 1;
3286 const OFFSET: u8 = 21;
3287 ((self.bits >> OFFSET) & MASK as u32) as u8
3288 }
3289 # [ doc = "Bit 21 - Transmit enable acknowledge flag" ]
3290 pub fn teack(&self) -> TeackR {
3291 TeackR { bits: self._teack() }
3292 }
3293 fn _wuf(&self) -> u8 {
3294 const MASK: u8 = 1;
3295 const OFFSET: u8 = 20;
3296 ((self.bits >> OFFSET) & MASK as u32) as u8
3297 }
3298 # [ doc = "Bit 20 - Wakeup from Stop mode flag" ]
3299 pub fn wuf(&self) -> WufR {
3300 WufR { bits: self._wuf() }
3301 }
3302 fn _rwu(&self) -> u8 {
3303 const MASK: u8 = 1;
3304 const OFFSET: u8 = 19;
3305 ((self.bits >> OFFSET) & MASK as u32) as u8
3306 }
3307 # [ doc = "Bit 19 - Receiver wakeup from Mute mode" ]
3308 pub fn rwu(&self) -> RwuR {
3309 RwuR { bits: self._rwu() }
3310 }
3311 fn _sbkf(&self) -> u8 {
3312 const MASK: u8 = 1;
3313 const OFFSET: u8 = 18;
3314 ((self.bits >> OFFSET) & MASK as u32) as u8
3315 }
3316 # [ doc = "Bit 18 - Send break flag" ]
3317 pub fn sbkf(&self) -> SbkfR {
3318 SbkfR { bits: self._sbkf() }
3319 }
3320 fn _cmf(&self) -> u8 {
3321 const MASK: u8 = 1;
3322 const OFFSET: u8 = 17;
3323 ((self.bits >> OFFSET) & MASK as u32) as u8
3324 }
3325 # [ doc = "Bit 17 - character match flag" ]
3326 pub fn cmf(&self) -> CmfR {
3327 CmfR { bits: self._cmf() }
3328 }
3329 fn _busy(&self) -> u8 {
3330 const MASK: u8 = 1;
3331 const OFFSET: u8 = 16;
3332 ((self.bits >> OFFSET) & MASK as u32) as u8
3333 }
3334 # [ doc = "Bit 16 - Busy flag" ]
3335 pub fn busy(&self) -> BusyR {
3336 BusyR { bits: self._busy() }
3337 }
3338 fn _abrf(&self) -> u8 {
3339 const MASK: u8 = 1;
3340 const OFFSET: u8 = 15;
3341 ((self.bits >> OFFSET) & MASK as u32) as u8
3342 }
3343 # [ doc = "Bit 15 - Auto baud rate flag" ]
3344 pub fn abrf(&self) -> AbrfR {
3345 AbrfR { bits: self._abrf() }
3346 }
3347 fn _abre(&self) -> u8 {
3348 const MASK: u8 = 1;
3349 const OFFSET: u8 = 14;
3350 ((self.bits >> OFFSET) & MASK as u32) as u8
3351 }
3352 # [ doc = "Bit 14 - Auto baud rate error" ]
3353 pub fn abre(&self) -> AbreR {
3354 AbreR { bits: self._abre() }
3355 }
3356 fn _eobf(&self) -> u8 {
3357 const MASK: u8 = 1;
3358 const OFFSET: u8 = 12;
3359 ((self.bits >> OFFSET) & MASK as u32) as u8
3360 }
3361 # [ doc = "Bit 12 - End of block flag" ]
3362 pub fn eobf(&self) -> EobfR {
3363 EobfR { bits: self._eobf() }
3364 }
3365 fn _rtof(&self) -> u8 {
3366 const MASK: u8 = 1;
3367 const OFFSET: u8 = 11;
3368 ((self.bits >> OFFSET) & MASK as u32) as u8
3369 }
3370 # [ doc = "Bit 11 - Receiver timeout" ]
3371 pub fn rtof(&self) -> RtofR {
3372 RtofR { bits: self._rtof() }
3373 }
3374 fn _cts(&self) -> u8 {
3375 const MASK: u8 = 1;
3376 const OFFSET: u8 = 10;
3377 ((self.bits >> OFFSET) & MASK as u32) as u8
3378 }
3379 # [ doc = "Bit 10 - CTS flag" ]
3380 pub fn cts(&self) -> CtsR {
3381 CtsR { bits: self._cts() }
3382 }
3383 fn _ctsif(&self) -> u8 {
3384 const MASK: u8 = 1;
3385 const OFFSET: u8 = 9;
3386 ((self.bits >> OFFSET) & MASK as u32) as u8
3387 }
3388 # [ doc = "Bit 9 - CTS interrupt flag" ]
3389 pub fn ctsif(&self) -> CtsifR {
3390 CtsifR { bits: self._ctsif() }
3391 }
3392 fn _lbdf(&self) -> u8 {
3393 const MASK: u8 = 1;
3394 const OFFSET: u8 = 8;
3395 ((self.bits >> OFFSET) & MASK as u32) as u8
3396 }
3397 # [ doc = "Bit 8 - LIN break detection flag" ]
3398 pub fn lbdf(&self) -> LbdfR {
3399 LbdfR { bits: self._lbdf() }
3400 }
3401 fn _txe(&self) -> u8 {
3402 const MASK: u8 = 1;
3403 const OFFSET: u8 = 7;
3404 ((self.bits >> OFFSET) & MASK as u32) as u8
3405 }
3406 # [ doc = "Bit 7 - Transmit data register empty" ]
3407 pub fn txe(&self) -> TxeR {
3408 TxeR { bits: self._txe() }
3409 }
3410 fn _tc(&self) -> u8 {
3411 const MASK: u8 = 1;
3412 const OFFSET: u8 = 6;
3413 ((self.bits >> OFFSET) & MASK as u32) as u8
3414 }
3415 # [ doc = "Bit 6 - Transmission complete" ]
3416 pub fn tc(&self) -> TcR {
3417 TcR { bits: self._tc() }
3418 }
3419 fn _rxne(&self) -> u8 {
3420 const MASK: u8 = 1;
3421 const OFFSET: u8 = 5;
3422 ((self.bits >> OFFSET) & MASK as u32) as u8
3423 }
3424 # [ doc = "Bit 5 - Read data register not empty" ]
3425 pub fn rxne(&self) -> RxneR {
3426 RxneR { bits: self._rxne() }
3427 }
3428 fn _idle(&self) -> u8 {
3429 const MASK: u8 = 1;
3430 const OFFSET: u8 = 4;
3431 ((self.bits >> OFFSET) & MASK as u32) as u8
3432 }
3433 # [ doc = "Bit 4 - Idle line detected" ]
3434 pub fn idle(&self) -> IdleR {
3435 IdleR { bits: self._idle() }
3436 }
3437 fn _ore(&self) -> u8 {
3438 const MASK: u8 = 1;
3439 const OFFSET: u8 = 3;
3440 ((self.bits >> OFFSET) & MASK as u32) as u8
3441 }
3442 # [ doc = "Bit 3 - Overrun error" ]
3443 pub fn ore(&self) -> OreR {
3444 OreR { bits: self._ore() }
3445 }
3446 fn _nf(&self) -> u8 {
3447 const MASK: u8 = 1;
3448 const OFFSET: u8 = 2;
3449 ((self.bits >> OFFSET) & MASK as u32) as u8
3450 }
3451 # [ doc = "Bit 2 - Noise detected flag" ]
3452 pub fn nf(&self) -> NfR {
3453 NfR { bits: self._nf() }
3454 }
3455 fn _fe(&self) -> u8 {
3456 const MASK: u8 = 1;
3457 const OFFSET: u8 = 1;
3458 ((self.bits >> OFFSET) & MASK as u32) as u8
3459 }
3460 # [ doc = "Bit 1 - Framing error" ]
3461 pub fn fe(&self) -> FeR {
3462 FeR { bits: self._fe() }
3463 }
3464 fn _pe(&self) -> u8 {
3465 const MASK: u8 = 1;
3466 const OFFSET: u8 = 0;
3467 ((self.bits >> OFFSET) & MASK as u32) as u8
3468 }
3469 # [ doc = "Bit 0 - Parity error" ]
3470 pub fn pe(&self) -> PeR {
3471 PeR { bits: self._pe() }
3472 }
3473 }
3474}
3475
3476# [ doc = "Interrupt flag clear register" ]
3477# [ repr ( C ) ]
3478pub struct Icr {
3479 register: ::volatile_register::RW<u32>,
3480}
3481
3482# [ doc = "Interrupt flag clear register" ]
3483pub mod icr {
3484 # [ doc = r" Value read from the register" ]
3485 pub struct R {
3486 bits: u32,
3487 }
3488 # [ doc = r" Value to write to the register" ]
3489 pub struct W {
3490 bits: u32,
3491 }
3492 impl super::Icr {
3493 # [ doc = r" Modifies the contents of the register" ]
3494 pub fn modify<F>(&mut self, f: F)
3495 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
3496 {
3497 let bits = self.register.read();
3498 let r = R { bits: bits };
3499 let mut w = W { bits: bits };
3500 f(&r, &mut w);
3501 self.register.write(w.bits);
3502 }
3503 # [ doc = r" Reads the contents of the register" ]
3504 pub fn read(&self) -> R {
3505 R { bits: self.register.read() }
3506 }
3507 # [ doc = r" Writes to the register" ]
3508 pub fn write<F>(&mut self, f: F)
3509 where F: FnOnce(&mut W) -> &mut W
3510 {
3511 let mut w = W::reset_value();
3512 f(&mut w);
3513 self.register.write(w.bits);
3514 }
3515 }
3516 # [ doc = "Value of the field WUCF" ]
3517 pub struct WucfR {
3518 bits: u8,
3519 }
3520 impl WucfR {
3521 # [ doc = r" Value of the field as raw bits" ]
3522 pub fn bits(&self) -> u8 {
3523 self.bits
3524 }
3525 }
3526 # [ doc = "Value of the field CMCF" ]
3527 pub struct CmcfR {
3528 bits: u8,
3529 }
3530 impl CmcfR {
3531 # [ doc = r" Value of the field as raw bits" ]
3532 pub fn bits(&self) -> u8 {
3533 self.bits
3534 }
3535 }
3536 # [ doc = "Value of the field EOBCF" ]
3537 pub struct EobcfR {
3538 bits: u8,
3539 }
3540 impl EobcfR {
3541 # [ doc = r" Value of the field as raw bits" ]
3542 pub fn bits(&self) -> u8 {
3543 self.bits
3544 }
3545 }
3546 # [ doc = "Value of the field RTOCF" ]
3547 pub struct RtocfR {
3548 bits: u8,
3549 }
3550 impl RtocfR {
3551 # [ doc = r" Value of the field as raw bits" ]
3552 pub fn bits(&self) -> u8 {
3553 self.bits
3554 }
3555 }
3556 # [ doc = "Value of the field CTSCF" ]
3557 pub struct CtscfR {
3558 bits: u8,
3559 }
3560 impl CtscfR {
3561 # [ doc = r" Value of the field as raw bits" ]
3562 pub fn bits(&self) -> u8 {
3563 self.bits
3564 }
3565 }
3566 # [ doc = "Value of the field LBDCF" ]
3567 pub struct LbdcfR {
3568 bits: u8,
3569 }
3570 impl LbdcfR {
3571 # [ doc = r" Value of the field as raw bits" ]
3572 pub fn bits(&self) -> u8 {
3573 self.bits
3574 }
3575 }
3576 # [ doc = "Value of the field TCCF" ]
3577 pub struct TccfR {
3578 bits: u8,
3579 }
3580 impl TccfR {
3581 # [ doc = r" Value of the field as raw bits" ]
3582 pub fn bits(&self) -> u8 {
3583 self.bits
3584 }
3585 }
3586 # [ doc = "Value of the field IDLECF" ]
3587 pub struct IdlecfR {
3588 bits: u8,
3589 }
3590 impl IdlecfR {
3591 # [ doc = r" Value of the field as raw bits" ]
3592 pub fn bits(&self) -> u8 {
3593 self.bits
3594 }
3595 }
3596 # [ doc = "Value of the field ORECF" ]
3597 pub struct OrecfR {
3598 bits: u8,
3599 }
3600 impl OrecfR {
3601 # [ doc = r" Value of the field as raw bits" ]
3602 pub fn bits(&self) -> u8 {
3603 self.bits
3604 }
3605 }
3606 # [ doc = "Value of the field NCF" ]
3607 pub struct NcfR {
3608 bits: u8,
3609 }
3610 impl NcfR {
3611 # [ doc = r" Value of the field as raw bits" ]
3612 pub fn bits(&self) -> u8 {
3613 self.bits
3614 }
3615 }
3616 # [ doc = "Value of the field FECF" ]
3617 pub struct FecfR {
3618 bits: u8,
3619 }
3620 impl FecfR {
3621 # [ doc = r" Value of the field as raw bits" ]
3622 pub fn bits(&self) -> u8 {
3623 self.bits
3624 }
3625 }
3626 # [ doc = "Value of the field PECF" ]
3627 pub struct PecfR {
3628 bits: u8,
3629 }
3630 impl PecfR {
3631 # [ doc = r" Value of the field as raw bits" ]
3632 pub fn bits(&self) -> u8 {
3633 self.bits
3634 }
3635 }
3636 # [ doc = r" Proxy" ]
3637 pub struct _WucfW<'a> {
3638 register: &'a mut W,
3639 }
3640 impl<'a> _WucfW<'a> {
3641 # [ doc = r" Writes raw `bits` to the field" ]
3642 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3643 const MASK: u8 = 1;
3644 const OFFSET: u8 = 20;
3645 self.register.bits &= !((MASK as u32) << OFFSET);
3646 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3647 self.register
3648 }
3649 }
3650 # [ doc = r" Proxy" ]
3651 pub struct _CmcfW<'a> {
3652 register: &'a mut W,
3653 }
3654 impl<'a> _CmcfW<'a> {
3655 # [ doc = r" Writes raw `bits` to the field" ]
3656 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3657 const MASK: u8 = 1;
3658 const OFFSET: u8 = 17;
3659 self.register.bits &= !((MASK as u32) << OFFSET);
3660 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3661 self.register
3662 }
3663 }
3664 # [ doc = r" Proxy" ]
3665 pub struct _EobcfW<'a> {
3666 register: &'a mut W,
3667 }
3668 impl<'a> _EobcfW<'a> {
3669 # [ doc = r" Writes raw `bits` to the field" ]
3670 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3671 const MASK: u8 = 1;
3672 const OFFSET: u8 = 12;
3673 self.register.bits &= !((MASK as u32) << OFFSET);
3674 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3675 self.register
3676 }
3677 }
3678 # [ doc = r" Proxy" ]
3679 pub struct _RtocfW<'a> {
3680 register: &'a mut W,
3681 }
3682 impl<'a> _RtocfW<'a> {
3683 # [ doc = r" Writes raw `bits` to the field" ]
3684 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3685 const MASK: u8 = 1;
3686 const OFFSET: u8 = 11;
3687 self.register.bits &= !((MASK as u32) << OFFSET);
3688 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3689 self.register
3690 }
3691 }
3692 # [ doc = r" Proxy" ]
3693 pub struct _CtscfW<'a> {
3694 register: &'a mut W,
3695 }
3696 impl<'a> _CtscfW<'a> {
3697 # [ doc = r" Writes raw `bits` to the field" ]
3698 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3699 const MASK: u8 = 1;
3700 const OFFSET: u8 = 9;
3701 self.register.bits &= !((MASK as u32) << OFFSET);
3702 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3703 self.register
3704 }
3705 }
3706 # [ doc = r" Proxy" ]
3707 pub struct _LbdcfW<'a> {
3708 register: &'a mut W,
3709 }
3710 impl<'a> _LbdcfW<'a> {
3711 # [ doc = r" Writes raw `bits` to the field" ]
3712 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3713 const MASK: u8 = 1;
3714 const OFFSET: u8 = 8;
3715 self.register.bits &= !((MASK as u32) << OFFSET);
3716 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3717 self.register
3718 }
3719 }
3720 # [ doc = r" Proxy" ]
3721 pub struct _TccfW<'a> {
3722 register: &'a mut W,
3723 }
3724 impl<'a> _TccfW<'a> {
3725 # [ doc = r" Writes raw `bits` to the field" ]
3726 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3727 const MASK: u8 = 1;
3728 const OFFSET: u8 = 6;
3729 self.register.bits &= !((MASK as u32) << OFFSET);
3730 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3731 self.register
3732 }
3733 }
3734 # [ doc = r" Proxy" ]
3735 pub struct _IdlecfW<'a> {
3736 register: &'a mut W,
3737 }
3738 impl<'a> _IdlecfW<'a> {
3739 # [ doc = r" Writes raw `bits` to the field" ]
3740 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3741 const MASK: u8 = 1;
3742 const OFFSET: u8 = 4;
3743 self.register.bits &= !((MASK as u32) << OFFSET);
3744 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3745 self.register
3746 }
3747 }
3748 # [ doc = r" Proxy" ]
3749 pub struct _OrecfW<'a> {
3750 register: &'a mut W,
3751 }
3752 impl<'a> _OrecfW<'a> {
3753 # [ doc = r" Writes raw `bits` to the field" ]
3754 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3755 const MASK: u8 = 1;
3756 const OFFSET: u8 = 3;
3757 self.register.bits &= !((MASK as u32) << OFFSET);
3758 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3759 self.register
3760 }
3761 }
3762 # [ doc = r" Proxy" ]
3763 pub struct _NcfW<'a> {
3764 register: &'a mut W,
3765 }
3766 impl<'a> _NcfW<'a> {
3767 # [ doc = r" Writes raw `bits` to the field" ]
3768 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3769 const MASK: u8 = 1;
3770 const OFFSET: u8 = 2;
3771 self.register.bits &= !((MASK as u32) << OFFSET);
3772 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3773 self.register
3774 }
3775 }
3776 # [ doc = r" Proxy" ]
3777 pub struct _FecfW<'a> {
3778 register: &'a mut W,
3779 }
3780 impl<'a> _FecfW<'a> {
3781 # [ doc = r" Writes raw `bits` to the field" ]
3782 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3783 const MASK: u8 = 1;
3784 const OFFSET: u8 = 1;
3785 self.register.bits &= !((MASK as u32) << OFFSET);
3786 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3787 self.register
3788 }
3789 }
3790 # [ doc = r" Proxy" ]
3791 pub struct _PecfW<'a> {
3792 register: &'a mut W,
3793 }
3794 impl<'a> _PecfW<'a> {
3795 # [ doc = r" Writes raw `bits` to the field" ]
3796 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3797 const MASK: u8 = 1;
3798 const OFFSET: u8 = 0;
3799 self.register.bits &= !((MASK as u32) << OFFSET);
3800 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3801 self.register
3802 }
3803 }
3804 impl R {
3805 # [ doc = r" Value of the register as raw bits" ]
3806 pub fn bits(&self) -> u32 {
3807 self.bits
3808 }
3809 fn _wucf(&self) -> u8 {
3810 const MASK: u8 = 1;
3811 const OFFSET: u8 = 20;
3812 ((self.bits >> OFFSET) & MASK as u32) as u8
3813 }
3814 # [ doc = "Bit 20 - Wakeup from Stop mode clear flag" ]
3815 pub fn wucf(&self) -> WucfR {
3816 WucfR { bits: self._wucf() }
3817 }
3818 fn _cmcf(&self) -> u8 {
3819 const MASK: u8 = 1;
3820 const OFFSET: u8 = 17;
3821 ((self.bits >> OFFSET) & MASK as u32) as u8
3822 }
3823 # [ doc = "Bit 17 - Character match clear flag" ]
3824 pub fn cmcf(&self) -> CmcfR {
3825 CmcfR { bits: self._cmcf() }
3826 }
3827 fn _eobcf(&self) -> u8 {
3828 const MASK: u8 = 1;
3829 const OFFSET: u8 = 12;
3830 ((self.bits >> OFFSET) & MASK as u32) as u8
3831 }
3832 # [ doc = "Bit 12 - End of timeout clear flag" ]
3833 pub fn eobcf(&self) -> EobcfR {
3834 EobcfR { bits: self._eobcf() }
3835 }
3836 fn _rtocf(&self) -> u8 {
3837 const MASK: u8 = 1;
3838 const OFFSET: u8 = 11;
3839 ((self.bits >> OFFSET) & MASK as u32) as u8
3840 }
3841 # [ doc = "Bit 11 - Receiver timeout clear flag" ]
3842 pub fn rtocf(&self) -> RtocfR {
3843 RtocfR { bits: self._rtocf() }
3844 }
3845 fn _ctscf(&self) -> u8 {
3846 const MASK: u8 = 1;
3847 const OFFSET: u8 = 9;
3848 ((self.bits >> OFFSET) & MASK as u32) as u8
3849 }
3850 # [ doc = "Bit 9 - CTS clear flag" ]
3851 pub fn ctscf(&self) -> CtscfR {
3852 CtscfR { bits: self._ctscf() }
3853 }
3854 fn _lbdcf(&self) -> u8 {
3855 const MASK: u8 = 1;
3856 const OFFSET: u8 = 8;
3857 ((self.bits >> OFFSET) & MASK as u32) as u8
3858 }
3859 # [ doc = "Bit 8 - LIN break detection clear flag" ]
3860 pub fn lbdcf(&self) -> LbdcfR {
3861 LbdcfR { bits: self._lbdcf() }
3862 }
3863 fn _tccf(&self) -> u8 {
3864 const MASK: u8 = 1;
3865 const OFFSET: u8 = 6;
3866 ((self.bits >> OFFSET) & MASK as u32) as u8
3867 }
3868 # [ doc = "Bit 6 - Transmission complete clear flag" ]
3869 pub fn tccf(&self) -> TccfR {
3870 TccfR { bits: self._tccf() }
3871 }
3872 fn _idlecf(&self) -> u8 {
3873 const MASK: u8 = 1;
3874 const OFFSET: u8 = 4;
3875 ((self.bits >> OFFSET) & MASK as u32) as u8
3876 }
3877 # [ doc = "Bit 4 - Idle line detected clear flag" ]
3878 pub fn idlecf(&self) -> IdlecfR {
3879 IdlecfR { bits: self._idlecf() }
3880 }
3881 fn _orecf(&self) -> u8 {
3882 const MASK: u8 = 1;
3883 const OFFSET: u8 = 3;
3884 ((self.bits >> OFFSET) & MASK as u32) as u8
3885 }
3886 # [ doc = "Bit 3 - Overrun error clear flag" ]
3887 pub fn orecf(&self) -> OrecfR {
3888 OrecfR { bits: self._orecf() }
3889 }
3890 fn _ncf(&self) -> u8 {
3891 const MASK: u8 = 1;
3892 const OFFSET: u8 = 2;
3893 ((self.bits >> OFFSET) & MASK as u32) as u8
3894 }
3895 # [ doc = "Bit 2 - Noise detected clear flag" ]
3896 pub fn ncf(&self) -> NcfR {
3897 NcfR { bits: self._ncf() }
3898 }
3899 fn _fecf(&self) -> u8 {
3900 const MASK: u8 = 1;
3901 const OFFSET: u8 = 1;
3902 ((self.bits >> OFFSET) & MASK as u32) as u8
3903 }
3904 # [ doc = "Bit 1 - Framing error clear flag" ]
3905 pub fn fecf(&self) -> FecfR {
3906 FecfR { bits: self._fecf() }
3907 }
3908 fn _pecf(&self) -> u8 {
3909 const MASK: u8 = 1;
3910 const OFFSET: u8 = 0;
3911 ((self.bits >> OFFSET) & MASK as u32) as u8
3912 }
3913 # [ doc = "Bit 0 - Parity error clear flag" ]
3914 pub fn pecf(&self) -> PecfR {
3915 PecfR { bits: self._pecf() }
3916 }
3917 }
3918 impl W {
3919 # [ doc = r" Reset value of the register" ]
3920 pub fn reset_value() -> W {
3921 W { bits: 0 }
3922 }
3923 # [ doc = r" Writes raw `bits` to the register" ]
3924 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
3925 self.bits = bits;
3926 self
3927 }
3928 # [ doc = "Bit 20 - Wakeup from Stop mode clear flag" ]
3929 pub fn wucf(&mut self) -> _WucfW {
3930 _WucfW { register: self }
3931 }
3932 # [ doc = "Bit 17 - Character match clear flag" ]
3933 pub fn cmcf(&mut self) -> _CmcfW {
3934 _CmcfW { register: self }
3935 }
3936 # [ doc = "Bit 12 - End of timeout clear flag" ]
3937 pub fn eobcf(&mut self) -> _EobcfW {
3938 _EobcfW { register: self }
3939 }
3940 # [ doc = "Bit 11 - Receiver timeout clear flag" ]
3941 pub fn rtocf(&mut self) -> _RtocfW {
3942 _RtocfW { register: self }
3943 }
3944 # [ doc = "Bit 9 - CTS clear flag" ]
3945 pub fn ctscf(&mut self) -> _CtscfW {
3946 _CtscfW { register: self }
3947 }
3948 # [ doc = "Bit 8 - LIN break detection clear flag" ]
3949 pub fn lbdcf(&mut self) -> _LbdcfW {
3950 _LbdcfW { register: self }
3951 }
3952 # [ doc = "Bit 6 - Transmission complete clear flag" ]
3953 pub fn tccf(&mut self) -> _TccfW {
3954 _TccfW { register: self }
3955 }
3956 # [ doc = "Bit 4 - Idle line detected clear flag" ]
3957 pub fn idlecf(&mut self) -> _IdlecfW {
3958 _IdlecfW { register: self }
3959 }
3960 # [ doc = "Bit 3 - Overrun error clear flag" ]
3961 pub fn orecf(&mut self) -> _OrecfW {
3962 _OrecfW { register: self }
3963 }
3964 # [ doc = "Bit 2 - Noise detected clear flag" ]
3965 pub fn ncf(&mut self) -> _NcfW {
3966 _NcfW { register: self }
3967 }
3968 # [ doc = "Bit 1 - Framing error clear flag" ]
3969 pub fn fecf(&mut self) -> _FecfW {
3970 _FecfW { register: self }
3971 }
3972 # [ doc = "Bit 0 - Parity error clear flag" ]
3973 pub fn pecf(&mut self) -> _PecfW {
3974 _PecfW { register: self }
3975 }
3976 }
3977}
3978
3979# [ doc = "Receive data register" ]
3980# [ repr ( C ) ]
3981pub struct Rdr {
3982 register: ::volatile_register::RO<u32>,
3983}
3984
3985# [ doc = "Receive data register" ]
3986pub mod rdr {
3987 # [ doc = r" Value read from the register" ]
3988 pub struct R {
3989 bits: u32,
3990 }
3991 impl super::Rdr {
3992 # [ doc = r" Reads the contents of the register" ]
3993 pub fn read(&self) -> R {
3994 R { bits: self.register.read() }
3995 }
3996 }
3997 # [ doc = "Value of the field RDR" ]
3998 pub struct RdrR {
3999 bits: u16,
4000 }
4001 impl RdrR {
4002 # [ doc = r" Value of the field as raw bits" ]
4003 pub fn bits(&self) -> u16 {
4004 self.bits
4005 }
4006 }
4007 impl R {
4008 # [ doc = r" Value of the register as raw bits" ]
4009 pub fn bits(&self) -> u32 {
4010 self.bits
4011 }
4012 fn _rdr(&self) -> u16 {
4013 const MASK: u16 = 511;
4014 const OFFSET: u8 = 0;
4015 ((self.bits >> OFFSET) & MASK as u32) as u16
4016 }
4017 # [ doc = "Bits 0:8 - Receive data value" ]
4018 pub fn rdr(&self) -> RdrR {
4019 RdrR { bits: self._rdr() }
4020 }
4021 }
4022}
4023
4024# [ doc = "Transmit data register" ]
4025# [ repr ( C ) ]
4026pub struct Tdr {
4027 register: ::volatile_register::RW<u32>,
4028}
4029
4030# [ doc = "Transmit data register" ]
4031pub mod tdr {
4032 # [ doc = r" Value read from the register" ]
4033 pub struct R {
4034 bits: u32,
4035 }
4036 # [ doc = r" Value to write to the register" ]
4037 pub struct W {
4038 bits: u32,
4039 }
4040 impl super::Tdr {
4041 # [ doc = r" Modifies the contents of the register" ]
4042 pub fn modify<F>(&mut self, f: F)
4043 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
4044 {
4045 let bits = self.register.read();
4046 let r = R { bits: bits };
4047 let mut w = W { bits: bits };
4048 f(&r, &mut w);
4049 self.register.write(w.bits);
4050 }
4051 # [ doc = r" Reads the contents of the register" ]
4052 pub fn read(&self) -> R {
4053 R { bits: self.register.read() }
4054 }
4055 # [ doc = r" Writes to the register" ]
4056 pub fn write<F>(&mut self, f: F)
4057 where F: FnOnce(&mut W) -> &mut W
4058 {
4059 let mut w = W::reset_value();
4060 f(&mut w);
4061 self.register.write(w.bits);
4062 }
4063 }
4064 # [ doc = "Value of the field TDR" ]
4065 pub struct TdrR {
4066 bits: u16,
4067 }
4068 impl TdrR {
4069 # [ doc = r" Value of the field as raw bits" ]
4070 pub fn bits(&self) -> u16 {
4071 self.bits
4072 }
4073 }
4074 # [ doc = r" Proxy" ]
4075 pub struct _TdrW<'a> {
4076 register: &'a mut W,
4077 }
4078 impl<'a> _TdrW<'a> {
4079 # [ doc = r" Writes raw `bits` to the field" ]
4080 pub unsafe fn bits(self, bits: u16) -> &'a mut W {
4081 const MASK: u16 = 511;
4082 const OFFSET: u8 = 0;
4083 self.register.bits &= !((MASK as u32) << OFFSET);
4084 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4085 self.register
4086 }
4087 }
4088 impl R {
4089 # [ doc = r" Value of the register as raw bits" ]
4090 pub fn bits(&self) -> u32 {
4091 self.bits
4092 }
4093 fn _tdr(&self) -> u16 {
4094 const MASK: u16 = 511;
4095 const OFFSET: u8 = 0;
4096 ((self.bits >> OFFSET) & MASK as u32) as u16
4097 }
4098 # [ doc = "Bits 0:8 - Transmit data value" ]
4099 pub fn tdr(&self) -> TdrR {
4100 TdrR { bits: self._tdr() }
4101 }
4102 }
4103 impl W {
4104 # [ doc = r" Reset value of the register" ]
4105 pub fn reset_value() -> W {
4106 W { bits: 0 }
4107 }
4108 # [ doc = r" Writes raw `bits` to the register" ]
4109 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
4110 self.bits = bits;
4111 self
4112 }
4113 # [ doc = "Bits 0:8 - Transmit data value" ]
4114 pub fn tdr(&mut self) -> _TdrW {
4115 _TdrW { register: self }
4116 }
4117 }
4118}