1# ! [ doc = "General-purpose-timers" ]
2# [ doc = r" Register block" ]
3# [ repr ( C ) ]
4pub struct GpTim {
5 # [ doc = "0x00 - control register 1" ]
6 pub cr1: Cr1,
7 # [ doc = "0x04 - control register 2" ]
8 pub cr2: Cr2,
9 # [ doc = "0x08 - slave mode control register" ]
10 pub smcr: Smcr,
11 # [ doc = "0x0c - DMA/Interrupt enable register" ]
12 pub dier: Dier,
13 # [ doc = "0x10 - status register" ]
14 pub sr: Sr,
15 # [ doc = "0x14 - event generation register" ]
16 pub egr: Egr,
17 # [ doc = "0x18 - capture/compare mode register 1 (output mode)" ]
18 pub ccmr1_output: Ccmr1Output,
19 # [ doc = "0x1c - capture/compare mode register 2 (output mode)" ]
20 pub ccmr2_output: Ccmr2Output,
21 # [ doc = "0x20 - capture/compare enable register" ]
22 pub ccer: Ccer,
23 # [ doc = "0x24 - counter" ]
24 pub cnt: Cnt,
25 # [ doc = "0x28 - prescaler" ]
26 pub psc: Psc,
27 # [ doc = "0x2c - auto-reload register" ]
28 pub arr: Arr,
29 _reserved0: [u8; 4usize],
30 # [ doc = "0x34 - capture/compare register 1" ]
31 pub ccr1: Ccr1,
32 # [ doc = "0x38 - capture/compare register 2" ]
33 pub ccr2: Ccr2,
34 # [ doc = "0x3c - capture/compare register 3" ]
35 pub ccr3: Ccr3,
36 # [ doc = "0x40 - capture/compare register 4" ]
37 pub ccr4: Ccr4,
38 _reserved1: [u8; 4usize],
39 # [ doc = "0x48 - DMA control register" ]
40 pub dcr: Dcr,
41 # [ doc = "0x4c - DMA address for full transfer" ]
42 pub dmar: Dmar,
43}
44
45# [ doc = "control register 1" ]
46# [ repr ( C ) ]
47pub struct Cr1 {
48 register: ::volatile_register::RW<u32>,
49}
50
51# [ doc = "control register 1" ]
52pub mod cr1 {
53 # [ doc = r" Value read from the register" ]
54 pub struct R {
55 bits: u32,
56 }
57 # [ doc = r" Value to write to the register" ]
58 pub struct W {
59 bits: u32,
60 }
61 impl super::Cr1 {
62 # [ doc = r" Modifies the contents of the register" ]
63 pub fn modify<F>(&mut self, f: F)
64 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
65 {
66 let bits = self.register.read();
67 let r = R { bits: bits };
68 let mut w = W { bits: bits };
69 f(&r, &mut w);
70 self.register.write(w.bits);
71 }
72 # [ doc = r" Reads the contents of the register" ]
73 pub fn read(&self) -> R {
74 R { bits: self.register.read() }
75 }
76 # [ doc = r" Writes to the register" ]
77 pub fn write<F>(&mut self, f: F)
78 where F: FnOnce(&mut W) -> &mut W
79 {
80 let mut w = W::reset_value();
81 f(&mut w);
82 self.register.write(w.bits);
83 }
84 }
85 # [ doc = "Value of the field CKD" ]
86 pub struct CkdR {
87 bits: u8,
88 }
89 impl CkdR {
90 # [ doc = r" Value of the field as raw bits" ]
91 pub fn bits(&self) -> u8 {
92 self.bits
93 }
94 }
95 # [ doc = "Value of the field ARPE" ]
96 pub struct ArpeR {
97 bits: u8,
98 }
99 impl ArpeR {
100 # [ doc = r" Value of the field as raw bits" ]
101 pub fn bits(&self) -> u8 {
102 self.bits
103 }
104 }
105 # [ doc = "Value of the field CMS" ]
106 pub struct CmsR {
107 bits: u8,
108 }
109 impl CmsR {
110 # [ doc = r" Value of the field as raw bits" ]
111 pub fn bits(&self) -> u8 {
112 self.bits
113 }
114 }
115 # [ doc = "Value of the field DIR" ]
116 pub struct DirR {
117 bits: u8,
118 }
119 impl DirR {
120 # [ doc = r" Value of the field as raw bits" ]
121 pub fn bits(&self) -> u8 {
122 self.bits
123 }
124 }
125 # [ doc = "Value of the field OPM" ]
126 pub struct OpmR {
127 bits: u8,
128 }
129 impl OpmR {
130 # [ doc = r" Value of the field as raw bits" ]
131 pub fn bits(&self) -> u8 {
132 self.bits
133 }
134 }
135 # [ doc = "Value of the field URS" ]
136 pub struct UrsR {
137 bits: u8,
138 }
139 impl UrsR {
140 # [ doc = r" Value of the field as raw bits" ]
141 pub fn bits(&self) -> u8 {
142 self.bits
143 }
144 }
145 # [ doc = "Value of the field UDIS" ]
146 pub struct UdisR {
147 bits: u8,
148 }
149 impl UdisR {
150 # [ doc = r" Value of the field as raw bits" ]
151 pub fn bits(&self) -> u8 {
152 self.bits
153 }
154 }
155 # [ doc = "Value of the field CEN" ]
156 pub struct CenR {
157 bits: u8,
158 }
159 impl CenR {
160 # [ doc = r" Value of the field as raw bits" ]
161 pub fn bits(&self) -> u8 {
162 self.bits
163 }
164 }
165 # [ doc = r" Proxy" ]
166 pub struct _CkdW<'a> {
167 register: &'a mut W,
168 }
169 impl<'a> _CkdW<'a> {
170 # [ doc = r" Writes raw `bits` to the field" ]
171 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
172 const MASK: u8 = 3;
173 const OFFSET: u8 = 8;
174 self.register.bits &= !((MASK as u32) << OFFSET);
175 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
176 self.register
177 }
178 }
179 # [ doc = r" Proxy" ]
180 pub struct _ArpeW<'a> {
181 register: &'a mut W,
182 }
183 impl<'a> _ArpeW<'a> {
184 # [ doc = r" Writes raw `bits` to the field" ]
185 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
186 const MASK: u8 = 1;
187 const OFFSET: u8 = 7;
188 self.register.bits &= !((MASK as u32) << OFFSET);
189 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
190 self.register
191 }
192 }
193 # [ doc = r" Proxy" ]
194 pub struct _CmsW<'a> {
195 register: &'a mut W,
196 }
197 impl<'a> _CmsW<'a> {
198 # [ doc = r" Writes raw `bits` to the field" ]
199 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
200 const MASK: u8 = 3;
201 const OFFSET: u8 = 5;
202 self.register.bits &= !((MASK as u32) << OFFSET);
203 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
204 self.register
205 }
206 }
207 # [ doc = r" Proxy" ]
208 pub struct _DirW<'a> {
209 register: &'a mut W,
210 }
211 impl<'a> _DirW<'a> {
212 # [ doc = r" Writes raw `bits` to the field" ]
213 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
214 const MASK: u8 = 1;
215 const OFFSET: u8 = 4;
216 self.register.bits &= !((MASK as u32) << OFFSET);
217 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
218 self.register
219 }
220 }
221 # [ doc = r" Proxy" ]
222 pub struct _OpmW<'a> {
223 register: &'a mut W,
224 }
225 impl<'a> _OpmW<'a> {
226 # [ doc = r" Writes raw `bits` to the field" ]
227 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
228 const MASK: u8 = 1;
229 const OFFSET: u8 = 3;
230 self.register.bits &= !((MASK as u32) << OFFSET);
231 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
232 self.register
233 }
234 }
235 # [ doc = r" Proxy" ]
236 pub struct _UrsW<'a> {
237 register: &'a mut W,
238 }
239 impl<'a> _UrsW<'a> {
240 # [ doc = r" Writes raw `bits` to the field" ]
241 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
242 const MASK: u8 = 1;
243 const OFFSET: u8 = 2;
244 self.register.bits &= !((MASK as u32) << OFFSET);
245 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
246 self.register
247 }
248 }
249 # [ doc = r" Proxy" ]
250 pub struct _UdisW<'a> {
251 register: &'a mut W,
252 }
253 impl<'a> _UdisW<'a> {
254 # [ doc = r" Writes raw `bits` to the field" ]
255 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
256 const MASK: u8 = 1;
257 const OFFSET: u8 = 1;
258 self.register.bits &= !((MASK as u32) << OFFSET);
259 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
260 self.register
261 }
262 }
263 # [ doc = r" Proxy" ]
264 pub struct _CenW<'a> {
265 register: &'a mut W,
266 }
267 impl<'a> _CenW<'a> {
268 # [ doc = r" Writes raw `bits` to the field" ]
269 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
270 const MASK: u8 = 1;
271 const OFFSET: u8 = 0;
272 self.register.bits &= !((MASK as u32) << OFFSET);
273 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
274 self.register
275 }
276 }
277 impl R {
278 # [ doc = r" Value of the register as raw bits" ]
279 pub fn bits(&self) -> u32 {
280 self.bits
281 }
282 fn _ckd(&self) -> u8 {
283 const MASK: u8 = 3;
284 const OFFSET: u8 = 8;
285 ((self.bits >> OFFSET) & MASK as u32) as u8
286 }
287 # [ doc = "Bits 8:9 - Clock division" ]
288 pub fn ckd(&self) -> CkdR {
289 CkdR { bits: self._ckd() }
290 }
291 fn _arpe(&self) -> u8 {
292 const MASK: u8 = 1;
293 const OFFSET: u8 = 7;
294 ((self.bits >> OFFSET) & MASK as u32) as u8
295 }
296 # [ doc = "Bit 7 - Auto-reload preload enable" ]
297 pub fn arpe(&self) -> ArpeR {
298 ArpeR { bits: self._arpe() }
299 }
300 fn _cms(&self) -> u8 {
301 const MASK: u8 = 3;
302 const OFFSET: u8 = 5;
303 ((self.bits >> OFFSET) & MASK as u32) as u8
304 }
305 # [ doc = "Bits 5:6 - Center-aligned mode selection" ]
306 pub fn cms(&self) -> CmsR {
307 CmsR { bits: self._cms() }
308 }
309 fn _dir(&self) -> u8 {
310 const MASK: u8 = 1;
311 const OFFSET: u8 = 4;
312 ((self.bits >> OFFSET) & MASK as u32) as u8
313 }
314 # [ doc = "Bit 4 - Direction" ]
315 pub fn dir(&self) -> DirR {
316 DirR { bits: self._dir() }
317 }
318 fn _opm(&self) -> u8 {
319 const MASK: u8 = 1;
320 const OFFSET: u8 = 3;
321 ((self.bits >> OFFSET) & MASK as u32) as u8
322 }
323 # [ doc = "Bit 3 - One-pulse mode" ]
324 pub fn opm(&self) -> OpmR {
325 OpmR { bits: self._opm() }
326 }
327 fn _urs(&self) -> u8 {
328 const MASK: u8 = 1;
329 const OFFSET: u8 = 2;
330 ((self.bits >> OFFSET) & MASK as u32) as u8
331 }
332 # [ doc = "Bit 2 - Update request source" ]
333 pub fn urs(&self) -> UrsR {
334 UrsR { bits: self._urs() }
335 }
336 fn _udis(&self) -> u8 {
337 const MASK: u8 = 1;
338 const OFFSET: u8 = 1;
339 ((self.bits >> OFFSET) & MASK as u32) as u8
340 }
341 # [ doc = "Bit 1 - Update disable" ]
342 pub fn udis(&self) -> UdisR {
343 UdisR { bits: self._udis() }
344 }
345 fn _cen(&self) -> u8 {
346 const MASK: u8 = 1;
347 const OFFSET: u8 = 0;
348 ((self.bits >> OFFSET) & MASK as u32) as u8
349 }
350 # [ doc = "Bit 0 - Counter enable" ]
351 pub fn cen(&self) -> CenR {
352 CenR { bits: self._cen() }
353 }
354 }
355 impl W {
356 # [ doc = r" Reset value of the register" ]
357 pub fn reset_value() -> W {
358 W { bits: 0 }
359 }
360 # [ doc = r" Writes raw `bits` to the register" ]
361 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
362 self.bits = bits;
363 self
364 }
365 # [ doc = "Bits 8:9 - Clock division" ]
366 pub fn ckd(&mut self) -> _CkdW {
367 _CkdW { register: self }
368 }
369 # [ doc = "Bit 7 - Auto-reload preload enable" ]
370 pub fn arpe(&mut self) -> _ArpeW {
371 _ArpeW { register: self }
372 }
373 # [ doc = "Bits 5:6 - Center-aligned mode selection" ]
374 pub fn cms(&mut self) -> _CmsW {
375 _CmsW { register: self }
376 }
377 # [ doc = "Bit 4 - Direction" ]
378 pub fn dir(&mut self) -> _DirW {
379 _DirW { register: self }
380 }
381 # [ doc = "Bit 3 - One-pulse mode" ]
382 pub fn opm(&mut self) -> _OpmW {
383 _OpmW { register: self }
384 }
385 # [ doc = "Bit 2 - Update request source" ]
386 pub fn urs(&mut self) -> _UrsW {
387 _UrsW { register: self }
388 }
389 # [ doc = "Bit 1 - Update disable" ]
390 pub fn udis(&mut self) -> _UdisW {
391 _UdisW { register: self }
392 }
393 # [ doc = "Bit 0 - Counter enable" ]
394 pub fn cen(&mut self) -> _CenW {
395 _CenW { register: self }
396 }
397 }
398}
399
400# [ doc = "control register 2" ]
401# [ repr ( C ) ]
402pub struct Cr2 {
403 register: ::volatile_register::RW<u32>,
404}
405
406# [ doc = "control register 2" ]
407pub mod cr2 {
408 # [ doc = r" Value read from the register" ]
409 pub struct R {
410 bits: u32,
411 }
412 # [ doc = r" Value to write to the register" ]
413 pub struct W {
414 bits: u32,
415 }
416 impl super::Cr2 {
417 # [ doc = r" Modifies the contents of the register" ]
418 pub fn modify<F>(&mut self, f: F)
419 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
420 {
421 let bits = self.register.read();
422 let r = R { bits: bits };
423 let mut w = W { bits: bits };
424 f(&r, &mut w);
425 self.register.write(w.bits);
426 }
427 # [ doc = r" Reads the contents of the register" ]
428 pub fn read(&self) -> R {
429 R { bits: self.register.read() }
430 }
431 # [ doc = r" Writes to the register" ]
432 pub fn write<F>(&mut self, f: F)
433 where F: FnOnce(&mut W) -> &mut W
434 {
435 let mut w = W::reset_value();
436 f(&mut w);
437 self.register.write(w.bits);
438 }
439 }
440 # [ doc = "Value of the field TI1S" ]
441 pub struct Ti1sR {
442 bits: u8,
443 }
444 impl Ti1sR {
445 # [ doc = r" Value of the field as raw bits" ]
446 pub fn bits(&self) -> u8 {
447 self.bits
448 }
449 }
450 # [ doc = "Value of the field MMS" ]
451 pub struct MmsR {
452 bits: u8,
453 }
454 impl MmsR {
455 # [ doc = r" Value of the field as raw bits" ]
456 pub fn bits(&self) -> u8 {
457 self.bits
458 }
459 }
460 # [ doc = "Value of the field CCDS" ]
461 pub struct CcdsR {
462 bits: u8,
463 }
464 impl CcdsR {
465 # [ doc = r" Value of the field as raw bits" ]
466 pub fn bits(&self) -> u8 {
467 self.bits
468 }
469 }
470 # [ doc = r" Proxy" ]
471 pub struct _Ti1sW<'a> {
472 register: &'a mut W,
473 }
474 impl<'a> _Ti1sW<'a> {
475 # [ doc = r" Writes raw `bits` to the field" ]
476 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
477 const MASK: u8 = 1;
478 const OFFSET: u8 = 7;
479 self.register.bits &= !((MASK as u32) << OFFSET);
480 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
481 self.register
482 }
483 }
484 # [ doc = r" Proxy" ]
485 pub struct _MmsW<'a> {
486 register: &'a mut W,
487 }
488 impl<'a> _MmsW<'a> {
489 # [ doc = r" Writes raw `bits` to the field" ]
490 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
491 const MASK: u8 = 7;
492 const OFFSET: u8 = 4;
493 self.register.bits &= !((MASK as u32) << OFFSET);
494 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
495 self.register
496 }
497 }
498 # [ doc = r" Proxy" ]
499 pub struct _CcdsW<'a> {
500 register: &'a mut W,
501 }
502 impl<'a> _CcdsW<'a> {
503 # [ doc = r" Writes raw `bits` to the field" ]
504 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
505 const MASK: u8 = 1;
506 const OFFSET: u8 = 3;
507 self.register.bits &= !((MASK as u32) << OFFSET);
508 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
509 self.register
510 }
511 }
512 impl R {
513 # [ doc = r" Value of the register as raw bits" ]
514 pub fn bits(&self) -> u32 {
515 self.bits
516 }
517 fn _ti1s(&self) -> u8 {
518 const MASK: u8 = 1;
519 const OFFSET: u8 = 7;
520 ((self.bits >> OFFSET) & MASK as u32) as u8
521 }
522 # [ doc = "Bit 7 - TI1 selection" ]
523 pub fn ti1s(&self) -> Ti1sR {
524 Ti1sR { bits: self._ti1s() }
525 }
526 fn _mms(&self) -> u8 {
527 const MASK: u8 = 7;
528 const OFFSET: u8 = 4;
529 ((self.bits >> OFFSET) & MASK as u32) as u8
530 }
531 # [ doc = "Bits 4:6 - Master mode selection" ]
532 pub fn mms(&self) -> MmsR {
533 MmsR { bits: self._mms() }
534 }
535 fn _ccds(&self) -> u8 {
536 const MASK: u8 = 1;
537 const OFFSET: u8 = 3;
538 ((self.bits >> OFFSET) & MASK as u32) as u8
539 }
540 # [ doc = "Bit 3 - Capture/compare DMA selection" ]
541 pub fn ccds(&self) -> CcdsR {
542 CcdsR { bits: self._ccds() }
543 }
544 }
545 impl W {
546 # [ doc = r" Reset value of the register" ]
547 pub fn reset_value() -> W {
548 W { bits: 0 }
549 }
550 # [ doc = r" Writes raw `bits` to the register" ]
551 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
552 self.bits = bits;
553 self
554 }
555 # [ doc = "Bit 7 - TI1 selection" ]
556 pub fn ti1s(&mut self) -> _Ti1sW {
557 _Ti1sW { register: self }
558 }
559 # [ doc = "Bits 4:6 - Master mode selection" ]
560 pub fn mms(&mut self) -> _MmsW {
561 _MmsW { register: self }
562 }
563 # [ doc = "Bit 3 - Capture/compare DMA selection" ]
564 pub fn ccds(&mut self) -> _CcdsW {
565 _CcdsW { register: self }
566 }
567 }
568}
569
570# [ doc = "slave mode control register" ]
571# [ repr ( C ) ]
572pub struct Smcr {
573 register: ::volatile_register::RW<u32>,
574}
575
576# [ doc = "slave mode control register" ]
577pub mod smcr {
578 # [ doc = r" Value read from the register" ]
579 pub struct R {
580 bits: u32,
581 }
582 # [ doc = r" Value to write to the register" ]
583 pub struct W {
584 bits: u32,
585 }
586 impl super::Smcr {
587 # [ doc = r" Modifies the contents of the register" ]
588 pub fn modify<F>(&mut self, f: F)
589 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
590 {
591 let bits = self.register.read();
592 let r = R { bits: bits };
593 let mut w = W { bits: bits };
594 f(&r, &mut w);
595 self.register.write(w.bits);
596 }
597 # [ doc = r" Reads the contents of the register" ]
598 pub fn read(&self) -> R {
599 R { bits: self.register.read() }
600 }
601 # [ doc = r" Writes to the register" ]
602 pub fn write<F>(&mut self, f: F)
603 where F: FnOnce(&mut W) -> &mut W
604 {
605 let mut w = W::reset_value();
606 f(&mut w);
607 self.register.write(w.bits);
608 }
609 }
610 # [ doc = "Value of the field ETP" ]
611 pub struct EtpR {
612 bits: u8,
613 }
614 impl EtpR {
615 # [ doc = r" Value of the field as raw bits" ]
616 pub fn bits(&self) -> u8 {
617 self.bits
618 }
619 }
620 # [ doc = "Value of the field ECE" ]
621 pub struct EceR {
622 bits: u8,
623 }
624 impl EceR {
625 # [ doc = r" Value of the field as raw bits" ]
626 pub fn bits(&self) -> u8 {
627 self.bits
628 }
629 }
630 # [ doc = "Value of the field ETPS" ]
631 pub struct EtpsR {
632 bits: u8,
633 }
634 impl EtpsR {
635 # [ doc = r" Value of the field as raw bits" ]
636 pub fn bits(&self) -> u8 {
637 self.bits
638 }
639 }
640 # [ doc = "Value of the field ETF" ]
641 pub struct EtfR {
642 bits: u8,
643 }
644 impl EtfR {
645 # [ doc = r" Value of the field as raw bits" ]
646 pub fn bits(&self) -> u8 {
647 self.bits
648 }
649 }
650 # [ doc = "Value of the field MSM" ]
651 pub struct MsmR {
652 bits: u8,
653 }
654 impl MsmR {
655 # [ doc = r" Value of the field as raw bits" ]
656 pub fn bits(&self) -> u8 {
657 self.bits
658 }
659 }
660 # [ doc = "Value of the field TS" ]
661 pub struct TsR {
662 bits: u8,
663 }
664 impl TsR {
665 # [ doc = r" Value of the field as raw bits" ]
666 pub fn bits(&self) -> u8 {
667 self.bits
668 }
669 }
670 # [ doc = "Value of the field SMS" ]
671 pub struct SmsR {
672 bits: u8,
673 }
674 impl SmsR {
675 # [ doc = r" Value of the field as raw bits" ]
676 pub fn bits(&self) -> u8 {
677 self.bits
678 }
679 }
680 # [ doc = r" Proxy" ]
681 pub struct _EtpW<'a> {
682 register: &'a mut W,
683 }
684 impl<'a> _EtpW<'a> {
685 # [ doc = r" Writes raw `bits` to the field" ]
686 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
687 const MASK: u8 = 1;
688 const OFFSET: u8 = 15;
689 self.register.bits &= !((MASK as u32) << OFFSET);
690 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
691 self.register
692 }
693 }
694 # [ doc = r" Proxy" ]
695 pub struct _EceW<'a> {
696 register: &'a mut W,
697 }
698 impl<'a> _EceW<'a> {
699 # [ doc = r" Writes raw `bits` to the field" ]
700 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
701 const MASK: u8 = 1;
702 const OFFSET: u8 = 14;
703 self.register.bits &= !((MASK as u32) << OFFSET);
704 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
705 self.register
706 }
707 }
708 # [ doc = r" Proxy" ]
709 pub struct _EtpsW<'a> {
710 register: &'a mut W,
711 }
712 impl<'a> _EtpsW<'a> {
713 # [ doc = r" Writes raw `bits` to the field" ]
714 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
715 const MASK: u8 = 3;
716 const OFFSET: u8 = 12;
717 self.register.bits &= !((MASK as u32) << OFFSET);
718 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
719 self.register
720 }
721 }
722 # [ doc = r" Proxy" ]
723 pub struct _EtfW<'a> {
724 register: &'a mut W,
725 }
726 impl<'a> _EtfW<'a> {
727 # [ doc = r" Writes raw `bits` to the field" ]
728 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
729 const MASK: u8 = 15;
730 const OFFSET: u8 = 8;
731 self.register.bits &= !((MASK as u32) << OFFSET);
732 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
733 self.register
734 }
735 }
736 # [ doc = r" Proxy" ]
737 pub struct _MsmW<'a> {
738 register: &'a mut W,
739 }
740 impl<'a> _MsmW<'a> {
741 # [ doc = r" Writes raw `bits` to the field" ]
742 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
743 const MASK: u8 = 1;
744 const OFFSET: u8 = 7;
745 self.register.bits &= !((MASK as u32) << OFFSET);
746 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
747 self.register
748 }
749 }
750 # [ doc = r" Proxy" ]
751 pub struct _TsW<'a> {
752 register: &'a mut W,
753 }
754 impl<'a> _TsW<'a> {
755 # [ doc = r" Writes raw `bits` to the field" ]
756 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
757 const MASK: u8 = 7;
758 const OFFSET: u8 = 4;
759 self.register.bits &= !((MASK as u32) << OFFSET);
760 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
761 self.register
762 }
763 }
764 # [ doc = r" Proxy" ]
765 pub struct _SmsW<'a> {
766 register: &'a mut W,
767 }
768 impl<'a> _SmsW<'a> {
769 # [ doc = r" Writes raw `bits` to the field" ]
770 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
771 const MASK: u8 = 7;
772 const OFFSET: u8 = 0;
773 self.register.bits &= !((MASK as u32) << OFFSET);
774 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
775 self.register
776 }
777 }
778 impl R {
779 # [ doc = r" Value of the register as raw bits" ]
780 pub fn bits(&self) -> u32 {
781 self.bits
782 }
783 fn _etp(&self) -> u8 {
784 const MASK: u8 = 1;
785 const OFFSET: u8 = 15;
786 ((self.bits >> OFFSET) & MASK as u32) as u8
787 }
788 # [ doc = "Bit 15 - External trigger polarity" ]
789 pub fn etp(&self) -> EtpR {
790 EtpR { bits: self._etp() }
791 }
792 fn _ece(&self) -> u8 {
793 const MASK: u8 = 1;
794 const OFFSET: u8 = 14;
795 ((self.bits >> OFFSET) & MASK as u32) as u8
796 }
797 # [ doc = "Bit 14 - External clock enable" ]
798 pub fn ece(&self) -> EceR {
799 EceR { bits: self._ece() }
800 }
801 fn _etps(&self) -> u8 {
802 const MASK: u8 = 3;
803 const OFFSET: u8 = 12;
804 ((self.bits >> OFFSET) & MASK as u32) as u8
805 }
806 # [ doc = "Bits 12:13 - External trigger prescaler" ]
807 pub fn etps(&self) -> EtpsR {
808 EtpsR { bits: self._etps() }
809 }
810 fn _etf(&self) -> u8 {
811 const MASK: u8 = 15;
812 const OFFSET: u8 = 8;
813 ((self.bits >> OFFSET) & MASK as u32) as u8
814 }
815 # [ doc = "Bits 8:11 - External trigger filter" ]
816 pub fn etf(&self) -> EtfR {
817 EtfR { bits: self._etf() }
818 }
819 fn _msm(&self) -> u8 {
820 const MASK: u8 = 1;
821 const OFFSET: u8 = 7;
822 ((self.bits >> OFFSET) & MASK as u32) as u8
823 }
824 # [ doc = "Bit 7 - Master/Slave mode" ]
825 pub fn msm(&self) -> MsmR {
826 MsmR { bits: self._msm() }
827 }
828 fn _ts(&self) -> u8 {
829 const MASK: u8 = 7;
830 const OFFSET: u8 = 4;
831 ((self.bits >> OFFSET) & MASK as u32) as u8
832 }
833 # [ doc = "Bits 4:6 - Trigger selection" ]
834 pub fn ts(&self) -> TsR {
835 TsR { bits: self._ts() }
836 }
837 fn _sms(&self) -> u8 {
838 const MASK: u8 = 7;
839 const OFFSET: u8 = 0;
840 ((self.bits >> OFFSET) & MASK as u32) as u8
841 }
842 # [ doc = "Bits 0:2 - Slave mode selection" ]
843 pub fn sms(&self) -> SmsR {
844 SmsR { bits: self._sms() }
845 }
846 }
847 impl W {
848 # [ doc = r" Reset value of the register" ]
849 pub fn reset_value() -> W {
850 W { bits: 0 }
851 }
852 # [ doc = r" Writes raw `bits` to the register" ]
853 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
854 self.bits = bits;
855 self
856 }
857 # [ doc = "Bit 15 - External trigger polarity" ]
858 pub fn etp(&mut self) -> _EtpW {
859 _EtpW { register: self }
860 }
861 # [ doc = "Bit 14 - External clock enable" ]
862 pub fn ece(&mut self) -> _EceW {
863 _EceW { register: self }
864 }
865 # [ doc = "Bits 12:13 - External trigger prescaler" ]
866 pub fn etps(&mut self) -> _EtpsW {
867 _EtpsW { register: self }
868 }
869 # [ doc = "Bits 8:11 - External trigger filter" ]
870 pub fn etf(&mut self) -> _EtfW {
871 _EtfW { register: self }
872 }
873 # [ doc = "Bit 7 - Master/Slave mode" ]
874 pub fn msm(&mut self) -> _MsmW {
875 _MsmW { register: self }
876 }
877 # [ doc = "Bits 4:6 - Trigger selection" ]
878 pub fn ts(&mut self) -> _TsW {
879 _TsW { register: self }
880 }
881 # [ doc = "Bits 0:2 - Slave mode selection" ]
882 pub fn sms(&mut self) -> _SmsW {
883 _SmsW { register: self }
884 }
885 }
886}
887
888# [ doc = "DMA/Interrupt enable register" ]
889# [ repr ( C ) ]
890pub struct Dier {
891 register: ::volatile_register::RW<u32>,
892}
893
894# [ doc = "DMA/Interrupt enable register" ]
895pub mod dier {
896 # [ doc = r" Value read from the register" ]
897 pub struct R {
898 bits: u32,
899 }
900 # [ doc = r" Value to write to the register" ]
901 pub struct W {
902 bits: u32,
903 }
904 impl super::Dier {
905 # [ doc = r" Modifies the contents of the register" ]
906 pub fn modify<F>(&mut self, f: F)
907 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
908 {
909 let bits = self.register.read();
910 let r = R { bits: bits };
911 let mut w = W { bits: bits };
912 f(&r, &mut w);
913 self.register.write(w.bits);
914 }
915 # [ doc = r" Reads the contents of the register" ]
916 pub fn read(&self) -> R {
917 R { bits: self.register.read() }
918 }
919 # [ doc = r" Writes to the register" ]
920 pub fn write<F>(&mut self, f: F)
921 where F: FnOnce(&mut W) -> &mut W
922 {
923 let mut w = W::reset_value();
924 f(&mut w);
925 self.register.write(w.bits);
926 }
927 }
928 # [ doc = "Value of the field TDE" ]
929 pub struct TdeR {
930 bits: u8,
931 }
932 impl TdeR {
933 # [ doc = r" Value of the field as raw bits" ]
934 pub fn bits(&self) -> u8 {
935 self.bits
936 }
937 }
938 # [ doc = "Value of the field COMDE" ]
939 pub struct ComdeR {
940 bits: u8,
941 }
942 impl ComdeR {
943 # [ doc = r" Value of the field as raw bits" ]
944 pub fn bits(&self) -> u8 {
945 self.bits
946 }
947 }
948 # [ doc = "Value of the field CC4DE" ]
949 pub struct Cc4deR {
950 bits: u8,
951 }
952 impl Cc4deR {
953 # [ doc = r" Value of the field as raw bits" ]
954 pub fn bits(&self) -> u8 {
955 self.bits
956 }
957 }
958 # [ doc = "Value of the field CC3DE" ]
959 pub struct Cc3deR {
960 bits: u8,
961 }
962 impl Cc3deR {
963 # [ doc = r" Value of the field as raw bits" ]
964 pub fn bits(&self) -> u8 {
965 self.bits
966 }
967 }
968 # [ doc = "Value of the field CC2DE" ]
969 pub struct Cc2deR {
970 bits: u8,
971 }
972 impl Cc2deR {
973 # [ doc = r" Value of the field as raw bits" ]
974 pub fn bits(&self) -> u8 {
975 self.bits
976 }
977 }
978 # [ doc = "Value of the field CC1DE" ]
979 pub struct Cc1deR {
980 bits: u8,
981 }
982 impl Cc1deR {
983 # [ doc = r" Value of the field as raw bits" ]
984 pub fn bits(&self) -> u8 {
985 self.bits
986 }
987 }
988 # [ doc = "Value of the field UDE" ]
989 pub struct UdeR {
990 bits: u8,
991 }
992 impl UdeR {
993 # [ doc = r" Value of the field as raw bits" ]
994 pub fn bits(&self) -> u8 {
995 self.bits
996 }
997 }
998 # [ doc = "Value of the field TIE" ]
999 pub struct TieR {
1000 bits: u8,
1001 }
1002 impl TieR {
1003 # [ doc = r" Value of the field as raw bits" ]
1004 pub fn bits(&self) -> u8 {
1005 self.bits
1006 }
1007 }
1008 # [ doc = "Value of the field CC4IE" ]
1009 pub struct Cc4ieR {
1010 bits: u8,
1011 }
1012 impl Cc4ieR {
1013 # [ doc = r" Value of the field as raw bits" ]
1014 pub fn bits(&self) -> u8 {
1015 self.bits
1016 }
1017 }
1018 # [ doc = "Value of the field CC3IE" ]
1019 pub struct Cc3ieR {
1020 bits: u8,
1021 }
1022 impl Cc3ieR {
1023 # [ doc = r" Value of the field as raw bits" ]
1024 pub fn bits(&self) -> u8 {
1025 self.bits
1026 }
1027 }
1028 # [ doc = "Value of the field CC2IE" ]
1029 pub struct Cc2ieR {
1030 bits: u8,
1031 }
1032 impl Cc2ieR {
1033 # [ doc = r" Value of the field as raw bits" ]
1034 pub fn bits(&self) -> u8 {
1035 self.bits
1036 }
1037 }
1038 # [ doc = "Value of the field CC1IE" ]
1039 pub struct Cc1ieR {
1040 bits: u8,
1041 }
1042 impl Cc1ieR {
1043 # [ doc = r" Value of the field as raw bits" ]
1044 pub fn bits(&self) -> u8 {
1045 self.bits
1046 }
1047 }
1048 # [ doc = "Value of the field UIE" ]
1049 pub struct UieR {
1050 bits: u8,
1051 }
1052 impl UieR {
1053 # [ doc = r" Value of the field as raw bits" ]
1054 pub fn bits(&self) -> u8 {
1055 self.bits
1056 }
1057 }
1058 # [ doc = r" Proxy" ]
1059 pub struct _TdeW<'a> {
1060 register: &'a mut W,
1061 }
1062 impl<'a> _TdeW<'a> {
1063 # [ doc = r" Writes raw `bits` to the field" ]
1064 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1065 const MASK: u8 = 1;
1066 const OFFSET: u8 = 14;
1067 self.register.bits &= !((MASK as u32) << OFFSET);
1068 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1069 self.register
1070 }
1071 }
1072 # [ doc = r" Proxy" ]
1073 pub struct _ComdeW<'a> {
1074 register: &'a mut W,
1075 }
1076 impl<'a> _ComdeW<'a> {
1077 # [ doc = r" Writes raw `bits` to the field" ]
1078 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1079 const MASK: u8 = 1;
1080 const OFFSET: u8 = 13;
1081 self.register.bits &= !((MASK as u32) << OFFSET);
1082 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1083 self.register
1084 }
1085 }
1086 # [ doc = r" Proxy" ]
1087 pub struct _Cc4deW<'a> {
1088 register: &'a mut W,
1089 }
1090 impl<'a> _Cc4deW<'a> {
1091 # [ doc = r" Writes raw `bits` to the field" ]
1092 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1093 const MASK: u8 = 1;
1094 const OFFSET: u8 = 12;
1095 self.register.bits &= !((MASK as u32) << OFFSET);
1096 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1097 self.register
1098 }
1099 }
1100 # [ doc = r" Proxy" ]
1101 pub struct _Cc3deW<'a> {
1102 register: &'a mut W,
1103 }
1104 impl<'a> _Cc3deW<'a> {
1105 # [ doc = r" Writes raw `bits` to the field" ]
1106 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1107 const MASK: u8 = 1;
1108 const OFFSET: u8 = 11;
1109 self.register.bits &= !((MASK as u32) << OFFSET);
1110 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1111 self.register
1112 }
1113 }
1114 # [ doc = r" Proxy" ]
1115 pub struct _Cc2deW<'a> {
1116 register: &'a mut W,
1117 }
1118 impl<'a> _Cc2deW<'a> {
1119 # [ doc = r" Writes raw `bits` to the field" ]
1120 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1121 const MASK: u8 = 1;
1122 const OFFSET: u8 = 10;
1123 self.register.bits &= !((MASK as u32) << OFFSET);
1124 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1125 self.register
1126 }
1127 }
1128 # [ doc = r" Proxy" ]
1129 pub struct _Cc1deW<'a> {
1130 register: &'a mut W,
1131 }
1132 impl<'a> _Cc1deW<'a> {
1133 # [ doc = r" Writes raw `bits` to the field" ]
1134 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1135 const MASK: u8 = 1;
1136 const OFFSET: u8 = 9;
1137 self.register.bits &= !((MASK as u32) << OFFSET);
1138 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1139 self.register
1140 }
1141 }
1142 # [ doc = r" Proxy" ]
1143 pub struct _UdeW<'a> {
1144 register: &'a mut W,
1145 }
1146 impl<'a> _UdeW<'a> {
1147 # [ doc = r" Writes raw `bits` to the field" ]
1148 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1149 const MASK: u8 = 1;
1150 const OFFSET: u8 = 8;
1151 self.register.bits &= !((MASK as u32) << OFFSET);
1152 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1153 self.register
1154 }
1155 }
1156 # [ doc = r" Proxy" ]
1157 pub struct _TieW<'a> {
1158 register: &'a mut W,
1159 }
1160 impl<'a> _TieW<'a> {
1161 # [ doc = r" Writes raw `bits` to the field" ]
1162 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1163 const MASK: u8 = 1;
1164 const OFFSET: u8 = 6;
1165 self.register.bits &= !((MASK as u32) << OFFSET);
1166 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1167 self.register
1168 }
1169 }
1170 # [ doc = r" Proxy" ]
1171 pub struct _Cc4ieW<'a> {
1172 register: &'a mut W,
1173 }
1174 impl<'a> _Cc4ieW<'a> {
1175 # [ doc = r" Writes raw `bits` to the field" ]
1176 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1177 const MASK: u8 = 1;
1178 const OFFSET: u8 = 4;
1179 self.register.bits &= !((MASK as u32) << OFFSET);
1180 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1181 self.register
1182 }
1183 }
1184 # [ doc = r" Proxy" ]
1185 pub struct _Cc3ieW<'a> {
1186 register: &'a mut W,
1187 }
1188 impl<'a> _Cc3ieW<'a> {
1189 # [ doc = r" Writes raw `bits` to the field" ]
1190 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1191 const MASK: u8 = 1;
1192 const OFFSET: u8 = 3;
1193 self.register.bits &= !((MASK as u32) << OFFSET);
1194 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1195 self.register
1196 }
1197 }
1198 # [ doc = r" Proxy" ]
1199 pub struct _Cc2ieW<'a> {
1200 register: &'a mut W,
1201 }
1202 impl<'a> _Cc2ieW<'a> {
1203 # [ doc = r" Writes raw `bits` to the field" ]
1204 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1205 const MASK: u8 = 1;
1206 const OFFSET: u8 = 2;
1207 self.register.bits &= !((MASK as u32) << OFFSET);
1208 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1209 self.register
1210 }
1211 }
1212 # [ doc = r" Proxy" ]
1213 pub struct _Cc1ieW<'a> {
1214 register: &'a mut W,
1215 }
1216 impl<'a> _Cc1ieW<'a> {
1217 # [ doc = r" Writes raw `bits` to the field" ]
1218 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1219 const MASK: u8 = 1;
1220 const OFFSET: u8 = 1;
1221 self.register.bits &= !((MASK as u32) << OFFSET);
1222 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1223 self.register
1224 }
1225 }
1226 # [ doc = r" Proxy" ]
1227 pub struct _UieW<'a> {
1228 register: &'a mut W,
1229 }
1230 impl<'a> _UieW<'a> {
1231 # [ doc = r" Writes raw `bits` to the field" ]
1232 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1233 const MASK: u8 = 1;
1234 const OFFSET: u8 = 0;
1235 self.register.bits &= !((MASK as u32) << OFFSET);
1236 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1237 self.register
1238 }
1239 }
1240 impl R {
1241 # [ doc = r" Value of the register as raw bits" ]
1242 pub fn bits(&self) -> u32 {
1243 self.bits
1244 }
1245 fn _tde(&self) -> u8 {
1246 const MASK: u8 = 1;
1247 const OFFSET: u8 = 14;
1248 ((self.bits >> OFFSET) & MASK as u32) as u8
1249 }
1250 # [ doc = "Bit 14 - Trigger DMA request enable" ]
1251 pub fn tde(&self) -> TdeR {
1252 TdeR { bits: self._tde() }
1253 }
1254 fn _comde(&self) -> u8 {
1255 const MASK: u8 = 1;
1256 const OFFSET: u8 = 13;
1257 ((self.bits >> OFFSET) & MASK as u32) as u8
1258 }
1259 # [ doc = "Bit 13 - Reserved" ]
1260 pub fn comde(&self) -> ComdeR {
1261 ComdeR { bits: self._comde() }
1262 }
1263 fn _cc4de(&self) -> u8 {
1264 const MASK: u8 = 1;
1265 const OFFSET: u8 = 12;
1266 ((self.bits >> OFFSET) & MASK as u32) as u8
1267 }
1268 # [ doc = "Bit 12 - Capture/Compare 4 DMA request enable" ]
1269 pub fn cc4de(&self) -> Cc4deR {
1270 Cc4deR { bits: self._cc4de() }
1271 }
1272 fn _cc3de(&self) -> u8 {
1273 const MASK: u8 = 1;
1274 const OFFSET: u8 = 11;
1275 ((self.bits >> OFFSET) & MASK as u32) as u8
1276 }
1277 # [ doc = "Bit 11 - Capture/Compare 3 DMA request enable" ]
1278 pub fn cc3de(&self) -> Cc3deR {
1279 Cc3deR { bits: self._cc3de() }
1280 }
1281 fn _cc2de(&self) -> u8 {
1282 const MASK: u8 = 1;
1283 const OFFSET: u8 = 10;
1284 ((self.bits >> OFFSET) & MASK as u32) as u8
1285 }
1286 # [ doc = "Bit 10 - Capture/Compare 2 DMA request enable" ]
1287 pub fn cc2de(&self) -> Cc2deR {
1288 Cc2deR { bits: self._cc2de() }
1289 }
1290 fn _cc1de(&self) -> u8 {
1291 const MASK: u8 = 1;
1292 const OFFSET: u8 = 9;
1293 ((self.bits >> OFFSET) & MASK as u32) as u8
1294 }
1295 # [ doc = "Bit 9 - Capture/Compare 1 DMA request enable" ]
1296 pub fn cc1de(&self) -> Cc1deR {
1297 Cc1deR { bits: self._cc1de() }
1298 }
1299 fn _ude(&self) -> u8 {
1300 const MASK: u8 = 1;
1301 const OFFSET: u8 = 8;
1302 ((self.bits >> OFFSET) & MASK as u32) as u8
1303 }
1304 # [ doc = "Bit 8 - Update DMA request enable" ]
1305 pub fn ude(&self) -> UdeR {
1306 UdeR { bits: self._ude() }
1307 }
1308 fn _tie(&self) -> u8 {
1309 const MASK: u8 = 1;
1310 const OFFSET: u8 = 6;
1311 ((self.bits >> OFFSET) & MASK as u32) as u8
1312 }
1313 # [ doc = "Bit 6 - Trigger interrupt enable" ]
1314 pub fn tie(&self) -> TieR {
1315 TieR { bits: self._tie() }
1316 }
1317 fn _cc4ie(&self) -> u8 {
1318 const MASK: u8 = 1;
1319 const OFFSET: u8 = 4;
1320 ((self.bits >> OFFSET) & MASK as u32) as u8
1321 }
1322 # [ doc = "Bit 4 - Capture/Compare 4 interrupt enable" ]
1323 pub fn cc4ie(&self) -> Cc4ieR {
1324 Cc4ieR { bits: self._cc4ie() }
1325 }
1326 fn _cc3ie(&self) -> u8 {
1327 const MASK: u8 = 1;
1328 const OFFSET: u8 = 3;
1329 ((self.bits >> OFFSET) & MASK as u32) as u8
1330 }
1331 # [ doc = "Bit 3 - Capture/Compare 3 interrupt enable" ]
1332 pub fn cc3ie(&self) -> Cc3ieR {
1333 Cc3ieR { bits: self._cc3ie() }
1334 }
1335 fn _cc2ie(&self) -> u8 {
1336 const MASK: u8 = 1;
1337 const OFFSET: u8 = 2;
1338 ((self.bits >> OFFSET) & MASK as u32) as u8
1339 }
1340 # [ doc = "Bit 2 - Capture/Compare 2 interrupt enable" ]
1341 pub fn cc2ie(&self) -> Cc2ieR {
1342 Cc2ieR { bits: self._cc2ie() }
1343 }
1344 fn _cc1ie(&self) -> u8 {
1345 const MASK: u8 = 1;
1346 const OFFSET: u8 = 1;
1347 ((self.bits >> OFFSET) & MASK as u32) as u8
1348 }
1349 # [ doc = "Bit 1 - Capture/Compare 1 interrupt enable" ]
1350 pub fn cc1ie(&self) -> Cc1ieR {
1351 Cc1ieR { bits: self._cc1ie() }
1352 }
1353 fn _uie(&self) -> u8 {
1354 const MASK: u8 = 1;
1355 const OFFSET: u8 = 0;
1356 ((self.bits >> OFFSET) & MASK as u32) as u8
1357 }
1358 # [ doc = "Bit 0 - Update interrupt enable" ]
1359 pub fn uie(&self) -> UieR {
1360 UieR { bits: self._uie() }
1361 }
1362 }
1363 impl W {
1364 # [ doc = r" Reset value of the register" ]
1365 pub fn reset_value() -> W {
1366 W { bits: 0 }
1367 }
1368 # [ doc = r" Writes raw `bits` to the register" ]
1369 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1370 self.bits = bits;
1371 self
1372 }
1373 # [ doc = "Bit 14 - Trigger DMA request enable" ]
1374 pub fn tde(&mut self) -> _TdeW {
1375 _TdeW { register: self }
1376 }
1377 # [ doc = "Bit 13 - Reserved" ]
1378 pub fn comde(&mut self) -> _ComdeW {
1379 _ComdeW { register: self }
1380 }
1381 # [ doc = "Bit 12 - Capture/Compare 4 DMA request enable" ]
1382 pub fn cc4de(&mut self) -> _Cc4deW {
1383 _Cc4deW { register: self }
1384 }
1385 # [ doc = "Bit 11 - Capture/Compare 3 DMA request enable" ]
1386 pub fn cc3de(&mut self) -> _Cc3deW {
1387 _Cc3deW { register: self }
1388 }
1389 # [ doc = "Bit 10 - Capture/Compare 2 DMA request enable" ]
1390 pub fn cc2de(&mut self) -> _Cc2deW {
1391 _Cc2deW { register: self }
1392 }
1393 # [ doc = "Bit 9 - Capture/Compare 1 DMA request enable" ]
1394 pub fn cc1de(&mut self) -> _Cc1deW {
1395 _Cc1deW { register: self }
1396 }
1397 # [ doc = "Bit 8 - Update DMA request enable" ]
1398 pub fn ude(&mut self) -> _UdeW {
1399 _UdeW { register: self }
1400 }
1401 # [ doc = "Bit 6 - Trigger interrupt enable" ]
1402 pub fn tie(&mut self) -> _TieW {
1403 _TieW { register: self }
1404 }
1405 # [ doc = "Bit 4 - Capture/Compare 4 interrupt enable" ]
1406 pub fn cc4ie(&mut self) -> _Cc4ieW {
1407 _Cc4ieW { register: self }
1408 }
1409 # [ doc = "Bit 3 - Capture/Compare 3 interrupt enable" ]
1410 pub fn cc3ie(&mut self) -> _Cc3ieW {
1411 _Cc3ieW { register: self }
1412 }
1413 # [ doc = "Bit 2 - Capture/Compare 2 interrupt enable" ]
1414 pub fn cc2ie(&mut self) -> _Cc2ieW {
1415 _Cc2ieW { register: self }
1416 }
1417 # [ doc = "Bit 1 - Capture/Compare 1 interrupt enable" ]
1418 pub fn cc1ie(&mut self) -> _Cc1ieW {
1419 _Cc1ieW { register: self }
1420 }
1421 # [ doc = "Bit 0 - Update interrupt enable" ]
1422 pub fn uie(&mut self) -> _UieW {
1423 _UieW { register: self }
1424 }
1425 }
1426}
1427
1428# [ doc = "status register" ]
1429# [ repr ( C ) ]
1430pub struct Sr {
1431 register: ::volatile_register::RW<u32>,
1432}
1433
1434# [ doc = "status register" ]
1435pub mod sr {
1436 # [ doc = r" Value read from the register" ]
1437 pub struct R {
1438 bits: u32,
1439 }
1440 # [ doc = r" Value to write to the register" ]
1441 pub struct W {
1442 bits: u32,
1443 }
1444 impl super::Sr {
1445 # [ doc = r" Modifies the contents of the register" ]
1446 pub fn modify<F>(&mut self, f: F)
1447 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
1448 {
1449 let bits = self.register.read();
1450 let r = R { bits: bits };
1451 let mut w = W { bits: bits };
1452 f(&r, &mut w);
1453 self.register.write(w.bits);
1454 }
1455 # [ doc = r" Reads the contents of the register" ]
1456 pub fn read(&self) -> R {
1457 R { bits: self.register.read() }
1458 }
1459 # [ doc = r" Writes to the register" ]
1460 pub fn write<F>(&mut self, f: F)
1461 where F: FnOnce(&mut W) -> &mut W
1462 {
1463 let mut w = W::reset_value();
1464 f(&mut w);
1465 self.register.write(w.bits);
1466 }
1467 }
1468 # [ doc = "Value of the field CC4OF" ]
1469 pub struct Cc4ofR {
1470 bits: u8,
1471 }
1472 impl Cc4ofR {
1473 # [ doc = r" Value of the field as raw bits" ]
1474 pub fn bits(&self) -> u8 {
1475 self.bits
1476 }
1477 }
1478 # [ doc = "Value of the field CC3OF" ]
1479 pub struct Cc3ofR {
1480 bits: u8,
1481 }
1482 impl Cc3ofR {
1483 # [ doc = r" Value of the field as raw bits" ]
1484 pub fn bits(&self) -> u8 {
1485 self.bits
1486 }
1487 }
1488 # [ doc = "Value of the field CC2OF" ]
1489 pub struct Cc2ofR {
1490 bits: u8,
1491 }
1492 impl Cc2ofR {
1493 # [ doc = r" Value of the field as raw bits" ]
1494 pub fn bits(&self) -> u8 {
1495 self.bits
1496 }
1497 }
1498 # [ doc = "Value of the field CC1OF" ]
1499 pub struct Cc1ofR {
1500 bits: u8,
1501 }
1502 impl Cc1ofR {
1503 # [ doc = r" Value of the field as raw bits" ]
1504 pub fn bits(&self) -> u8 {
1505 self.bits
1506 }
1507 }
1508 # [ doc = "Value of the field TIF" ]
1509 pub struct TifR {
1510 bits: u8,
1511 }
1512 impl TifR {
1513 # [ doc = r" Value of the field as raw bits" ]
1514 pub fn bits(&self) -> u8 {
1515 self.bits
1516 }
1517 }
1518 # [ doc = "Value of the field CC4IF" ]
1519 pub struct Cc4ifR {
1520 bits: u8,
1521 }
1522 impl Cc4ifR {
1523 # [ doc = r" Value of the field as raw bits" ]
1524 pub fn bits(&self) -> u8 {
1525 self.bits
1526 }
1527 }
1528 # [ doc = "Value of the field CC3IF" ]
1529 pub struct Cc3ifR {
1530 bits: u8,
1531 }
1532 impl Cc3ifR {
1533 # [ doc = r" Value of the field as raw bits" ]
1534 pub fn bits(&self) -> u8 {
1535 self.bits
1536 }
1537 }
1538 # [ doc = "Value of the field CC2IF" ]
1539 pub struct Cc2ifR {
1540 bits: u8,
1541 }
1542 impl Cc2ifR {
1543 # [ doc = r" Value of the field as raw bits" ]
1544 pub fn bits(&self) -> u8 {
1545 self.bits
1546 }
1547 }
1548 # [ doc = "Value of the field CC1IF" ]
1549 pub struct Cc1ifR {
1550 bits: u8,
1551 }
1552 impl Cc1ifR {
1553 # [ doc = r" Value of the field as raw bits" ]
1554 pub fn bits(&self) -> u8 {
1555 self.bits
1556 }
1557 }
1558 # [ doc = "Value of the field UIF" ]
1559 pub struct UifR {
1560 bits: u8,
1561 }
1562 impl UifR {
1563 # [ doc = r" Value of the field as raw bits" ]
1564 pub fn bits(&self) -> u8 {
1565 self.bits
1566 }
1567 }
1568 # [ doc = r" Proxy" ]
1569 pub struct _Cc4ofW<'a> {
1570 register: &'a mut W,
1571 }
1572 impl<'a> _Cc4ofW<'a> {
1573 # [ doc = r" Writes raw `bits` to the field" ]
1574 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1575 const MASK: u8 = 1;
1576 const OFFSET: u8 = 12;
1577 self.register.bits &= !((MASK as u32) << OFFSET);
1578 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1579 self.register
1580 }
1581 }
1582 # [ doc = r" Proxy" ]
1583 pub struct _Cc3ofW<'a> {
1584 register: &'a mut W,
1585 }
1586 impl<'a> _Cc3ofW<'a> {
1587 # [ doc = r" Writes raw `bits` to the field" ]
1588 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1589 const MASK: u8 = 1;
1590 const OFFSET: u8 = 11;
1591 self.register.bits &= !((MASK as u32) << OFFSET);
1592 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1593 self.register
1594 }
1595 }
1596 # [ doc = r" Proxy" ]
1597 pub struct _Cc2ofW<'a> {
1598 register: &'a mut W,
1599 }
1600 impl<'a> _Cc2ofW<'a> {
1601 # [ doc = r" Writes raw `bits` to the field" ]
1602 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1603 const MASK: u8 = 1;
1604 const OFFSET: u8 = 10;
1605 self.register.bits &= !((MASK as u32) << OFFSET);
1606 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1607 self.register
1608 }
1609 }
1610 # [ doc = r" Proxy" ]
1611 pub struct _Cc1ofW<'a> {
1612 register: &'a mut W,
1613 }
1614 impl<'a> _Cc1ofW<'a> {
1615 # [ doc = r" Writes raw `bits` to the field" ]
1616 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1617 const MASK: u8 = 1;
1618 const OFFSET: u8 = 9;
1619 self.register.bits &= !((MASK as u32) << OFFSET);
1620 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1621 self.register
1622 }
1623 }
1624 # [ doc = r" Proxy" ]
1625 pub struct _TifW<'a> {
1626 register: &'a mut W,
1627 }
1628 impl<'a> _TifW<'a> {
1629 # [ doc = r" Writes raw `bits` to the field" ]
1630 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1631 const MASK: u8 = 1;
1632 const OFFSET: u8 = 6;
1633 self.register.bits &= !((MASK as u32) << OFFSET);
1634 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1635 self.register
1636 }
1637 }
1638 # [ doc = r" Proxy" ]
1639 pub struct _Cc4ifW<'a> {
1640 register: &'a mut W,
1641 }
1642 impl<'a> _Cc4ifW<'a> {
1643 # [ doc = r" Writes raw `bits` to the field" ]
1644 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1645 const MASK: u8 = 1;
1646 const OFFSET: u8 = 4;
1647 self.register.bits &= !((MASK as u32) << OFFSET);
1648 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1649 self.register
1650 }
1651 }
1652 # [ doc = r" Proxy" ]
1653 pub struct _Cc3ifW<'a> {
1654 register: &'a mut W,
1655 }
1656 impl<'a> _Cc3ifW<'a> {
1657 # [ doc = r" Writes raw `bits` to the field" ]
1658 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1659 const MASK: u8 = 1;
1660 const OFFSET: u8 = 3;
1661 self.register.bits &= !((MASK as u32) << OFFSET);
1662 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1663 self.register
1664 }
1665 }
1666 # [ doc = r" Proxy" ]
1667 pub struct _Cc2ifW<'a> {
1668 register: &'a mut W,
1669 }
1670 impl<'a> _Cc2ifW<'a> {
1671 # [ doc = r" Writes raw `bits` to the field" ]
1672 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1673 const MASK: u8 = 1;
1674 const OFFSET: u8 = 2;
1675 self.register.bits &= !((MASK as u32) << OFFSET);
1676 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1677 self.register
1678 }
1679 }
1680 # [ doc = r" Proxy" ]
1681 pub struct _Cc1ifW<'a> {
1682 register: &'a mut W,
1683 }
1684 impl<'a> _Cc1ifW<'a> {
1685 # [ doc = r" Writes raw `bits` to the field" ]
1686 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1687 const MASK: u8 = 1;
1688 const OFFSET: u8 = 1;
1689 self.register.bits &= !((MASK as u32) << OFFSET);
1690 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1691 self.register
1692 }
1693 }
1694 # [ doc = r" Proxy" ]
1695 pub struct _UifW<'a> {
1696 register: &'a mut W,
1697 }
1698 impl<'a> _UifW<'a> {
1699 # [ doc = r" Writes raw `bits` to the field" ]
1700 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1701 const MASK: u8 = 1;
1702 const OFFSET: u8 = 0;
1703 self.register.bits &= !((MASK as u32) << OFFSET);
1704 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1705 self.register
1706 }
1707 }
1708 impl R {
1709 # [ doc = r" Value of the register as raw bits" ]
1710 pub fn bits(&self) -> u32 {
1711 self.bits
1712 }
1713 fn _cc4of(&self) -> u8 {
1714 const MASK: u8 = 1;
1715 const OFFSET: u8 = 12;
1716 ((self.bits >> OFFSET) & MASK as u32) as u8
1717 }
1718 # [ doc = "Bit 12 - Capture/Compare 4 overcapture flag" ]
1719 pub fn cc4of(&self) -> Cc4ofR {
1720 Cc4ofR { bits: self._cc4of() }
1721 }
1722 fn _cc3of(&self) -> u8 {
1723 const MASK: u8 = 1;
1724 const OFFSET: u8 = 11;
1725 ((self.bits >> OFFSET) & MASK as u32) as u8
1726 }
1727 # [ doc = "Bit 11 - Capture/Compare 3 overcapture flag" ]
1728 pub fn cc3of(&self) -> Cc3ofR {
1729 Cc3ofR { bits: self._cc3of() }
1730 }
1731 fn _cc2of(&self) -> u8 {
1732 const MASK: u8 = 1;
1733 const OFFSET: u8 = 10;
1734 ((self.bits >> OFFSET) & MASK as u32) as u8
1735 }
1736 # [ doc = "Bit 10 - Capture/compare 2 overcapture flag" ]
1737 pub fn cc2of(&self) -> Cc2ofR {
1738 Cc2ofR { bits: self._cc2of() }
1739 }
1740 fn _cc1of(&self) -> u8 {
1741 const MASK: u8 = 1;
1742 const OFFSET: u8 = 9;
1743 ((self.bits >> OFFSET) & MASK as u32) as u8
1744 }
1745 # [ doc = "Bit 9 - Capture/Compare 1 overcapture flag" ]
1746 pub fn cc1of(&self) -> Cc1ofR {
1747 Cc1ofR { bits: self._cc1of() }
1748 }
1749 fn _tif(&self) -> u8 {
1750 const MASK: u8 = 1;
1751 const OFFSET: u8 = 6;
1752 ((self.bits >> OFFSET) & MASK as u32) as u8
1753 }
1754 # [ doc = "Bit 6 - Trigger interrupt flag" ]
1755 pub fn tif(&self) -> TifR {
1756 TifR { bits: self._tif() }
1757 }
1758 fn _cc4if(&self) -> u8 {
1759 const MASK: u8 = 1;
1760 const OFFSET: u8 = 4;
1761 ((self.bits >> OFFSET) & MASK as u32) as u8
1762 }
1763 # [ doc = "Bit 4 - Capture/Compare 4 interrupt flag" ]
1764 pub fn cc4if(&self) -> Cc4ifR {
1765 Cc4ifR { bits: self._cc4if() }
1766 }
1767 fn _cc3if(&self) -> u8 {
1768 const MASK: u8 = 1;
1769 const OFFSET: u8 = 3;
1770 ((self.bits >> OFFSET) & MASK as u32) as u8
1771 }
1772 # [ doc = "Bit 3 - Capture/Compare 3 interrupt flag" ]
1773 pub fn cc3if(&self) -> Cc3ifR {
1774 Cc3ifR { bits: self._cc3if() }
1775 }
1776 fn _cc2if(&self) -> u8 {
1777 const MASK: u8 = 1;
1778 const OFFSET: u8 = 2;
1779 ((self.bits >> OFFSET) & MASK as u32) as u8
1780 }
1781 # [ doc = "Bit 2 - Capture/Compare 2 interrupt flag" ]
1782 pub fn cc2if(&self) -> Cc2ifR {
1783 Cc2ifR { bits: self._cc2if() }
1784 }
1785 fn _cc1if(&self) -> u8 {
1786 const MASK: u8 = 1;
1787 const OFFSET: u8 = 1;
1788 ((self.bits >> OFFSET) & MASK as u32) as u8
1789 }
1790 # [ doc = "Bit 1 - Capture/compare 1 interrupt flag" ]
1791 pub fn cc1if(&self) -> Cc1ifR {
1792 Cc1ifR { bits: self._cc1if() }
1793 }
1794 fn _uif(&self) -> u8 {
1795 const MASK: u8 = 1;
1796 const OFFSET: u8 = 0;
1797 ((self.bits >> OFFSET) & MASK as u32) as u8
1798 }
1799 # [ doc = "Bit 0 - Update interrupt flag" ]
1800 pub fn uif(&self) -> UifR {
1801 UifR { bits: self._uif() }
1802 }
1803 }
1804 impl W {
1805 # [ doc = r" Reset value of the register" ]
1806 pub fn reset_value() -> W {
1807 W { bits: 0 }
1808 }
1809 # [ doc = r" Writes raw `bits` to the register" ]
1810 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1811 self.bits = bits;
1812 self
1813 }
1814 # [ doc = "Bit 12 - Capture/Compare 4 overcapture flag" ]
1815 pub fn cc4of(&mut self) -> _Cc4ofW {
1816 _Cc4ofW { register: self }
1817 }
1818 # [ doc = "Bit 11 - Capture/Compare 3 overcapture flag" ]
1819 pub fn cc3of(&mut self) -> _Cc3ofW {
1820 _Cc3ofW { register: self }
1821 }
1822 # [ doc = "Bit 10 - Capture/compare 2 overcapture flag" ]
1823 pub fn cc2of(&mut self) -> _Cc2ofW {
1824 _Cc2ofW { register: self }
1825 }
1826 # [ doc = "Bit 9 - Capture/Compare 1 overcapture flag" ]
1827 pub fn cc1of(&mut self) -> _Cc1ofW {
1828 _Cc1ofW { register: self }
1829 }
1830 # [ doc = "Bit 6 - Trigger interrupt flag" ]
1831 pub fn tif(&mut self) -> _TifW {
1832 _TifW { register: self }
1833 }
1834 # [ doc = "Bit 4 - Capture/Compare 4 interrupt flag" ]
1835 pub fn cc4if(&mut self) -> _Cc4ifW {
1836 _Cc4ifW { register: self }
1837 }
1838 # [ doc = "Bit 3 - Capture/Compare 3 interrupt flag" ]
1839 pub fn cc3if(&mut self) -> _Cc3ifW {
1840 _Cc3ifW { register: self }
1841 }
1842 # [ doc = "Bit 2 - Capture/Compare 2 interrupt flag" ]
1843 pub fn cc2if(&mut self) -> _Cc2ifW {
1844 _Cc2ifW { register: self }
1845 }
1846 # [ doc = "Bit 1 - Capture/compare 1 interrupt flag" ]
1847 pub fn cc1if(&mut self) -> _Cc1ifW {
1848 _Cc1ifW { register: self }
1849 }
1850 # [ doc = "Bit 0 - Update interrupt flag" ]
1851 pub fn uif(&mut self) -> _UifW {
1852 _UifW { register: self }
1853 }
1854 }
1855}
1856
1857# [ doc = "event generation register" ]
1858# [ repr ( C ) ]
1859pub struct Egr {
1860 register: ::volatile_register::WO<u32>,
1861}
1862
1863# [ doc = "event generation register" ]
1864pub mod egr {
1865 # [ doc = r" Value to write to the register" ]
1866 pub struct W {
1867 bits: u32,
1868 }
1869 impl super::Egr {
1870 # [ doc = r" Writes to the register" ]
1871 pub fn write<F>(&mut self, f: F)
1872 where F: FnOnce(&mut W) -> &mut W
1873 {
1874 let mut w = W::reset_value();
1875 f(&mut w);
1876 self.register.write(w.bits);
1877 }
1878 }
1879 # [ doc = r" Proxy" ]
1880 pub struct _TgW<'a> {
1881 register: &'a mut W,
1882 }
1883 impl<'a> _TgW<'a> {
1884 # [ doc = r" Writes raw `bits` to the field" ]
1885 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1886 const MASK: u8 = 1;
1887 const OFFSET: u8 = 6;
1888 self.register.bits &= !((MASK as u32) << OFFSET);
1889 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1890 self.register
1891 }
1892 }
1893 # [ doc = r" Proxy" ]
1894 pub struct _Cc4gW<'a> {
1895 register: &'a mut W,
1896 }
1897 impl<'a> _Cc4gW<'a> {
1898 # [ doc = r" Writes raw `bits` to the field" ]
1899 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1900 const MASK: u8 = 1;
1901 const OFFSET: u8 = 4;
1902 self.register.bits &= !((MASK as u32) << OFFSET);
1903 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1904 self.register
1905 }
1906 }
1907 # [ doc = r" Proxy" ]
1908 pub struct _Cc3gW<'a> {
1909 register: &'a mut W,
1910 }
1911 impl<'a> _Cc3gW<'a> {
1912 # [ doc = r" Writes raw `bits` to the field" ]
1913 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1914 const MASK: u8 = 1;
1915 const OFFSET: u8 = 3;
1916 self.register.bits &= !((MASK as u32) << OFFSET);
1917 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1918 self.register
1919 }
1920 }
1921 # [ doc = r" Proxy" ]
1922 pub struct _Cc2gW<'a> {
1923 register: &'a mut W,
1924 }
1925 impl<'a> _Cc2gW<'a> {
1926 # [ doc = r" Writes raw `bits` to the field" ]
1927 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1928 const MASK: u8 = 1;
1929 const OFFSET: u8 = 2;
1930 self.register.bits &= !((MASK as u32) << OFFSET);
1931 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1932 self.register
1933 }
1934 }
1935 # [ doc = r" Proxy" ]
1936 pub struct _Cc1gW<'a> {
1937 register: &'a mut W,
1938 }
1939 impl<'a> _Cc1gW<'a> {
1940 # [ doc = r" Writes raw `bits` to the field" ]
1941 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1942 const MASK: u8 = 1;
1943 const OFFSET: u8 = 1;
1944 self.register.bits &= !((MASK as u32) << OFFSET);
1945 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1946 self.register
1947 }
1948 }
1949 # [ doc = r" Proxy" ]
1950 pub struct _UgW<'a> {
1951 register: &'a mut W,
1952 }
1953 impl<'a> _UgW<'a> {
1954 # [ doc = r" Writes raw `bits` to the field" ]
1955 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
1956 const MASK: u8 = 1;
1957 const OFFSET: u8 = 0;
1958 self.register.bits &= !((MASK as u32) << OFFSET);
1959 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
1960 self.register
1961 }
1962 }
1963 impl W {
1964 # [ doc = r" Reset value of the register" ]
1965 pub fn reset_value() -> W {
1966 W { bits: 0 }
1967 }
1968 # [ doc = r" Writes raw `bits` to the register" ]
1969 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1970 self.bits = bits;
1971 self
1972 }
1973 # [ doc = "Bit 6 - Trigger generation" ]
1974 pub fn tg(&mut self) -> _TgW {
1975 _TgW { register: self }
1976 }
1977 # [ doc = "Bit 4 - Capture/compare 4 generation" ]
1978 pub fn cc4g(&mut self) -> _Cc4gW {
1979 _Cc4gW { register: self }
1980 }
1981 # [ doc = "Bit 3 - Capture/compare 3 generation" ]
1982 pub fn cc3g(&mut self) -> _Cc3gW {
1983 _Cc3gW { register: self }
1984 }
1985 # [ doc = "Bit 2 - Capture/compare 2 generation" ]
1986 pub fn cc2g(&mut self) -> _Cc2gW {
1987 _Cc2gW { register: self }
1988 }
1989 # [ doc = "Bit 1 - Capture/compare 1 generation" ]
1990 pub fn cc1g(&mut self) -> _Cc1gW {
1991 _Cc1gW { register: self }
1992 }
1993 # [ doc = "Bit 0 - Update generation" ]
1994 pub fn ug(&mut self) -> _UgW {
1995 _UgW { register: self }
1996 }
1997 }
1998}
1999
2000# [ doc = "capture/compare mode register 1 (output mode)" ]
2001# [ repr ( C ) ]
2002pub struct Ccmr1Output {
2003 register: ::volatile_register::RW<u32>,
2004}
2005
2006# [ doc = "capture/compare mode register 1 (output mode)" ]
2007pub mod ccmr1_output {
2008 # [ doc = r" Value read from the register" ]
2009 pub struct R {
2010 bits: u32,
2011 }
2012 # [ doc = r" Value to write to the register" ]
2013 pub struct W {
2014 bits: u32,
2015 }
2016 impl super::Ccmr1Output {
2017 # [ doc = r" Modifies the contents of the register" ]
2018 pub fn modify<F>(&mut self, f: F)
2019 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
2020 {
2021 let bits = self.register.read();
2022 let r = R { bits: bits };
2023 let mut w = W { bits: bits };
2024 f(&r, &mut w);
2025 self.register.write(w.bits);
2026 }
2027 # [ doc = r" Reads the contents of the register" ]
2028 pub fn read(&self) -> R {
2029 R { bits: self.register.read() }
2030 }
2031 # [ doc = r" Writes to the register" ]
2032 pub fn write<F>(&mut self, f: F)
2033 where F: FnOnce(&mut W) -> &mut W
2034 {
2035 let mut w = W::reset_value();
2036 f(&mut w);
2037 self.register.write(w.bits);
2038 }
2039 }
2040 # [ doc = "Value of the field OC2CE" ]
2041 pub struct Oc2ceR {
2042 bits: u8,
2043 }
2044 impl Oc2ceR {
2045 # [ doc = r" Value of the field as raw bits" ]
2046 pub fn bits(&self) -> u8 {
2047 self.bits
2048 }
2049 }
2050 # [ doc = "Value of the field OC2M" ]
2051 pub struct Oc2mR {
2052 bits: u8,
2053 }
2054 impl Oc2mR {
2055 # [ doc = r" Value of the field as raw bits" ]
2056 pub fn bits(&self) -> u8 {
2057 self.bits
2058 }
2059 }
2060 # [ doc = "Value of the field OC2PE" ]
2061 pub struct Oc2peR {
2062 bits: u8,
2063 }
2064 impl Oc2peR {
2065 # [ doc = r" Value of the field as raw bits" ]
2066 pub fn bits(&self) -> u8 {
2067 self.bits
2068 }
2069 }
2070 # [ doc = "Value of the field OC2FE" ]
2071 pub struct Oc2feR {
2072 bits: u8,
2073 }
2074 impl Oc2feR {
2075 # [ doc = r" Value of the field as raw bits" ]
2076 pub fn bits(&self) -> u8 {
2077 self.bits
2078 }
2079 }
2080 # [ doc = "Value of the field CC2S" ]
2081 pub struct Cc2sR {
2082 bits: u8,
2083 }
2084 impl Cc2sR {
2085 # [ doc = r" Value of the field as raw bits" ]
2086 pub fn bits(&self) -> u8 {
2087 self.bits
2088 }
2089 }
2090 # [ doc = "Value of the field OC1CE" ]
2091 pub struct Oc1ceR {
2092 bits: u8,
2093 }
2094 impl Oc1ceR {
2095 # [ doc = r" Value of the field as raw bits" ]
2096 pub fn bits(&self) -> u8 {
2097 self.bits
2098 }
2099 }
2100 # [ doc = "Value of the field OC1M" ]
2101 pub struct Oc1mR {
2102 bits: u8,
2103 }
2104 impl Oc1mR {
2105 # [ doc = r" Value of the field as raw bits" ]
2106 pub fn bits(&self) -> u8 {
2107 self.bits
2108 }
2109 }
2110 # [ doc = "Value of the field OC1PE" ]
2111 pub struct Oc1peR {
2112 bits: u8,
2113 }
2114 impl Oc1peR {
2115 # [ doc = r" Value of the field as raw bits" ]
2116 pub fn bits(&self) -> u8 {
2117 self.bits
2118 }
2119 }
2120 # [ doc = "Value of the field OC1FE" ]
2121 pub struct Oc1feR {
2122 bits: u8,
2123 }
2124 impl Oc1feR {
2125 # [ doc = r" Value of the field as raw bits" ]
2126 pub fn bits(&self) -> u8 {
2127 self.bits
2128 }
2129 }
2130 # [ doc = "Value of the field CC1S" ]
2131 pub struct Cc1sR {
2132 bits: u8,
2133 }
2134 impl Cc1sR {
2135 # [ doc = r" Value of the field as raw bits" ]
2136 pub fn bits(&self) -> u8 {
2137 self.bits
2138 }
2139 }
2140 # [ doc = r" Proxy" ]
2141 pub struct _Oc2ceW<'a> {
2142 register: &'a mut W,
2143 }
2144 impl<'a> _Oc2ceW<'a> {
2145 # [ doc = r" Writes raw `bits` to the field" ]
2146 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2147 const MASK: u8 = 1;
2148 const OFFSET: u8 = 15;
2149 self.register.bits &= !((MASK as u32) << OFFSET);
2150 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2151 self.register
2152 }
2153 }
2154 # [ doc = r" Proxy" ]
2155 pub struct _Oc2mW<'a> {
2156 register: &'a mut W,
2157 }
2158 impl<'a> _Oc2mW<'a> {
2159 # [ doc = r" Writes raw `bits` to the field" ]
2160 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2161 const MASK: u8 = 7;
2162 const OFFSET: u8 = 12;
2163 self.register.bits &= !((MASK as u32) << OFFSET);
2164 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2165 self.register
2166 }
2167 }
2168 # [ doc = r" Proxy" ]
2169 pub struct _Oc2peW<'a> {
2170 register: &'a mut W,
2171 }
2172 impl<'a> _Oc2peW<'a> {
2173 # [ doc = r" Writes raw `bits` to the field" ]
2174 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2175 const MASK: u8 = 1;
2176 const OFFSET: u8 = 11;
2177 self.register.bits &= !((MASK as u32) << OFFSET);
2178 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2179 self.register
2180 }
2181 }
2182 # [ doc = r" Proxy" ]
2183 pub struct _Oc2feW<'a> {
2184 register: &'a mut W,
2185 }
2186 impl<'a> _Oc2feW<'a> {
2187 # [ doc = r" Writes raw `bits` to the field" ]
2188 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2189 const MASK: u8 = 1;
2190 const OFFSET: u8 = 10;
2191 self.register.bits &= !((MASK as u32) << OFFSET);
2192 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2193 self.register
2194 }
2195 }
2196 # [ doc = r" Proxy" ]
2197 pub struct _Cc2sW<'a> {
2198 register: &'a mut W,
2199 }
2200 impl<'a> _Cc2sW<'a> {
2201 # [ doc = r" Writes raw `bits` to the field" ]
2202 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2203 const MASK: u8 = 3;
2204 const OFFSET: u8 = 8;
2205 self.register.bits &= !((MASK as u32) << OFFSET);
2206 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2207 self.register
2208 }
2209 }
2210 # [ doc = r" Proxy" ]
2211 pub struct _Oc1ceW<'a> {
2212 register: &'a mut W,
2213 }
2214 impl<'a> _Oc1ceW<'a> {
2215 # [ doc = r" Writes raw `bits` to the field" ]
2216 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2217 const MASK: u8 = 1;
2218 const OFFSET: u8 = 7;
2219 self.register.bits &= !((MASK as u32) << OFFSET);
2220 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2221 self.register
2222 }
2223 }
2224 # [ doc = r" Proxy" ]
2225 pub struct _Oc1mW<'a> {
2226 register: &'a mut W,
2227 }
2228 impl<'a> _Oc1mW<'a> {
2229 # [ doc = r" Writes raw `bits` to the field" ]
2230 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2231 const MASK: u8 = 7;
2232 const OFFSET: u8 = 4;
2233 self.register.bits &= !((MASK as u32) << OFFSET);
2234 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2235 self.register
2236 }
2237 }
2238 # [ doc = r" Proxy" ]
2239 pub struct _Oc1peW<'a> {
2240 register: &'a mut W,
2241 }
2242 impl<'a> _Oc1peW<'a> {
2243 # [ doc = r" Writes raw `bits` to the field" ]
2244 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2245 const MASK: u8 = 1;
2246 const OFFSET: u8 = 3;
2247 self.register.bits &= !((MASK as u32) << OFFSET);
2248 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2249 self.register
2250 }
2251 }
2252 # [ doc = r" Proxy" ]
2253 pub struct _Oc1feW<'a> {
2254 register: &'a mut W,
2255 }
2256 impl<'a> _Oc1feW<'a> {
2257 # [ doc = r" Writes raw `bits` to the field" ]
2258 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2259 const MASK: u8 = 1;
2260 const OFFSET: u8 = 2;
2261 self.register.bits &= !((MASK as u32) << OFFSET);
2262 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2263 self.register
2264 }
2265 }
2266 # [ doc = r" Proxy" ]
2267 pub struct _Cc1sW<'a> {
2268 register: &'a mut W,
2269 }
2270 impl<'a> _Cc1sW<'a> {
2271 # [ doc = r" Writes raw `bits` to the field" ]
2272 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2273 const MASK: u8 = 3;
2274 const OFFSET: u8 = 0;
2275 self.register.bits &= !((MASK as u32) << OFFSET);
2276 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2277 self.register
2278 }
2279 }
2280 impl R {
2281 # [ doc = r" Value of the register as raw bits" ]
2282 pub fn bits(&self) -> u32 {
2283 self.bits
2284 }
2285 fn _oc2ce(&self) -> u8 {
2286 const MASK: u8 = 1;
2287 const OFFSET: u8 = 15;
2288 ((self.bits >> OFFSET) & MASK as u32) as u8
2289 }
2290 # [ doc = "Bit 15 - Output compare 2 clear enable" ]
2291 pub fn oc2ce(&self) -> Oc2ceR {
2292 Oc2ceR { bits: self._oc2ce() }
2293 }
2294 fn _oc2m(&self) -> u8 {
2295 const MASK: u8 = 7;
2296 const OFFSET: u8 = 12;
2297 ((self.bits >> OFFSET) & MASK as u32) as u8
2298 }
2299 # [ doc = "Bits 12:14 - Output compare 2 mode" ]
2300 pub fn oc2m(&self) -> Oc2mR {
2301 Oc2mR { bits: self._oc2m() }
2302 }
2303 fn _oc2pe(&self) -> u8 {
2304 const MASK: u8 = 1;
2305 const OFFSET: u8 = 11;
2306 ((self.bits >> OFFSET) & MASK as u32) as u8
2307 }
2308 # [ doc = "Bit 11 - Output compare 2 preload enable" ]
2309 pub fn oc2pe(&self) -> Oc2peR {
2310 Oc2peR { bits: self._oc2pe() }
2311 }
2312 fn _oc2fe(&self) -> u8 {
2313 const MASK: u8 = 1;
2314 const OFFSET: u8 = 10;
2315 ((self.bits >> OFFSET) & MASK as u32) as u8
2316 }
2317 # [ doc = "Bit 10 - Output compare 2 fast enable" ]
2318 pub fn oc2fe(&self) -> Oc2feR {
2319 Oc2feR { bits: self._oc2fe() }
2320 }
2321 fn _cc2s(&self) -> u8 {
2322 const MASK: u8 = 3;
2323 const OFFSET: u8 = 8;
2324 ((self.bits >> OFFSET) & MASK as u32) as u8
2325 }
2326 # [ doc = "Bits 8:9 - Capture/Compare 2 selection" ]
2327 pub fn cc2s(&self) -> Cc2sR {
2328 Cc2sR { bits: self._cc2s() }
2329 }
2330 fn _oc1ce(&self) -> u8 {
2331 const MASK: u8 = 1;
2332 const OFFSET: u8 = 7;
2333 ((self.bits >> OFFSET) & MASK as u32) as u8
2334 }
2335 # [ doc = "Bit 7 - Output compare 1 clear enable" ]
2336 pub fn oc1ce(&self) -> Oc1ceR {
2337 Oc1ceR { bits: self._oc1ce() }
2338 }
2339 fn _oc1m(&self) -> u8 {
2340 const MASK: u8 = 7;
2341 const OFFSET: u8 = 4;
2342 ((self.bits >> OFFSET) & MASK as u32) as u8
2343 }
2344 # [ doc = "Bits 4:6 - Output compare 1 mode" ]
2345 pub fn oc1m(&self) -> Oc1mR {
2346 Oc1mR { bits: self._oc1m() }
2347 }
2348 fn _oc1pe(&self) -> u8 {
2349 const MASK: u8 = 1;
2350 const OFFSET: u8 = 3;
2351 ((self.bits >> OFFSET) & MASK as u32) as u8
2352 }
2353 # [ doc = "Bit 3 - Output compare 1 preload enable" ]
2354 pub fn oc1pe(&self) -> Oc1peR {
2355 Oc1peR { bits: self._oc1pe() }
2356 }
2357 fn _oc1fe(&self) -> u8 {
2358 const MASK: u8 = 1;
2359 const OFFSET: u8 = 2;
2360 ((self.bits >> OFFSET) & MASK as u32) as u8
2361 }
2362 # [ doc = "Bit 2 - Output compare 1 fast enable" ]
2363 pub fn oc1fe(&self) -> Oc1feR {
2364 Oc1feR { bits: self._oc1fe() }
2365 }
2366 fn _cc1s(&self) -> u8 {
2367 const MASK: u8 = 3;
2368 const OFFSET: u8 = 0;
2369 ((self.bits >> OFFSET) & MASK as u32) as u8
2370 }
2371 # [ doc = "Bits 0:1 - Capture/Compare 1 selection" ]
2372 pub fn cc1s(&self) -> Cc1sR {
2373 Cc1sR { bits: self._cc1s() }
2374 }
2375 }
2376 impl W {
2377 # [ doc = r" Reset value of the register" ]
2378 pub fn reset_value() -> W {
2379 W { bits: 0 }
2380 }
2381 # [ doc = r" Writes raw `bits` to the register" ]
2382 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
2383 self.bits = bits;
2384 self
2385 }
2386 # [ doc = "Bit 15 - Output compare 2 clear enable" ]
2387 pub fn oc2ce(&mut self) -> _Oc2ceW {
2388 _Oc2ceW { register: self }
2389 }
2390 # [ doc = "Bits 12:14 - Output compare 2 mode" ]
2391 pub fn oc2m(&mut self) -> _Oc2mW {
2392 _Oc2mW { register: self }
2393 }
2394 # [ doc = "Bit 11 - Output compare 2 preload enable" ]
2395 pub fn oc2pe(&mut self) -> _Oc2peW {
2396 _Oc2peW { register: self }
2397 }
2398 # [ doc = "Bit 10 - Output compare 2 fast enable" ]
2399 pub fn oc2fe(&mut self) -> _Oc2feW {
2400 _Oc2feW { register: self }
2401 }
2402 # [ doc = "Bits 8:9 - Capture/Compare 2 selection" ]
2403 pub fn cc2s(&mut self) -> _Cc2sW {
2404 _Cc2sW { register: self }
2405 }
2406 # [ doc = "Bit 7 - Output compare 1 clear enable" ]
2407 pub fn oc1ce(&mut self) -> _Oc1ceW {
2408 _Oc1ceW { register: self }
2409 }
2410 # [ doc = "Bits 4:6 - Output compare 1 mode" ]
2411 pub fn oc1m(&mut self) -> _Oc1mW {
2412 _Oc1mW { register: self }
2413 }
2414 # [ doc = "Bit 3 - Output compare 1 preload enable" ]
2415 pub fn oc1pe(&mut self) -> _Oc1peW {
2416 _Oc1peW { register: self }
2417 }
2418 # [ doc = "Bit 2 - Output compare 1 fast enable" ]
2419 pub fn oc1fe(&mut self) -> _Oc1feW {
2420 _Oc1feW { register: self }
2421 }
2422 # [ doc = "Bits 0:1 - Capture/Compare 1 selection" ]
2423 pub fn cc1s(&mut self) -> _Cc1sW {
2424 _Cc1sW { register: self }
2425 }
2426 }
2427}
2428
2429# [ doc = "capture/compare mode register 1 (input mode)" ]
2430# [ repr ( C ) ]
2431pub struct Ccmr1Input {
2432 register: ::volatile_register::RW<u32>,
2433}
2434
2435# [ doc = "capture/compare mode register 1 (input mode)" ]
2436pub mod ccmr1_input {
2437 # [ doc = r" Value read from the register" ]
2438 pub struct R {
2439 bits: u32,
2440 }
2441 # [ doc = r" Value to write to the register" ]
2442 pub struct W {
2443 bits: u32,
2444 }
2445 impl super::Ccmr1Input {
2446 # [ doc = r" Modifies the contents of the register" ]
2447 pub fn modify<F>(&mut self, f: F)
2448 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
2449 {
2450 let bits = self.register.read();
2451 let r = R { bits: bits };
2452 let mut w = W { bits: bits };
2453 f(&r, &mut w);
2454 self.register.write(w.bits);
2455 }
2456 # [ doc = r" Reads the contents of the register" ]
2457 pub fn read(&self) -> R {
2458 R { bits: self.register.read() }
2459 }
2460 # [ doc = r" Writes to the register" ]
2461 pub fn write<F>(&mut self, f: F)
2462 where F: FnOnce(&mut W) -> &mut W
2463 {
2464 let mut w = W::reset_value();
2465 f(&mut w);
2466 self.register.write(w.bits);
2467 }
2468 }
2469 # [ doc = "Value of the field IC2F" ]
2470 pub struct Ic2fR {
2471 bits: u8,
2472 }
2473 impl Ic2fR {
2474 # [ doc = r" Value of the field as raw bits" ]
2475 pub fn bits(&self) -> u8 {
2476 self.bits
2477 }
2478 }
2479 # [ doc = "Value of the field IC2PSC" ]
2480 pub struct Ic2pscR {
2481 bits: u8,
2482 }
2483 impl Ic2pscR {
2484 # [ doc = r" Value of the field as raw bits" ]
2485 pub fn bits(&self) -> u8 {
2486 self.bits
2487 }
2488 }
2489 # [ doc = "Value of the field CC2S" ]
2490 pub struct Cc2sR {
2491 bits: u8,
2492 }
2493 impl Cc2sR {
2494 # [ doc = r" Value of the field as raw bits" ]
2495 pub fn bits(&self) -> u8 {
2496 self.bits
2497 }
2498 }
2499 # [ doc = "Value of the field IC1F" ]
2500 pub struct Ic1fR {
2501 bits: u8,
2502 }
2503 impl Ic1fR {
2504 # [ doc = r" Value of the field as raw bits" ]
2505 pub fn bits(&self) -> u8 {
2506 self.bits
2507 }
2508 }
2509 # [ doc = "Value of the field IC1PSC" ]
2510 pub struct Ic1pscR {
2511 bits: u8,
2512 }
2513 impl Ic1pscR {
2514 # [ doc = r" Value of the field as raw bits" ]
2515 pub fn bits(&self) -> u8 {
2516 self.bits
2517 }
2518 }
2519 # [ doc = "Value of the field CC1S" ]
2520 pub struct Cc1sR {
2521 bits: u8,
2522 }
2523 impl Cc1sR {
2524 # [ doc = r" Value of the field as raw bits" ]
2525 pub fn bits(&self) -> u8 {
2526 self.bits
2527 }
2528 }
2529 # [ doc = r" Proxy" ]
2530 pub struct _Ic2fW<'a> {
2531 register: &'a mut W,
2532 }
2533 impl<'a> _Ic2fW<'a> {
2534 # [ doc = r" Writes raw `bits` to the field" ]
2535 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2536 const MASK: u8 = 15;
2537 const OFFSET: u8 = 12;
2538 self.register.bits &= !((MASK as u32) << OFFSET);
2539 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2540 self.register
2541 }
2542 }
2543 # [ doc = r" Proxy" ]
2544 pub struct _Ic2pscW<'a> {
2545 register: &'a mut W,
2546 }
2547 impl<'a> _Ic2pscW<'a> {
2548 # [ doc = r" Writes raw `bits` to the field" ]
2549 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2550 const MASK: u8 = 3;
2551 const OFFSET: u8 = 10;
2552 self.register.bits &= !((MASK as u32) << OFFSET);
2553 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2554 self.register
2555 }
2556 }
2557 # [ doc = r" Proxy" ]
2558 pub struct _Cc2sW<'a> {
2559 register: &'a mut W,
2560 }
2561 impl<'a> _Cc2sW<'a> {
2562 # [ doc = r" Writes raw `bits` to the field" ]
2563 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2564 const MASK: u8 = 3;
2565 const OFFSET: u8 = 8;
2566 self.register.bits &= !((MASK as u32) << OFFSET);
2567 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2568 self.register
2569 }
2570 }
2571 # [ doc = r" Proxy" ]
2572 pub struct _Ic1fW<'a> {
2573 register: &'a mut W,
2574 }
2575 impl<'a> _Ic1fW<'a> {
2576 # [ doc = r" Writes raw `bits` to the field" ]
2577 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2578 const MASK: u8 = 15;
2579 const OFFSET: u8 = 4;
2580 self.register.bits &= !((MASK as u32) << OFFSET);
2581 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2582 self.register
2583 }
2584 }
2585 # [ doc = r" Proxy" ]
2586 pub struct _Ic1pscW<'a> {
2587 register: &'a mut W,
2588 }
2589 impl<'a> _Ic1pscW<'a> {
2590 # [ doc = r" Writes raw `bits` to the field" ]
2591 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2592 const MASK: u8 = 3;
2593 const OFFSET: u8 = 2;
2594 self.register.bits &= !((MASK as u32) << OFFSET);
2595 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2596 self.register
2597 }
2598 }
2599 # [ doc = r" Proxy" ]
2600 pub struct _Cc1sW<'a> {
2601 register: &'a mut W,
2602 }
2603 impl<'a> _Cc1sW<'a> {
2604 # [ doc = r" Writes raw `bits` to the field" ]
2605 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2606 const MASK: u8 = 3;
2607 const OFFSET: u8 = 0;
2608 self.register.bits &= !((MASK as u32) << OFFSET);
2609 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2610 self.register
2611 }
2612 }
2613 impl R {
2614 # [ doc = r" Value of the register as raw bits" ]
2615 pub fn bits(&self) -> u32 {
2616 self.bits
2617 }
2618 fn _ic2f(&self) -> u8 {
2619 const MASK: u8 = 15;
2620 const OFFSET: u8 = 12;
2621 ((self.bits >> OFFSET) & MASK as u32) as u8
2622 }
2623 # [ doc = "Bits 12:15 - Input capture 2 filter" ]
2624 pub fn ic2f(&self) -> Ic2fR {
2625 Ic2fR { bits: self._ic2f() }
2626 }
2627 fn _ic2psc(&self) -> u8 {
2628 const MASK: u8 = 3;
2629 const OFFSET: u8 = 10;
2630 ((self.bits >> OFFSET) & MASK as u32) as u8
2631 }
2632 # [ doc = "Bits 10:11 - Input capture 2 prescaler" ]
2633 pub fn ic2psc(&self) -> Ic2pscR {
2634 Ic2pscR { bits: self._ic2psc() }
2635 }
2636 fn _cc2s(&self) -> u8 {
2637 const MASK: u8 = 3;
2638 const OFFSET: u8 = 8;
2639 ((self.bits >> OFFSET) & MASK as u32) as u8
2640 }
2641 # [ doc = "Bits 8:9 - Capture/compare 2 selection" ]
2642 pub fn cc2s(&self) -> Cc2sR {
2643 Cc2sR { bits: self._cc2s() }
2644 }
2645 fn _ic1f(&self) -> u8 {
2646 const MASK: u8 = 15;
2647 const OFFSET: u8 = 4;
2648 ((self.bits >> OFFSET) & MASK as u32) as u8
2649 }
2650 # [ doc = "Bits 4:7 - Input capture 1 filter" ]
2651 pub fn ic1f(&self) -> Ic1fR {
2652 Ic1fR { bits: self._ic1f() }
2653 }
2654 fn _ic1psc(&self) -> u8 {
2655 const MASK: u8 = 3;
2656 const OFFSET: u8 = 2;
2657 ((self.bits >> OFFSET) & MASK as u32) as u8
2658 }
2659 # [ doc = "Bits 2:3 - Input capture 1 prescaler" ]
2660 pub fn ic1psc(&self) -> Ic1pscR {
2661 Ic1pscR { bits: self._ic1psc() }
2662 }
2663 fn _cc1s(&self) -> u8 {
2664 const MASK: u8 = 3;
2665 const OFFSET: u8 = 0;
2666 ((self.bits >> OFFSET) & MASK as u32) as u8
2667 }
2668 # [ doc = "Bits 0:1 - Capture/Compare 1 selection" ]
2669 pub fn cc1s(&self) -> Cc1sR {
2670 Cc1sR { bits: self._cc1s() }
2671 }
2672 }
2673 impl W {
2674 # [ doc = r" Reset value of the register" ]
2675 pub fn reset_value() -> W {
2676 W { bits: 0 }
2677 }
2678 # [ doc = r" Writes raw `bits` to the register" ]
2679 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
2680 self.bits = bits;
2681 self
2682 }
2683 # [ doc = "Bits 12:15 - Input capture 2 filter" ]
2684 pub fn ic2f(&mut self) -> _Ic2fW {
2685 _Ic2fW { register: self }
2686 }
2687 # [ doc = "Bits 10:11 - Input capture 2 prescaler" ]
2688 pub fn ic2psc(&mut self) -> _Ic2pscW {
2689 _Ic2pscW { register: self }
2690 }
2691 # [ doc = "Bits 8:9 - Capture/compare 2 selection" ]
2692 pub fn cc2s(&mut self) -> _Cc2sW {
2693 _Cc2sW { register: self }
2694 }
2695 # [ doc = "Bits 4:7 - Input capture 1 filter" ]
2696 pub fn ic1f(&mut self) -> _Ic1fW {
2697 _Ic1fW { register: self }
2698 }
2699 # [ doc = "Bits 2:3 - Input capture 1 prescaler" ]
2700 pub fn ic1psc(&mut self) -> _Ic1pscW {
2701 _Ic1pscW { register: self }
2702 }
2703 # [ doc = "Bits 0:1 - Capture/Compare 1 selection" ]
2704 pub fn cc1s(&mut self) -> _Cc1sW {
2705 _Cc1sW { register: self }
2706 }
2707 }
2708}
2709
2710# [ doc = "capture/compare mode register 2 (output mode)" ]
2711# [ repr ( C ) ]
2712pub struct Ccmr2Output {
2713 register: ::volatile_register::RW<u32>,
2714}
2715
2716# [ doc = "capture/compare mode register 2 (output mode)" ]
2717pub mod ccmr2_output {
2718 # [ doc = r" Value read from the register" ]
2719 pub struct R {
2720 bits: u32,
2721 }
2722 # [ doc = r" Value to write to the register" ]
2723 pub struct W {
2724 bits: u32,
2725 }
2726 impl super::Ccmr2Output {
2727 # [ doc = r" Modifies the contents of the register" ]
2728 pub fn modify<F>(&mut self, f: F)
2729 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
2730 {
2731 let bits = self.register.read();
2732 let r = R { bits: bits };
2733 let mut w = W { bits: bits };
2734 f(&r, &mut w);
2735 self.register.write(w.bits);
2736 }
2737 # [ doc = r" Reads the contents of the register" ]
2738 pub fn read(&self) -> R {
2739 R { bits: self.register.read() }
2740 }
2741 # [ doc = r" Writes to the register" ]
2742 pub fn write<F>(&mut self, f: F)
2743 where F: FnOnce(&mut W) -> &mut W
2744 {
2745 let mut w = W::reset_value();
2746 f(&mut w);
2747 self.register.write(w.bits);
2748 }
2749 }
2750 # [ doc = "Value of the field OC4CE" ]
2751 pub struct Oc4ceR {
2752 bits: u8,
2753 }
2754 impl Oc4ceR {
2755 # [ doc = r" Value of the field as raw bits" ]
2756 pub fn bits(&self) -> u8 {
2757 self.bits
2758 }
2759 }
2760 # [ doc = "Value of the field OC4M" ]
2761 pub struct Oc4mR {
2762 bits: u8,
2763 }
2764 impl Oc4mR {
2765 # [ doc = r" Value of the field as raw bits" ]
2766 pub fn bits(&self) -> u8 {
2767 self.bits
2768 }
2769 }
2770 # [ doc = "Value of the field OC4PE" ]
2771 pub struct Oc4peR {
2772 bits: u8,
2773 }
2774 impl Oc4peR {
2775 # [ doc = r" Value of the field as raw bits" ]
2776 pub fn bits(&self) -> u8 {
2777 self.bits
2778 }
2779 }
2780 # [ doc = "Value of the field OC4FE" ]
2781 pub struct Oc4feR {
2782 bits: u8,
2783 }
2784 impl Oc4feR {
2785 # [ doc = r" Value of the field as raw bits" ]
2786 pub fn bits(&self) -> u8 {
2787 self.bits
2788 }
2789 }
2790 # [ doc = "Value of the field CC4S" ]
2791 pub struct Cc4sR {
2792 bits: u8,
2793 }
2794 impl Cc4sR {
2795 # [ doc = r" Value of the field as raw bits" ]
2796 pub fn bits(&self) -> u8 {
2797 self.bits
2798 }
2799 }
2800 # [ doc = "Value of the field OC3CE" ]
2801 pub struct Oc3ceR {
2802 bits: u8,
2803 }
2804 impl Oc3ceR {
2805 # [ doc = r" Value of the field as raw bits" ]
2806 pub fn bits(&self) -> u8 {
2807 self.bits
2808 }
2809 }
2810 # [ doc = "Value of the field OC3M" ]
2811 pub struct Oc3mR {
2812 bits: u8,
2813 }
2814 impl Oc3mR {
2815 # [ doc = r" Value of the field as raw bits" ]
2816 pub fn bits(&self) -> u8 {
2817 self.bits
2818 }
2819 }
2820 # [ doc = "Value of the field OC3PE" ]
2821 pub struct Oc3peR {
2822 bits: u8,
2823 }
2824 impl Oc3peR {
2825 # [ doc = r" Value of the field as raw bits" ]
2826 pub fn bits(&self) -> u8 {
2827 self.bits
2828 }
2829 }
2830 # [ doc = "Value of the field OC3FE" ]
2831 pub struct Oc3feR {
2832 bits: u8,
2833 }
2834 impl Oc3feR {
2835 # [ doc = r" Value of the field as raw bits" ]
2836 pub fn bits(&self) -> u8 {
2837 self.bits
2838 }
2839 }
2840 # [ doc = "Value of the field CC3S" ]
2841 pub struct Cc3sR {
2842 bits: u8,
2843 }
2844 impl Cc3sR {
2845 # [ doc = r" Value of the field as raw bits" ]
2846 pub fn bits(&self) -> u8 {
2847 self.bits
2848 }
2849 }
2850 # [ doc = r" Proxy" ]
2851 pub struct _Oc4ceW<'a> {
2852 register: &'a mut W,
2853 }
2854 impl<'a> _Oc4ceW<'a> {
2855 # [ doc = r" Writes raw `bits` to the field" ]
2856 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2857 const MASK: u8 = 1;
2858 const OFFSET: u8 = 15;
2859 self.register.bits &= !((MASK as u32) << OFFSET);
2860 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2861 self.register
2862 }
2863 }
2864 # [ doc = r" Proxy" ]
2865 pub struct _Oc4mW<'a> {
2866 register: &'a mut W,
2867 }
2868 impl<'a> _Oc4mW<'a> {
2869 # [ doc = r" Writes raw `bits` to the field" ]
2870 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2871 const MASK: u8 = 7;
2872 const OFFSET: u8 = 12;
2873 self.register.bits &= !((MASK as u32) << OFFSET);
2874 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2875 self.register
2876 }
2877 }
2878 # [ doc = r" Proxy" ]
2879 pub struct _Oc4peW<'a> {
2880 register: &'a mut W,
2881 }
2882 impl<'a> _Oc4peW<'a> {
2883 # [ doc = r" Writes raw `bits` to the field" ]
2884 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2885 const MASK: u8 = 1;
2886 const OFFSET: u8 = 11;
2887 self.register.bits &= !((MASK as u32) << OFFSET);
2888 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2889 self.register
2890 }
2891 }
2892 # [ doc = r" Proxy" ]
2893 pub struct _Oc4feW<'a> {
2894 register: &'a mut W,
2895 }
2896 impl<'a> _Oc4feW<'a> {
2897 # [ doc = r" Writes raw `bits` to the field" ]
2898 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2899 const MASK: u8 = 1;
2900 const OFFSET: u8 = 10;
2901 self.register.bits &= !((MASK as u32) << OFFSET);
2902 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2903 self.register
2904 }
2905 }
2906 # [ doc = r" Proxy" ]
2907 pub struct _Cc4sW<'a> {
2908 register: &'a mut W,
2909 }
2910 impl<'a> _Cc4sW<'a> {
2911 # [ doc = r" Writes raw `bits` to the field" ]
2912 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2913 const MASK: u8 = 3;
2914 const OFFSET: u8 = 8;
2915 self.register.bits &= !((MASK as u32) << OFFSET);
2916 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2917 self.register
2918 }
2919 }
2920 # [ doc = r" Proxy" ]
2921 pub struct _Oc3ceW<'a> {
2922 register: &'a mut W,
2923 }
2924 impl<'a> _Oc3ceW<'a> {
2925 # [ doc = r" Writes raw `bits` to the field" ]
2926 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2927 const MASK: u8 = 1;
2928 const OFFSET: u8 = 7;
2929 self.register.bits &= !((MASK as u32) << OFFSET);
2930 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2931 self.register
2932 }
2933 }
2934 # [ doc = r" Proxy" ]
2935 pub struct _Oc3mW<'a> {
2936 register: &'a mut W,
2937 }
2938 impl<'a> _Oc3mW<'a> {
2939 # [ doc = r" Writes raw `bits` to the field" ]
2940 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2941 const MASK: u8 = 7;
2942 const OFFSET: u8 = 4;
2943 self.register.bits &= !((MASK as u32) << OFFSET);
2944 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2945 self.register
2946 }
2947 }
2948 # [ doc = r" Proxy" ]
2949 pub struct _Oc3peW<'a> {
2950 register: &'a mut W,
2951 }
2952 impl<'a> _Oc3peW<'a> {
2953 # [ doc = r" Writes raw `bits` to the field" ]
2954 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2955 const MASK: u8 = 1;
2956 const OFFSET: u8 = 3;
2957 self.register.bits &= !((MASK as u32) << OFFSET);
2958 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2959 self.register
2960 }
2961 }
2962 # [ doc = r" Proxy" ]
2963 pub struct _Oc3feW<'a> {
2964 register: &'a mut W,
2965 }
2966 impl<'a> _Oc3feW<'a> {
2967 # [ doc = r" Writes raw `bits` to the field" ]
2968 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2969 const MASK: u8 = 1;
2970 const OFFSET: u8 = 2;
2971 self.register.bits &= !((MASK as u32) << OFFSET);
2972 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2973 self.register
2974 }
2975 }
2976 # [ doc = r" Proxy" ]
2977 pub struct _Cc3sW<'a> {
2978 register: &'a mut W,
2979 }
2980 impl<'a> _Cc3sW<'a> {
2981 # [ doc = r" Writes raw `bits` to the field" ]
2982 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
2983 const MASK: u8 = 3;
2984 const OFFSET: u8 = 0;
2985 self.register.bits &= !((MASK as u32) << OFFSET);
2986 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
2987 self.register
2988 }
2989 }
2990 impl R {
2991 # [ doc = r" Value of the register as raw bits" ]
2992 pub fn bits(&self) -> u32 {
2993 self.bits
2994 }
2995 fn _oc4ce(&self) -> u8 {
2996 const MASK: u8 = 1;
2997 const OFFSET: u8 = 15;
2998 ((self.bits >> OFFSET) & MASK as u32) as u8
2999 }
3000 # [ doc = "Bit 15 - Output compare 4 clear enable" ]
3001 pub fn oc4ce(&self) -> Oc4ceR {
3002 Oc4ceR { bits: self._oc4ce() }
3003 }
3004 fn _oc4m(&self) -> u8 {
3005 const MASK: u8 = 7;
3006 const OFFSET: u8 = 12;
3007 ((self.bits >> OFFSET) & MASK as u32) as u8
3008 }
3009 # [ doc = "Bits 12:14 - Output compare 4 mode" ]
3010 pub fn oc4m(&self) -> Oc4mR {
3011 Oc4mR { bits: self._oc4m() }
3012 }
3013 fn _oc4pe(&self) -> u8 {
3014 const MASK: u8 = 1;
3015 const OFFSET: u8 = 11;
3016 ((self.bits >> OFFSET) & MASK as u32) as u8
3017 }
3018 # [ doc = "Bit 11 - Output compare 4 preload enable" ]
3019 pub fn oc4pe(&self) -> Oc4peR {
3020 Oc4peR { bits: self._oc4pe() }
3021 }
3022 fn _oc4fe(&self) -> u8 {
3023 const MASK: u8 = 1;
3024 const OFFSET: u8 = 10;
3025 ((self.bits >> OFFSET) & MASK as u32) as u8
3026 }
3027 # [ doc = "Bit 10 - Output compare 4 fast enable" ]
3028 pub fn oc4fe(&self) -> Oc4feR {
3029 Oc4feR { bits: self._oc4fe() }
3030 }
3031 fn _cc4s(&self) -> u8 {
3032 const MASK: u8 = 3;
3033 const OFFSET: u8 = 8;
3034 ((self.bits >> OFFSET) & MASK as u32) as u8
3035 }
3036 # [ doc = "Bits 8:9 - Capture/Compare 4 selection" ]
3037 pub fn cc4s(&self) -> Cc4sR {
3038 Cc4sR { bits: self._cc4s() }
3039 }
3040 fn _oc3ce(&self) -> u8 {
3041 const MASK: u8 = 1;
3042 const OFFSET: u8 = 7;
3043 ((self.bits >> OFFSET) & MASK as u32) as u8
3044 }
3045 # [ doc = "Bit 7 - Output compare 3 clear enable" ]
3046 pub fn oc3ce(&self) -> Oc3ceR {
3047 Oc3ceR { bits: self._oc3ce() }
3048 }
3049 fn _oc3m(&self) -> u8 {
3050 const MASK: u8 = 7;
3051 const OFFSET: u8 = 4;
3052 ((self.bits >> OFFSET) & MASK as u32) as u8
3053 }
3054 # [ doc = "Bits 4:6 - Output compare 3 mode" ]
3055 pub fn oc3m(&self) -> Oc3mR {
3056 Oc3mR { bits: self._oc3m() }
3057 }
3058 fn _oc3pe(&self) -> u8 {
3059 const MASK: u8 = 1;
3060 const OFFSET: u8 = 3;
3061 ((self.bits >> OFFSET) & MASK as u32) as u8
3062 }
3063 # [ doc = "Bit 3 - Output compare 3 preload enable" ]
3064 pub fn oc3pe(&self) -> Oc3peR {
3065 Oc3peR { bits: self._oc3pe() }
3066 }
3067 fn _oc3fe(&self) -> u8 {
3068 const MASK: u8 = 1;
3069 const OFFSET: u8 = 2;
3070 ((self.bits >> OFFSET) & MASK as u32) as u8
3071 }
3072 # [ doc = "Bit 2 - Output compare 3 fast enable" ]
3073 pub fn oc3fe(&self) -> Oc3feR {
3074 Oc3feR { bits: self._oc3fe() }
3075 }
3076 fn _cc3s(&self) -> u8 {
3077 const MASK: u8 = 3;
3078 const OFFSET: u8 = 0;
3079 ((self.bits >> OFFSET) & MASK as u32) as u8
3080 }
3081 # [ doc = "Bits 0:1 - Capture/Compare 3 selection" ]
3082 pub fn cc3s(&self) -> Cc3sR {
3083 Cc3sR { bits: self._cc3s() }
3084 }
3085 }
3086 impl W {
3087 # [ doc = r" Reset value of the register" ]
3088 pub fn reset_value() -> W {
3089 W { bits: 0 }
3090 }
3091 # [ doc = r" Writes raw `bits` to the register" ]
3092 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
3093 self.bits = bits;
3094 self
3095 }
3096 # [ doc = "Bit 15 - Output compare 4 clear enable" ]
3097 pub fn oc4ce(&mut self) -> _Oc4ceW {
3098 _Oc4ceW { register: self }
3099 }
3100 # [ doc = "Bits 12:14 - Output compare 4 mode" ]
3101 pub fn oc4m(&mut self) -> _Oc4mW {
3102 _Oc4mW { register: self }
3103 }
3104 # [ doc = "Bit 11 - Output compare 4 preload enable" ]
3105 pub fn oc4pe(&mut self) -> _Oc4peW {
3106 _Oc4peW { register: self }
3107 }
3108 # [ doc = "Bit 10 - Output compare 4 fast enable" ]
3109 pub fn oc4fe(&mut self) -> _Oc4feW {
3110 _Oc4feW { register: self }
3111 }
3112 # [ doc = "Bits 8:9 - Capture/Compare 4 selection" ]
3113 pub fn cc4s(&mut self) -> _Cc4sW {
3114 _Cc4sW { register: self }
3115 }
3116 # [ doc = "Bit 7 - Output compare 3 clear enable" ]
3117 pub fn oc3ce(&mut self) -> _Oc3ceW {
3118 _Oc3ceW { register: self }
3119 }
3120 # [ doc = "Bits 4:6 - Output compare 3 mode" ]
3121 pub fn oc3m(&mut self) -> _Oc3mW {
3122 _Oc3mW { register: self }
3123 }
3124 # [ doc = "Bit 3 - Output compare 3 preload enable" ]
3125 pub fn oc3pe(&mut self) -> _Oc3peW {
3126 _Oc3peW { register: self }
3127 }
3128 # [ doc = "Bit 2 - Output compare 3 fast enable" ]
3129 pub fn oc3fe(&mut self) -> _Oc3feW {
3130 _Oc3feW { register: self }
3131 }
3132 # [ doc = "Bits 0:1 - Capture/Compare 3 selection" ]
3133 pub fn cc3s(&mut self) -> _Cc3sW {
3134 _Cc3sW { register: self }
3135 }
3136 }
3137}
3138
3139# [ doc = "capture/compare mode register 2 (input mode)" ]
3140# [ repr ( C ) ]
3141pub struct Ccmr2Input {
3142 register: ::volatile_register::RW<u32>,
3143}
3144
3145# [ doc = "capture/compare mode register 2 (input mode)" ]
3146pub mod ccmr2_input {
3147 # [ doc = r" Value read from the register" ]
3148 pub struct R {
3149 bits: u32,
3150 }
3151 # [ doc = r" Value to write to the register" ]
3152 pub struct W {
3153 bits: u32,
3154 }
3155 impl super::Ccmr2Input {
3156 # [ doc = r" Modifies the contents of the register" ]
3157 pub fn modify<F>(&mut self, f: F)
3158 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
3159 {
3160 let bits = self.register.read();
3161 let r = R { bits: bits };
3162 let mut w = W { bits: bits };
3163 f(&r, &mut w);
3164 self.register.write(w.bits);
3165 }
3166 # [ doc = r" Reads the contents of the register" ]
3167 pub fn read(&self) -> R {
3168 R { bits: self.register.read() }
3169 }
3170 # [ doc = r" Writes to the register" ]
3171 pub fn write<F>(&mut self, f: F)
3172 where F: FnOnce(&mut W) -> &mut W
3173 {
3174 let mut w = W::reset_value();
3175 f(&mut w);
3176 self.register.write(w.bits);
3177 }
3178 }
3179 # [ doc = "Value of the field IC4F" ]
3180 pub struct Ic4fR {
3181 bits: u8,
3182 }
3183 impl Ic4fR {
3184 # [ doc = r" Value of the field as raw bits" ]
3185 pub fn bits(&self) -> u8 {
3186 self.bits
3187 }
3188 }
3189 # [ doc = "Value of the field IC4PSC" ]
3190 pub struct Ic4pscR {
3191 bits: u8,
3192 }
3193 impl Ic4pscR {
3194 # [ doc = r" Value of the field as raw bits" ]
3195 pub fn bits(&self) -> u8 {
3196 self.bits
3197 }
3198 }
3199 # [ doc = "Value of the field CC4S" ]
3200 pub struct Cc4sR {
3201 bits: u8,
3202 }
3203 impl Cc4sR {
3204 # [ doc = r" Value of the field as raw bits" ]
3205 pub fn bits(&self) -> u8 {
3206 self.bits
3207 }
3208 }
3209 # [ doc = "Value of the field IC3F" ]
3210 pub struct Ic3fR {
3211 bits: u8,
3212 }
3213 impl Ic3fR {
3214 # [ doc = r" Value of the field as raw bits" ]
3215 pub fn bits(&self) -> u8 {
3216 self.bits
3217 }
3218 }
3219 # [ doc = "Value of the field IC3PSC" ]
3220 pub struct Ic3pscR {
3221 bits: u8,
3222 }
3223 impl Ic3pscR {
3224 # [ doc = r" Value of the field as raw bits" ]
3225 pub fn bits(&self) -> u8 {
3226 self.bits
3227 }
3228 }
3229 # [ doc = "Value of the field CC3S" ]
3230 pub struct Cc3sR {
3231 bits: u8,
3232 }
3233 impl Cc3sR {
3234 # [ doc = r" Value of the field as raw bits" ]
3235 pub fn bits(&self) -> u8 {
3236 self.bits
3237 }
3238 }
3239 # [ doc = r" Proxy" ]
3240 pub struct _Ic4fW<'a> {
3241 register: &'a mut W,
3242 }
3243 impl<'a> _Ic4fW<'a> {
3244 # [ doc = r" Writes raw `bits` to the field" ]
3245 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3246 const MASK: u8 = 15;
3247 const OFFSET: u8 = 12;
3248 self.register.bits &= !((MASK as u32) << OFFSET);
3249 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3250 self.register
3251 }
3252 }
3253 # [ doc = r" Proxy" ]
3254 pub struct _Ic4pscW<'a> {
3255 register: &'a mut W,
3256 }
3257 impl<'a> _Ic4pscW<'a> {
3258 # [ doc = r" Writes raw `bits` to the field" ]
3259 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3260 const MASK: u8 = 3;
3261 const OFFSET: u8 = 10;
3262 self.register.bits &= !((MASK as u32) << OFFSET);
3263 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3264 self.register
3265 }
3266 }
3267 # [ doc = r" Proxy" ]
3268 pub struct _Cc4sW<'a> {
3269 register: &'a mut W,
3270 }
3271 impl<'a> _Cc4sW<'a> {
3272 # [ doc = r" Writes raw `bits` to the field" ]
3273 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3274 const MASK: u8 = 3;
3275 const OFFSET: u8 = 8;
3276 self.register.bits &= !((MASK as u32) << OFFSET);
3277 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3278 self.register
3279 }
3280 }
3281 # [ doc = r" Proxy" ]
3282 pub struct _Ic3fW<'a> {
3283 register: &'a mut W,
3284 }
3285 impl<'a> _Ic3fW<'a> {
3286 # [ doc = r" Writes raw `bits` to the field" ]
3287 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3288 const MASK: u8 = 15;
3289 const OFFSET: u8 = 4;
3290 self.register.bits &= !((MASK as u32) << OFFSET);
3291 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3292 self.register
3293 }
3294 }
3295 # [ doc = r" Proxy" ]
3296 pub struct _Ic3pscW<'a> {
3297 register: &'a mut W,
3298 }
3299 impl<'a> _Ic3pscW<'a> {
3300 # [ doc = r" Writes raw `bits` to the field" ]
3301 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3302 const MASK: u8 = 3;
3303 const OFFSET: u8 = 2;
3304 self.register.bits &= !((MASK as u32) << OFFSET);
3305 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3306 self.register
3307 }
3308 }
3309 # [ doc = r" Proxy" ]
3310 pub struct _Cc3sW<'a> {
3311 register: &'a mut W,
3312 }
3313 impl<'a> _Cc3sW<'a> {
3314 # [ doc = r" Writes raw `bits` to the field" ]
3315 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3316 const MASK: u8 = 3;
3317 const OFFSET: u8 = 0;
3318 self.register.bits &= !((MASK as u32) << OFFSET);
3319 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3320 self.register
3321 }
3322 }
3323 impl R {
3324 # [ doc = r" Value of the register as raw bits" ]
3325 pub fn bits(&self) -> u32 {
3326 self.bits
3327 }
3328 fn _ic4f(&self) -> u8 {
3329 const MASK: u8 = 15;
3330 const OFFSET: u8 = 12;
3331 ((self.bits >> OFFSET) & MASK as u32) as u8
3332 }
3333 # [ doc = "Bits 12:15 - Input capture 4 filter" ]
3334 pub fn ic4f(&self) -> Ic4fR {
3335 Ic4fR { bits: self._ic4f() }
3336 }
3337 fn _ic4psc(&self) -> u8 {
3338 const MASK: u8 = 3;
3339 const OFFSET: u8 = 10;
3340 ((self.bits >> OFFSET) & MASK as u32) as u8
3341 }
3342 # [ doc = "Bits 10:11 - Input capture 4 prescaler" ]
3343 pub fn ic4psc(&self) -> Ic4pscR {
3344 Ic4pscR { bits: self._ic4psc() }
3345 }
3346 fn _cc4s(&self) -> u8 {
3347 const MASK: u8 = 3;
3348 const OFFSET: u8 = 8;
3349 ((self.bits >> OFFSET) & MASK as u32) as u8
3350 }
3351 # [ doc = "Bits 8:9 - Capture/Compare 4 selection" ]
3352 pub fn cc4s(&self) -> Cc4sR {
3353 Cc4sR { bits: self._cc4s() }
3354 }
3355 fn _ic3f(&self) -> u8 {
3356 const MASK: u8 = 15;
3357 const OFFSET: u8 = 4;
3358 ((self.bits >> OFFSET) & MASK as u32) as u8
3359 }
3360 # [ doc = "Bits 4:7 - Input capture 3 filter" ]
3361 pub fn ic3f(&self) -> Ic3fR {
3362 Ic3fR { bits: self._ic3f() }
3363 }
3364 fn _ic3psc(&self) -> u8 {
3365 const MASK: u8 = 3;
3366 const OFFSET: u8 = 2;
3367 ((self.bits >> OFFSET) & MASK as u32) as u8
3368 }
3369 # [ doc = "Bits 2:3 - Input capture 3 prescaler" ]
3370 pub fn ic3psc(&self) -> Ic3pscR {
3371 Ic3pscR { bits: self._ic3psc() }
3372 }
3373 fn _cc3s(&self) -> u8 {
3374 const MASK: u8 = 3;
3375 const OFFSET: u8 = 0;
3376 ((self.bits >> OFFSET) & MASK as u32) as u8
3377 }
3378 # [ doc = "Bits 0:1 - Capture/Compare 3 selection" ]
3379 pub fn cc3s(&self) -> Cc3sR {
3380 Cc3sR { bits: self._cc3s() }
3381 }
3382 }
3383 impl W {
3384 # [ doc = r" Reset value of the register" ]
3385 pub fn reset_value() -> W {
3386 W { bits: 0 }
3387 }
3388 # [ doc = r" Writes raw `bits` to the register" ]
3389 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
3390 self.bits = bits;
3391 self
3392 }
3393 # [ doc = "Bits 12:15 - Input capture 4 filter" ]
3394 pub fn ic4f(&mut self) -> _Ic4fW {
3395 _Ic4fW { register: self }
3396 }
3397 # [ doc = "Bits 10:11 - Input capture 4 prescaler" ]
3398 pub fn ic4psc(&mut self) -> _Ic4pscW {
3399 _Ic4pscW { register: self }
3400 }
3401 # [ doc = "Bits 8:9 - Capture/Compare 4 selection" ]
3402 pub fn cc4s(&mut self) -> _Cc4sW {
3403 _Cc4sW { register: self }
3404 }
3405 # [ doc = "Bits 4:7 - Input capture 3 filter" ]
3406 pub fn ic3f(&mut self) -> _Ic3fW {
3407 _Ic3fW { register: self }
3408 }
3409 # [ doc = "Bits 2:3 - Input capture 3 prescaler" ]
3410 pub fn ic3psc(&mut self) -> _Ic3pscW {
3411 _Ic3pscW { register: self }
3412 }
3413 # [ doc = "Bits 0:1 - Capture/Compare 3 selection" ]
3414 pub fn cc3s(&mut self) -> _Cc3sW {
3415 _Cc3sW { register: self }
3416 }
3417 }
3418}
3419
3420# [ doc = "capture/compare enable register" ]
3421# [ repr ( C ) ]
3422pub struct Ccer {
3423 register: ::volatile_register::RW<u32>,
3424}
3425
3426# [ doc = "capture/compare enable register" ]
3427pub mod ccer {
3428 # [ doc = r" Value read from the register" ]
3429 pub struct R {
3430 bits: u32,
3431 }
3432 # [ doc = r" Value to write to the register" ]
3433 pub struct W {
3434 bits: u32,
3435 }
3436 impl super::Ccer {
3437 # [ doc = r" Modifies the contents of the register" ]
3438 pub fn modify<F>(&mut self, f: F)
3439 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
3440 {
3441 let bits = self.register.read();
3442 let r = R { bits: bits };
3443 let mut w = W { bits: bits };
3444 f(&r, &mut w);
3445 self.register.write(w.bits);
3446 }
3447 # [ doc = r" Reads the contents of the register" ]
3448 pub fn read(&self) -> R {
3449 R { bits: self.register.read() }
3450 }
3451 # [ doc = r" Writes to the register" ]
3452 pub fn write<F>(&mut self, f: F)
3453 where F: FnOnce(&mut W) -> &mut W
3454 {
3455 let mut w = W::reset_value();
3456 f(&mut w);
3457 self.register.write(w.bits);
3458 }
3459 }
3460 # [ doc = "Value of the field CC4NP" ]
3461 pub struct Cc4npR {
3462 bits: u8,
3463 }
3464 impl Cc4npR {
3465 # [ doc = r" Value of the field as raw bits" ]
3466 pub fn bits(&self) -> u8 {
3467 self.bits
3468 }
3469 }
3470 # [ doc = "Value of the field CC4P" ]
3471 pub struct Cc4pR {
3472 bits: u8,
3473 }
3474 impl Cc4pR {
3475 # [ doc = r" Value of the field as raw bits" ]
3476 pub fn bits(&self) -> u8 {
3477 self.bits
3478 }
3479 }
3480 # [ doc = "Value of the field CC4E" ]
3481 pub struct Cc4eR {
3482 bits: u8,
3483 }
3484 impl Cc4eR {
3485 # [ doc = r" Value of the field as raw bits" ]
3486 pub fn bits(&self) -> u8 {
3487 self.bits
3488 }
3489 }
3490 # [ doc = "Value of the field CC3NP" ]
3491 pub struct Cc3npR {
3492 bits: u8,
3493 }
3494 impl Cc3npR {
3495 # [ doc = r" Value of the field as raw bits" ]
3496 pub fn bits(&self) -> u8 {
3497 self.bits
3498 }
3499 }
3500 # [ doc = "Value of the field CC3P" ]
3501 pub struct Cc3pR {
3502 bits: u8,
3503 }
3504 impl Cc3pR {
3505 # [ doc = r" Value of the field as raw bits" ]
3506 pub fn bits(&self) -> u8 {
3507 self.bits
3508 }
3509 }
3510 # [ doc = "Value of the field CC3E" ]
3511 pub struct Cc3eR {
3512 bits: u8,
3513 }
3514 impl Cc3eR {
3515 # [ doc = r" Value of the field as raw bits" ]
3516 pub fn bits(&self) -> u8 {
3517 self.bits
3518 }
3519 }
3520 # [ doc = "Value of the field CC2NP" ]
3521 pub struct Cc2npR {
3522 bits: u8,
3523 }
3524 impl Cc2npR {
3525 # [ doc = r" Value of the field as raw bits" ]
3526 pub fn bits(&self) -> u8 {
3527 self.bits
3528 }
3529 }
3530 # [ doc = "Value of the field CC2P" ]
3531 pub struct Cc2pR {
3532 bits: u8,
3533 }
3534 impl Cc2pR {
3535 # [ doc = r" Value of the field as raw bits" ]
3536 pub fn bits(&self) -> u8 {
3537 self.bits
3538 }
3539 }
3540 # [ doc = "Value of the field CC2E" ]
3541 pub struct Cc2eR {
3542 bits: u8,
3543 }
3544 impl Cc2eR {
3545 # [ doc = r" Value of the field as raw bits" ]
3546 pub fn bits(&self) -> u8 {
3547 self.bits
3548 }
3549 }
3550 # [ doc = "Value of the field CC1NP" ]
3551 pub struct Cc1npR {
3552 bits: u8,
3553 }
3554 impl Cc1npR {
3555 # [ doc = r" Value of the field as raw bits" ]
3556 pub fn bits(&self) -> u8 {
3557 self.bits
3558 }
3559 }
3560 # [ doc = "Value of the field CC1P" ]
3561 pub struct Cc1pR {
3562 bits: u8,
3563 }
3564 impl Cc1pR {
3565 # [ doc = r" Value of the field as raw bits" ]
3566 pub fn bits(&self) -> u8 {
3567 self.bits
3568 }
3569 }
3570 # [ doc = "Value of the field CC1E" ]
3571 pub struct Cc1eR {
3572 bits: u8,
3573 }
3574 impl Cc1eR {
3575 # [ doc = r" Value of the field as raw bits" ]
3576 pub fn bits(&self) -> u8 {
3577 self.bits
3578 }
3579 }
3580 # [ doc = r" Proxy" ]
3581 pub struct _Cc4npW<'a> {
3582 register: &'a mut W,
3583 }
3584 impl<'a> _Cc4npW<'a> {
3585 # [ doc = r" Writes raw `bits` to the field" ]
3586 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3587 const MASK: u8 = 1;
3588 const OFFSET: u8 = 15;
3589 self.register.bits &= !((MASK as u32) << OFFSET);
3590 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3591 self.register
3592 }
3593 }
3594 # [ doc = r" Proxy" ]
3595 pub struct _Cc4pW<'a> {
3596 register: &'a mut W,
3597 }
3598 impl<'a> _Cc4pW<'a> {
3599 # [ doc = r" Writes raw `bits` to the field" ]
3600 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3601 const MASK: u8 = 1;
3602 const OFFSET: u8 = 13;
3603 self.register.bits &= !((MASK as u32) << OFFSET);
3604 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3605 self.register
3606 }
3607 }
3608 # [ doc = r" Proxy" ]
3609 pub struct _Cc4eW<'a> {
3610 register: &'a mut W,
3611 }
3612 impl<'a> _Cc4eW<'a> {
3613 # [ doc = r" Writes raw `bits` to the field" ]
3614 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3615 const MASK: u8 = 1;
3616 const OFFSET: u8 = 12;
3617 self.register.bits &= !((MASK as u32) << OFFSET);
3618 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3619 self.register
3620 }
3621 }
3622 # [ doc = r" Proxy" ]
3623 pub struct _Cc3npW<'a> {
3624 register: &'a mut W,
3625 }
3626 impl<'a> _Cc3npW<'a> {
3627 # [ doc = r" Writes raw `bits` to the field" ]
3628 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3629 const MASK: u8 = 1;
3630 const OFFSET: u8 = 11;
3631 self.register.bits &= !((MASK as u32) << OFFSET);
3632 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3633 self.register
3634 }
3635 }
3636 # [ doc = r" Proxy" ]
3637 pub struct _Cc3pW<'a> {
3638 register: &'a mut W,
3639 }
3640 impl<'a> _Cc3pW<'a> {
3641 # [ doc = r" Writes raw `bits` to the field" ]
3642 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3643 const MASK: u8 = 1;
3644 const OFFSET: u8 = 9;
3645 self.register.bits &= !((MASK as u32) << OFFSET);
3646 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3647 self.register
3648 }
3649 }
3650 # [ doc = r" Proxy" ]
3651 pub struct _Cc3eW<'a> {
3652 register: &'a mut W,
3653 }
3654 impl<'a> _Cc3eW<'a> {
3655 # [ doc = r" Writes raw `bits` to the field" ]
3656 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3657 const MASK: u8 = 1;
3658 const OFFSET: u8 = 8;
3659 self.register.bits &= !((MASK as u32) << OFFSET);
3660 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3661 self.register
3662 }
3663 }
3664 # [ doc = r" Proxy" ]
3665 pub struct _Cc2npW<'a> {
3666 register: &'a mut W,
3667 }
3668 impl<'a> _Cc2npW<'a> {
3669 # [ doc = r" Writes raw `bits` to the field" ]
3670 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3671 const MASK: u8 = 1;
3672 const OFFSET: u8 = 7;
3673 self.register.bits &= !((MASK as u32) << OFFSET);
3674 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3675 self.register
3676 }
3677 }
3678 # [ doc = r" Proxy" ]
3679 pub struct _Cc2pW<'a> {
3680 register: &'a mut W,
3681 }
3682 impl<'a> _Cc2pW<'a> {
3683 # [ doc = r" Writes raw `bits` to the field" ]
3684 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3685 const MASK: u8 = 1;
3686 const OFFSET: u8 = 5;
3687 self.register.bits &= !((MASK as u32) << OFFSET);
3688 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3689 self.register
3690 }
3691 }
3692 # [ doc = r" Proxy" ]
3693 pub struct _Cc2eW<'a> {
3694 register: &'a mut W,
3695 }
3696 impl<'a> _Cc2eW<'a> {
3697 # [ doc = r" Writes raw `bits` to the field" ]
3698 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3699 const MASK: u8 = 1;
3700 const OFFSET: u8 = 4;
3701 self.register.bits &= !((MASK as u32) << OFFSET);
3702 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3703 self.register
3704 }
3705 }
3706 # [ doc = r" Proxy" ]
3707 pub struct _Cc1npW<'a> {
3708 register: &'a mut W,
3709 }
3710 impl<'a> _Cc1npW<'a> {
3711 # [ doc = r" Writes raw `bits` to the field" ]
3712 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3713 const MASK: u8 = 1;
3714 const OFFSET: u8 = 3;
3715 self.register.bits &= !((MASK as u32) << OFFSET);
3716 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3717 self.register
3718 }
3719 }
3720 # [ doc = r" Proxy" ]
3721 pub struct _Cc1pW<'a> {
3722 register: &'a mut W,
3723 }
3724 impl<'a> _Cc1pW<'a> {
3725 # [ doc = r" Writes raw `bits` to the field" ]
3726 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3727 const MASK: u8 = 1;
3728 const OFFSET: u8 = 1;
3729 self.register.bits &= !((MASK as u32) << OFFSET);
3730 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3731 self.register
3732 }
3733 }
3734 # [ doc = r" Proxy" ]
3735 pub struct _Cc1eW<'a> {
3736 register: &'a mut W,
3737 }
3738 impl<'a> _Cc1eW<'a> {
3739 # [ doc = r" Writes raw `bits` to the field" ]
3740 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
3741 const MASK: u8 = 1;
3742 const OFFSET: u8 = 0;
3743 self.register.bits &= !((MASK as u32) << OFFSET);
3744 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3745 self.register
3746 }
3747 }
3748 impl R {
3749 # [ doc = r" Value of the register as raw bits" ]
3750 pub fn bits(&self) -> u32 {
3751 self.bits
3752 }
3753 fn _cc4np(&self) -> u8 {
3754 const MASK: u8 = 1;
3755 const OFFSET: u8 = 15;
3756 ((self.bits >> OFFSET) & MASK as u32) as u8
3757 }
3758 # [ doc = "Bit 15 - Capture/Compare 4 output Polarity" ]
3759 pub fn cc4np(&self) -> Cc4npR {
3760 Cc4npR { bits: self._cc4np() }
3761 }
3762 fn _cc4p(&self) -> u8 {
3763 const MASK: u8 = 1;
3764 const OFFSET: u8 = 13;
3765 ((self.bits >> OFFSET) & MASK as u32) as u8
3766 }
3767 # [ doc = "Bit 13 - Capture/Compare 3 output Polarity" ]
3768 pub fn cc4p(&self) -> Cc4pR {
3769 Cc4pR { bits: self._cc4p() }
3770 }
3771 fn _cc4e(&self) -> u8 {
3772 const MASK: u8 = 1;
3773 const OFFSET: u8 = 12;
3774 ((self.bits >> OFFSET) & MASK as u32) as u8
3775 }
3776 # [ doc = "Bit 12 - Capture/Compare 4 output enable" ]
3777 pub fn cc4e(&self) -> Cc4eR {
3778 Cc4eR { bits: self._cc4e() }
3779 }
3780 fn _cc3np(&self) -> u8 {
3781 const MASK: u8 = 1;
3782 const OFFSET: u8 = 11;
3783 ((self.bits >> OFFSET) & MASK as u32) as u8
3784 }
3785 # [ doc = "Bit 11 - Capture/Compare 3 output Polarity" ]
3786 pub fn cc3np(&self) -> Cc3npR {
3787 Cc3npR { bits: self._cc3np() }
3788 }
3789 fn _cc3p(&self) -> u8 {
3790 const MASK: u8 = 1;
3791 const OFFSET: u8 = 9;
3792 ((self.bits >> OFFSET) & MASK as u32) as u8
3793 }
3794 # [ doc = "Bit 9 - Capture/Compare 3 output Polarity" ]
3795 pub fn cc3p(&self) -> Cc3pR {
3796 Cc3pR { bits: self._cc3p() }
3797 }
3798 fn _cc3e(&self) -> u8 {
3799 const MASK: u8 = 1;
3800 const OFFSET: u8 = 8;
3801 ((self.bits >> OFFSET) & MASK as u32) as u8
3802 }
3803 # [ doc = "Bit 8 - Capture/Compare 3 output enable" ]
3804 pub fn cc3e(&self) -> Cc3eR {
3805 Cc3eR { bits: self._cc3e() }
3806 }
3807 fn _cc2np(&self) -> u8 {
3808 const MASK: u8 = 1;
3809 const OFFSET: u8 = 7;
3810 ((self.bits >> OFFSET) & MASK as u32) as u8
3811 }
3812 # [ doc = "Bit 7 - Capture/Compare 2 output Polarity" ]
3813 pub fn cc2np(&self) -> Cc2npR {
3814 Cc2npR { bits: self._cc2np() }
3815 }
3816 fn _cc2p(&self) -> u8 {
3817 const MASK: u8 = 1;
3818 const OFFSET: u8 = 5;
3819 ((self.bits >> OFFSET) & MASK as u32) as u8
3820 }
3821 # [ doc = "Bit 5 - Capture/Compare 2 output Polarity" ]
3822 pub fn cc2p(&self) -> Cc2pR {
3823 Cc2pR { bits: self._cc2p() }
3824 }
3825 fn _cc2e(&self) -> u8 {
3826 const MASK: u8 = 1;
3827 const OFFSET: u8 = 4;
3828 ((self.bits >> OFFSET) & MASK as u32) as u8
3829 }
3830 # [ doc = "Bit 4 - Capture/Compare 2 output enable" ]
3831 pub fn cc2e(&self) -> Cc2eR {
3832 Cc2eR { bits: self._cc2e() }
3833 }
3834 fn _cc1np(&self) -> u8 {
3835 const MASK: u8 = 1;
3836 const OFFSET: u8 = 3;
3837 ((self.bits >> OFFSET) & MASK as u32) as u8
3838 }
3839 # [ doc = "Bit 3 - Capture/Compare 1 output Polarity" ]
3840 pub fn cc1np(&self) -> Cc1npR {
3841 Cc1npR { bits: self._cc1np() }
3842 }
3843 fn _cc1p(&self) -> u8 {
3844 const MASK: u8 = 1;
3845 const OFFSET: u8 = 1;
3846 ((self.bits >> OFFSET) & MASK as u32) as u8
3847 }
3848 # [ doc = "Bit 1 - Capture/Compare 1 output Polarity" ]
3849 pub fn cc1p(&self) -> Cc1pR {
3850 Cc1pR { bits: self._cc1p() }
3851 }
3852 fn _cc1e(&self) -> u8 {
3853 const MASK: u8 = 1;
3854 const OFFSET: u8 = 0;
3855 ((self.bits >> OFFSET) & MASK as u32) as u8
3856 }
3857 # [ doc = "Bit 0 - Capture/Compare 1 output enable" ]
3858 pub fn cc1e(&self) -> Cc1eR {
3859 Cc1eR { bits: self._cc1e() }
3860 }
3861 }
3862 impl W {
3863 # [ doc = r" Reset value of the register" ]
3864 pub fn reset_value() -> W {
3865 W { bits: 0 }
3866 }
3867 # [ doc = r" Writes raw `bits` to the register" ]
3868 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
3869 self.bits = bits;
3870 self
3871 }
3872 # [ doc = "Bit 15 - Capture/Compare 4 output Polarity" ]
3873 pub fn cc4np(&mut self) -> _Cc4npW {
3874 _Cc4npW { register: self }
3875 }
3876 # [ doc = "Bit 13 - Capture/Compare 3 output Polarity" ]
3877 pub fn cc4p(&mut self) -> _Cc4pW {
3878 _Cc4pW { register: self }
3879 }
3880 # [ doc = "Bit 12 - Capture/Compare 4 output enable" ]
3881 pub fn cc4e(&mut self) -> _Cc4eW {
3882 _Cc4eW { register: self }
3883 }
3884 # [ doc = "Bit 11 - Capture/Compare 3 output Polarity" ]
3885 pub fn cc3np(&mut self) -> _Cc3npW {
3886 _Cc3npW { register: self }
3887 }
3888 # [ doc = "Bit 9 - Capture/Compare 3 output Polarity" ]
3889 pub fn cc3p(&mut self) -> _Cc3pW {
3890 _Cc3pW { register: self }
3891 }
3892 # [ doc = "Bit 8 - Capture/Compare 3 output enable" ]
3893 pub fn cc3e(&mut self) -> _Cc3eW {
3894 _Cc3eW { register: self }
3895 }
3896 # [ doc = "Bit 7 - Capture/Compare 2 output Polarity" ]
3897 pub fn cc2np(&mut self) -> _Cc2npW {
3898 _Cc2npW { register: self }
3899 }
3900 # [ doc = "Bit 5 - Capture/Compare 2 output Polarity" ]
3901 pub fn cc2p(&mut self) -> _Cc2pW {
3902 _Cc2pW { register: self }
3903 }
3904 # [ doc = "Bit 4 - Capture/Compare 2 output enable" ]
3905 pub fn cc2e(&mut self) -> _Cc2eW {
3906 _Cc2eW { register: self }
3907 }
3908 # [ doc = "Bit 3 - Capture/Compare 1 output Polarity" ]
3909 pub fn cc1np(&mut self) -> _Cc1npW {
3910 _Cc1npW { register: self }
3911 }
3912 # [ doc = "Bit 1 - Capture/Compare 1 output Polarity" ]
3913 pub fn cc1p(&mut self) -> _Cc1pW {
3914 _Cc1pW { register: self }
3915 }
3916 # [ doc = "Bit 0 - Capture/Compare 1 output enable" ]
3917 pub fn cc1e(&mut self) -> _Cc1eW {
3918 _Cc1eW { register: self }
3919 }
3920 }
3921}
3922
3923# [ doc = "counter" ]
3924# [ repr ( C ) ]
3925pub struct Cnt {
3926 register: ::volatile_register::RW<u32>,
3927}
3928
3929# [ doc = "counter" ]
3930pub mod cnt {
3931 # [ doc = r" Value read from the register" ]
3932 pub struct R {
3933 bits: u32,
3934 }
3935 # [ doc = r" Value to write to the register" ]
3936 pub struct W {
3937 bits: u32,
3938 }
3939 impl super::Cnt {
3940 # [ doc = r" Modifies the contents of the register" ]
3941 pub fn modify<F>(&mut self, f: F)
3942 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
3943 {
3944 let bits = self.register.read();
3945 let r = R { bits: bits };
3946 let mut w = W { bits: bits };
3947 f(&r, &mut w);
3948 self.register.write(w.bits);
3949 }
3950 # [ doc = r" Reads the contents of the register" ]
3951 pub fn read(&self) -> R {
3952 R { bits: self.register.read() }
3953 }
3954 # [ doc = r" Writes to the register" ]
3955 pub fn write<F>(&mut self, f: F)
3956 where F: FnOnce(&mut W) -> &mut W
3957 {
3958 let mut w = W::reset_value();
3959 f(&mut w);
3960 self.register.write(w.bits);
3961 }
3962 }
3963 # [ doc = "Value of the field CNT_H" ]
3964 pub struct CntHR {
3965 bits: u16,
3966 }
3967 impl CntHR {
3968 # [ doc = r" Value of the field as raw bits" ]
3969 pub fn bits(&self) -> u16 {
3970 self.bits
3971 }
3972 }
3973 # [ doc = "Value of the field CNT_L" ]
3974 pub struct CntLR {
3975 bits: u16,
3976 }
3977 impl CntLR {
3978 # [ doc = r" Value of the field as raw bits" ]
3979 pub fn bits(&self) -> u16 {
3980 self.bits
3981 }
3982 }
3983 # [ doc = r" Proxy" ]
3984 pub struct _CntHW<'a> {
3985 register: &'a mut W,
3986 }
3987 impl<'a> _CntHW<'a> {
3988 # [ doc = r" Writes raw `bits` to the field" ]
3989 pub unsafe fn bits(self, bits: u16) -> &'a mut W {
3990 const MASK: u16 = 65535;
3991 const OFFSET: u8 = 16;
3992 self.register.bits &= !((MASK as u32) << OFFSET);
3993 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
3994 self.register
3995 }
3996 }
3997 # [ doc = r" Proxy" ]
3998 pub struct _CntLW<'a> {
3999 register: &'a mut W,
4000 }
4001 impl<'a> _CntLW<'a> {
4002 # [ doc = r" Writes raw `bits` to the field" ]
4003 pub unsafe fn bits(self, bits: u16) -> &'a mut W {
4004 const MASK: u16 = 65535;
4005 const OFFSET: u8 = 0;
4006 self.register.bits &= !((MASK as u32) << OFFSET);
4007 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4008 self.register
4009 }
4010 }
4011 impl R {
4012 # [ doc = r" Value of the register as raw bits" ]
4013 pub fn bits(&self) -> u32 {
4014 self.bits
4015 }
4016 fn _cnt_h(&self) -> u16 {
4017 const MASK: u16 = 65535;
4018 const OFFSET: u8 = 16;
4019 ((self.bits >> OFFSET) & MASK as u32) as u16
4020 }
4021 # [ doc = "Bits 16:31 - High counter value (TIM2 only)" ]
4022 pub fn cnt_h(&self) -> CntHR {
4023 CntHR { bits: self._cnt_h() }
4024 }
4025 fn _cnt_l(&self) -> u16 {
4026 const MASK: u16 = 65535;
4027 const OFFSET: u8 = 0;
4028 ((self.bits >> OFFSET) & MASK as u32) as u16
4029 }
4030 # [ doc = "Bits 0:15 - Low counter value" ]
4031 pub fn cnt_l(&self) -> CntLR {
4032 CntLR { bits: self._cnt_l() }
4033 }
4034 }
4035 impl W {
4036 # [ doc = r" Reset value of the register" ]
4037 pub fn reset_value() -> W {
4038 W { bits: 0 }
4039 }
4040 # [ doc = r" Writes raw `bits` to the register" ]
4041 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
4042 self.bits = bits;
4043 self
4044 }
4045 # [ doc = "Bits 16:31 - High counter value (TIM2 only)" ]
4046 pub fn cnt_h(&mut self) -> _CntHW {
4047 _CntHW { register: self }
4048 }
4049 # [ doc = "Bits 0:15 - Low counter value" ]
4050 pub fn cnt_l(&mut self) -> _CntLW {
4051 _CntLW { register: self }
4052 }
4053 }
4054}
4055
4056# [ doc = "prescaler" ]
4057# [ repr ( C ) ]
4058pub struct Psc {
4059 register: ::volatile_register::RW<u32>,
4060}
4061
4062# [ doc = "prescaler" ]
4063pub mod psc {
4064 # [ doc = r" Value read from the register" ]
4065 pub struct R {
4066 bits: u32,
4067 }
4068 # [ doc = r" Value to write to the register" ]
4069 pub struct W {
4070 bits: u32,
4071 }
4072 impl super::Psc {
4073 # [ doc = r" Modifies the contents of the register" ]
4074 pub fn modify<F>(&mut self, f: F)
4075 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
4076 {
4077 let bits = self.register.read();
4078 let r = R { bits: bits };
4079 let mut w = W { bits: bits };
4080 f(&r, &mut w);
4081 self.register.write(w.bits);
4082 }
4083 # [ doc = r" Reads the contents of the register" ]
4084 pub fn read(&self) -> R {
4085 R { bits: self.register.read() }
4086 }
4087 # [ doc = r" Writes to the register" ]
4088 pub fn write<F>(&mut self, f: F)
4089 where F: FnOnce(&mut W) -> &mut W
4090 {
4091 let mut w = W::reset_value();
4092 f(&mut w);
4093 self.register.write(w.bits);
4094 }
4095 }
4096 # [ doc = "Value of the field PSC" ]
4097 pub struct PscR {
4098 bits: u16,
4099 }
4100 impl PscR {
4101 # [ doc = r" Value of the field as raw bits" ]
4102 pub fn bits(&self) -> u16 {
4103 self.bits
4104 }
4105 }
4106 # [ doc = r" Proxy" ]
4107 pub struct _PscW<'a> {
4108 register: &'a mut W,
4109 }
4110 impl<'a> _PscW<'a> {
4111 # [ doc = r" Writes raw `bits` to the field" ]
4112 pub unsafe fn bits(self, bits: u16) -> &'a mut W {
4113 const MASK: u16 = 65535;
4114 const OFFSET: u8 = 0;
4115 self.register.bits &= !((MASK as u32) << OFFSET);
4116 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4117 self.register
4118 }
4119 }
4120 impl R {
4121 # [ doc = r" Value of the register as raw bits" ]
4122 pub fn bits(&self) -> u32 {
4123 self.bits
4124 }
4125 fn _psc(&self) -> u16 {
4126 const MASK: u16 = 65535;
4127 const OFFSET: u8 = 0;
4128 ((self.bits >> OFFSET) & MASK as u32) as u16
4129 }
4130 # [ doc = "Bits 0:15 - Prescaler value" ]
4131 pub fn psc(&self) -> PscR {
4132 PscR { bits: self._psc() }
4133 }
4134 }
4135 impl W {
4136 # [ doc = r" Reset value of the register" ]
4137 pub fn reset_value() -> W {
4138 W { bits: 0 }
4139 }
4140 # [ doc = r" Writes raw `bits` to the register" ]
4141 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
4142 self.bits = bits;
4143 self
4144 }
4145 # [ doc = "Bits 0:15 - Prescaler value" ]
4146 pub fn psc(&mut self) -> _PscW {
4147 _PscW { register: self }
4148 }
4149 }
4150}
4151
4152# [ doc = "auto-reload register" ]
4153# [ repr ( C ) ]
4154pub struct Arr {
4155 register: ::volatile_register::RW<u32>,
4156}
4157
4158# [ doc = "auto-reload register" ]
4159pub mod arr {
4160 # [ doc = r" Value read from the register" ]
4161 pub struct R {
4162 bits: u32,
4163 }
4164 # [ doc = r" Value to write to the register" ]
4165 pub struct W {
4166 bits: u32,
4167 }
4168 impl super::Arr {
4169 # [ doc = r" Modifies the contents of the register" ]
4170 pub fn modify<F>(&mut self, f: F)
4171 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
4172 {
4173 let bits = self.register.read();
4174 let r = R { bits: bits };
4175 let mut w = W { bits: bits };
4176 f(&r, &mut w);
4177 self.register.write(w.bits);
4178 }
4179 # [ doc = r" Reads the contents of the register" ]
4180 pub fn read(&self) -> R {
4181 R { bits: self.register.read() }
4182 }
4183 # [ doc = r" Writes to the register" ]
4184 pub fn write<F>(&mut self, f: F)
4185 where F: FnOnce(&mut W) -> &mut W
4186 {
4187 let mut w = W::reset_value();
4188 f(&mut w);
4189 self.register.write(w.bits);
4190 }
4191 }
4192 # [ doc = "Value of the field ARR_H" ]
4193 pub struct ArrHR {
4194 bits: u16,
4195 }
4196 impl ArrHR {
4197 # [ doc = r" Value of the field as raw bits" ]
4198 pub fn bits(&self) -> u16 {
4199 self.bits
4200 }
4201 }
4202 # [ doc = "Value of the field ARR_L" ]
4203 pub struct ArrLR {
4204 bits: u16,
4205 }
4206 impl ArrLR {
4207 # [ doc = r" Value of the field as raw bits" ]
4208 pub fn bits(&self) -> u16 {
4209 self.bits
4210 }
4211 }
4212 # [ doc = r" Proxy" ]
4213 pub struct _ArrHW<'a> {
4214 register: &'a mut W,
4215 }
4216 impl<'a> _ArrHW<'a> {
4217 # [ doc = r" Writes raw `bits` to the field" ]
4218 pub unsafe fn bits(self, bits: u16) -> &'a mut W {
4219 const MASK: u16 = 65535;
4220 const OFFSET: u8 = 16;
4221 self.register.bits &= !((MASK as u32) << OFFSET);
4222 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4223 self.register
4224 }
4225 }
4226 # [ doc = r" Proxy" ]
4227 pub struct _ArrLW<'a> {
4228 register: &'a mut W,
4229 }
4230 impl<'a> _ArrLW<'a> {
4231 # [ doc = r" Writes raw `bits` to the field" ]
4232 pub unsafe fn bits(self, bits: u16) -> &'a mut W {
4233 const MASK: u16 = 65535;
4234 const OFFSET: u8 = 0;
4235 self.register.bits &= !((MASK as u32) << OFFSET);
4236 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4237 self.register
4238 }
4239 }
4240 impl R {
4241 # [ doc = r" Value of the register as raw bits" ]
4242 pub fn bits(&self) -> u32 {
4243 self.bits
4244 }
4245 fn _arr_h(&self) -> u16 {
4246 const MASK: u16 = 65535;
4247 const OFFSET: u8 = 16;
4248 ((self.bits >> OFFSET) & MASK as u32) as u16
4249 }
4250 # [ doc = "Bits 16:31 - High Auto-reload value (TIM2 only)" ]
4251 pub fn arr_h(&self) -> ArrHR {
4252 ArrHR { bits: self._arr_h() }
4253 }
4254 fn _arr_l(&self) -> u16 {
4255 const MASK: u16 = 65535;
4256 const OFFSET: u8 = 0;
4257 ((self.bits >> OFFSET) & MASK as u32) as u16
4258 }
4259 # [ doc = "Bits 0:15 - Low Auto-reload value" ]
4260 pub fn arr_l(&self) -> ArrLR {
4261 ArrLR { bits: self._arr_l() }
4262 }
4263 }
4264 impl W {
4265 # [ doc = r" Reset value of the register" ]
4266 pub fn reset_value() -> W {
4267 W { bits: 0 }
4268 }
4269 # [ doc = r" Writes raw `bits` to the register" ]
4270 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
4271 self.bits = bits;
4272 self
4273 }
4274 # [ doc = "Bits 16:31 - High Auto-reload value (TIM2 only)" ]
4275 pub fn arr_h(&mut self) -> _ArrHW {
4276 _ArrHW { register: self }
4277 }
4278 # [ doc = "Bits 0:15 - Low Auto-reload value" ]
4279 pub fn arr_l(&mut self) -> _ArrLW {
4280 _ArrLW { register: self }
4281 }
4282 }
4283}
4284
4285# [ doc = "capture/compare register 1" ]
4286# [ repr ( C ) ]
4287pub struct Ccr1 {
4288 register: ::volatile_register::RW<u32>,
4289}
4290
4291# [ doc = "capture/compare register 1" ]
4292pub mod ccr1 {
4293 # [ doc = r" Value read from the register" ]
4294 pub struct R {
4295 bits: u32,
4296 }
4297 # [ doc = r" Value to write to the register" ]
4298 pub struct W {
4299 bits: u32,
4300 }
4301 impl super::Ccr1 {
4302 # [ doc = r" Modifies the contents of the register" ]
4303 pub fn modify<F>(&mut self, f: F)
4304 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
4305 {
4306 let bits = self.register.read();
4307 let r = R { bits: bits };
4308 let mut w = W { bits: bits };
4309 f(&r, &mut w);
4310 self.register.write(w.bits);
4311 }
4312 # [ doc = r" Reads the contents of the register" ]
4313 pub fn read(&self) -> R {
4314 R { bits: self.register.read() }
4315 }
4316 # [ doc = r" Writes to the register" ]
4317 pub fn write<F>(&mut self, f: F)
4318 where F: FnOnce(&mut W) -> &mut W
4319 {
4320 let mut w = W::reset_value();
4321 f(&mut w);
4322 self.register.write(w.bits);
4323 }
4324 }
4325 # [ doc = "Value of the field CCR1_H" ]
4326 pub struct Ccr1HR {
4327 bits: u16,
4328 }
4329 impl Ccr1HR {
4330 # [ doc = r" Value of the field as raw bits" ]
4331 pub fn bits(&self) -> u16 {
4332 self.bits
4333 }
4334 }
4335 # [ doc = "Value of the field CCR1_L" ]
4336 pub struct Ccr1LR {
4337 bits: u16,
4338 }
4339 impl Ccr1LR {
4340 # [ doc = r" Value of the field as raw bits" ]
4341 pub fn bits(&self) -> u16 {
4342 self.bits
4343 }
4344 }
4345 # [ doc = r" Proxy" ]
4346 pub struct _Ccr1HW<'a> {
4347 register: &'a mut W,
4348 }
4349 impl<'a> _Ccr1HW<'a> {
4350 # [ doc = r" Writes raw `bits` to the field" ]
4351 pub unsafe fn bits(self, bits: u16) -> &'a mut W {
4352 const MASK: u16 = 65535;
4353 const OFFSET: u8 = 16;
4354 self.register.bits &= !((MASK as u32) << OFFSET);
4355 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4356 self.register
4357 }
4358 }
4359 # [ doc = r" Proxy" ]
4360 pub struct _Ccr1LW<'a> {
4361 register: &'a mut W,
4362 }
4363 impl<'a> _Ccr1LW<'a> {
4364 # [ doc = r" Writes raw `bits` to the field" ]
4365 pub unsafe fn bits(self, bits: u16) -> &'a mut W {
4366 const MASK: u16 = 65535;
4367 const OFFSET: u8 = 0;
4368 self.register.bits &= !((MASK as u32) << OFFSET);
4369 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4370 self.register
4371 }
4372 }
4373 impl R {
4374 # [ doc = r" Value of the register as raw bits" ]
4375 pub fn bits(&self) -> u32 {
4376 self.bits
4377 }
4378 fn _ccr1_h(&self) -> u16 {
4379 const MASK: u16 = 65535;
4380 const OFFSET: u8 = 16;
4381 ((self.bits >> OFFSET) & MASK as u32) as u16
4382 }
4383 # [ doc = "Bits 16:31 - High Capture/Compare 1 value (TIM2 only)" ]
4384 pub fn ccr1_h(&self) -> Ccr1HR {
4385 Ccr1HR { bits: self._ccr1_h() }
4386 }
4387 fn _ccr1_l(&self) -> u16 {
4388 const MASK: u16 = 65535;
4389 const OFFSET: u8 = 0;
4390 ((self.bits >> OFFSET) & MASK as u32) as u16
4391 }
4392 # [ doc = "Bits 0:15 - Low Capture/Compare 1 value" ]
4393 pub fn ccr1_l(&self) -> Ccr1LR {
4394 Ccr1LR { bits: self._ccr1_l() }
4395 }
4396 }
4397 impl W {
4398 # [ doc = r" Reset value of the register" ]
4399 pub fn reset_value() -> W {
4400 W { bits: 0 }
4401 }
4402 # [ doc = r" Writes raw `bits` to the register" ]
4403 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
4404 self.bits = bits;
4405 self
4406 }
4407 # [ doc = "Bits 16:31 - High Capture/Compare 1 value (TIM2 only)" ]
4408 pub fn ccr1_h(&mut self) -> _Ccr1HW {
4409 _Ccr1HW { register: self }
4410 }
4411 # [ doc = "Bits 0:15 - Low Capture/Compare 1 value" ]
4412 pub fn ccr1_l(&mut self) -> _Ccr1LW {
4413 _Ccr1LW { register: self }
4414 }
4415 }
4416}
4417
4418# [ doc = "capture/compare register 2" ]
4419# [ repr ( C ) ]
4420pub struct Ccr2 {
4421 register: ::volatile_register::RW<u32>,
4422}
4423
4424# [ doc = "capture/compare register 2" ]
4425pub mod ccr2 {
4426 # [ doc = r" Value read from the register" ]
4427 pub struct R {
4428 bits: u32,
4429 }
4430 # [ doc = r" Value to write to the register" ]
4431 pub struct W {
4432 bits: u32,
4433 }
4434 impl super::Ccr2 {
4435 # [ doc = r" Modifies the contents of the register" ]
4436 pub fn modify<F>(&mut self, f: F)
4437 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
4438 {
4439 let bits = self.register.read();
4440 let r = R { bits: bits };
4441 let mut w = W { bits: bits };
4442 f(&r, &mut w);
4443 self.register.write(w.bits);
4444 }
4445 # [ doc = r" Reads the contents of the register" ]
4446 pub fn read(&self) -> R {
4447 R { bits: self.register.read() }
4448 }
4449 # [ doc = r" Writes to the register" ]
4450 pub fn write<F>(&mut self, f: F)
4451 where F: FnOnce(&mut W) -> &mut W
4452 {
4453 let mut w = W::reset_value();
4454 f(&mut w);
4455 self.register.write(w.bits);
4456 }
4457 }
4458 # [ doc = "Value of the field CCR2_H" ]
4459 pub struct Ccr2HR {
4460 bits: u16,
4461 }
4462 impl Ccr2HR {
4463 # [ doc = r" Value of the field as raw bits" ]
4464 pub fn bits(&self) -> u16 {
4465 self.bits
4466 }
4467 }
4468 # [ doc = "Value of the field CCR2_L" ]
4469 pub struct Ccr2LR {
4470 bits: u16,
4471 }
4472 impl Ccr2LR {
4473 # [ doc = r" Value of the field as raw bits" ]
4474 pub fn bits(&self) -> u16 {
4475 self.bits
4476 }
4477 }
4478 # [ doc = r" Proxy" ]
4479 pub struct _Ccr2HW<'a> {
4480 register: &'a mut W,
4481 }
4482 impl<'a> _Ccr2HW<'a> {
4483 # [ doc = r" Writes raw `bits` to the field" ]
4484 pub unsafe fn bits(self, bits: u16) -> &'a mut W {
4485 const MASK: u16 = 65535;
4486 const OFFSET: u8 = 16;
4487 self.register.bits &= !((MASK as u32) << OFFSET);
4488 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4489 self.register
4490 }
4491 }
4492 # [ doc = r" Proxy" ]
4493 pub struct _Ccr2LW<'a> {
4494 register: &'a mut W,
4495 }
4496 impl<'a> _Ccr2LW<'a> {
4497 # [ doc = r" Writes raw `bits` to the field" ]
4498 pub unsafe fn bits(self, bits: u16) -> &'a mut W {
4499 const MASK: u16 = 65535;
4500 const OFFSET: u8 = 0;
4501 self.register.bits &= !((MASK as u32) << OFFSET);
4502 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4503 self.register
4504 }
4505 }
4506 impl R {
4507 # [ doc = r" Value of the register as raw bits" ]
4508 pub fn bits(&self) -> u32 {
4509 self.bits
4510 }
4511 fn _ccr2_h(&self) -> u16 {
4512 const MASK: u16 = 65535;
4513 const OFFSET: u8 = 16;
4514 ((self.bits >> OFFSET) & MASK as u32) as u16
4515 }
4516 # [ doc = "Bits 16:31 - High Capture/Compare 2 value (TIM2 only)" ]
4517 pub fn ccr2_h(&self) -> Ccr2HR {
4518 Ccr2HR { bits: self._ccr2_h() }
4519 }
4520 fn _ccr2_l(&self) -> u16 {
4521 const MASK: u16 = 65535;
4522 const OFFSET: u8 = 0;
4523 ((self.bits >> OFFSET) & MASK as u32) as u16
4524 }
4525 # [ doc = "Bits 0:15 - Low Capture/Compare 2 value" ]
4526 pub fn ccr2_l(&self) -> Ccr2LR {
4527 Ccr2LR { bits: self._ccr2_l() }
4528 }
4529 }
4530 impl W {
4531 # [ doc = r" Reset value of the register" ]
4532 pub fn reset_value() -> W {
4533 W { bits: 0 }
4534 }
4535 # [ doc = r" Writes raw `bits` to the register" ]
4536 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
4537 self.bits = bits;
4538 self
4539 }
4540 # [ doc = "Bits 16:31 - High Capture/Compare 2 value (TIM2 only)" ]
4541 pub fn ccr2_h(&mut self) -> _Ccr2HW {
4542 _Ccr2HW { register: self }
4543 }
4544 # [ doc = "Bits 0:15 - Low Capture/Compare 2 value" ]
4545 pub fn ccr2_l(&mut self) -> _Ccr2LW {
4546 _Ccr2LW { register: self }
4547 }
4548 }
4549}
4550
4551# [ doc = "capture/compare register 3" ]
4552# [ repr ( C ) ]
4553pub struct Ccr3 {
4554 register: ::volatile_register::RW<u32>,
4555}
4556
4557# [ doc = "capture/compare register 3" ]
4558pub mod ccr3 {
4559 # [ doc = r" Value read from the register" ]
4560 pub struct R {
4561 bits: u32,
4562 }
4563 # [ doc = r" Value to write to the register" ]
4564 pub struct W {
4565 bits: u32,
4566 }
4567 impl super::Ccr3 {
4568 # [ doc = r" Modifies the contents of the register" ]
4569 pub fn modify<F>(&mut self, f: F)
4570 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
4571 {
4572 let bits = self.register.read();
4573 let r = R { bits: bits };
4574 let mut w = W { bits: bits };
4575 f(&r, &mut w);
4576 self.register.write(w.bits);
4577 }
4578 # [ doc = r" Reads the contents of the register" ]
4579 pub fn read(&self) -> R {
4580 R { bits: self.register.read() }
4581 }
4582 # [ doc = r" Writes to the register" ]
4583 pub fn write<F>(&mut self, f: F)
4584 where F: FnOnce(&mut W) -> &mut W
4585 {
4586 let mut w = W::reset_value();
4587 f(&mut w);
4588 self.register.write(w.bits);
4589 }
4590 }
4591 # [ doc = "Value of the field CCR3_H" ]
4592 pub struct Ccr3HR {
4593 bits: u16,
4594 }
4595 impl Ccr3HR {
4596 # [ doc = r" Value of the field as raw bits" ]
4597 pub fn bits(&self) -> u16 {
4598 self.bits
4599 }
4600 }
4601 # [ doc = "Value of the field CCR3_L" ]
4602 pub struct Ccr3LR {
4603 bits: u16,
4604 }
4605 impl Ccr3LR {
4606 # [ doc = r" Value of the field as raw bits" ]
4607 pub fn bits(&self) -> u16 {
4608 self.bits
4609 }
4610 }
4611 # [ doc = r" Proxy" ]
4612 pub struct _Ccr3HW<'a> {
4613 register: &'a mut W,
4614 }
4615 impl<'a> _Ccr3HW<'a> {
4616 # [ doc = r" Writes raw `bits` to the field" ]
4617 pub unsafe fn bits(self, bits: u16) -> &'a mut W {
4618 const MASK: u16 = 65535;
4619 const OFFSET: u8 = 16;
4620 self.register.bits &= !((MASK as u32) << OFFSET);
4621 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4622 self.register
4623 }
4624 }
4625 # [ doc = r" Proxy" ]
4626 pub struct _Ccr3LW<'a> {
4627 register: &'a mut W,
4628 }
4629 impl<'a> _Ccr3LW<'a> {
4630 # [ doc = r" Writes raw `bits` to the field" ]
4631 pub unsafe fn bits(self, bits: u16) -> &'a mut W {
4632 const MASK: u16 = 65535;
4633 const OFFSET: u8 = 0;
4634 self.register.bits &= !((MASK as u32) << OFFSET);
4635 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4636 self.register
4637 }
4638 }
4639 impl R {
4640 # [ doc = r" Value of the register as raw bits" ]
4641 pub fn bits(&self) -> u32 {
4642 self.bits
4643 }
4644 fn _ccr3_h(&self) -> u16 {
4645 const MASK: u16 = 65535;
4646 const OFFSET: u8 = 16;
4647 ((self.bits >> OFFSET) & MASK as u32) as u16
4648 }
4649 # [ doc = "Bits 16:31 - High Capture/Compare value (TIM2 only)" ]
4650 pub fn ccr3_h(&self) -> Ccr3HR {
4651 Ccr3HR { bits: self._ccr3_h() }
4652 }
4653 fn _ccr3_l(&self) -> u16 {
4654 const MASK: u16 = 65535;
4655 const OFFSET: u8 = 0;
4656 ((self.bits >> OFFSET) & MASK as u32) as u16
4657 }
4658 # [ doc = "Bits 0:15 - Low Capture/Compare value" ]
4659 pub fn ccr3_l(&self) -> Ccr3LR {
4660 Ccr3LR { bits: self._ccr3_l() }
4661 }
4662 }
4663 impl W {
4664 # [ doc = r" Reset value of the register" ]
4665 pub fn reset_value() -> W {
4666 W { bits: 0 }
4667 }
4668 # [ doc = r" Writes raw `bits` to the register" ]
4669 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
4670 self.bits = bits;
4671 self
4672 }
4673 # [ doc = "Bits 16:31 - High Capture/Compare value (TIM2 only)" ]
4674 pub fn ccr3_h(&mut self) -> _Ccr3HW {
4675 _Ccr3HW { register: self }
4676 }
4677 # [ doc = "Bits 0:15 - Low Capture/Compare value" ]
4678 pub fn ccr3_l(&mut self) -> _Ccr3LW {
4679 _Ccr3LW { register: self }
4680 }
4681 }
4682}
4683
4684# [ doc = "capture/compare register 4" ]
4685# [ repr ( C ) ]
4686pub struct Ccr4 {
4687 register: ::volatile_register::RW<u32>,
4688}
4689
4690# [ doc = "capture/compare register 4" ]
4691pub mod ccr4 {
4692 # [ doc = r" Value read from the register" ]
4693 pub struct R {
4694 bits: u32,
4695 }
4696 # [ doc = r" Value to write to the register" ]
4697 pub struct W {
4698 bits: u32,
4699 }
4700 impl super::Ccr4 {
4701 # [ doc = r" Modifies the contents of the register" ]
4702 pub fn modify<F>(&mut self, f: F)
4703 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
4704 {
4705 let bits = self.register.read();
4706 let r = R { bits: bits };
4707 let mut w = W { bits: bits };
4708 f(&r, &mut w);
4709 self.register.write(w.bits);
4710 }
4711 # [ doc = r" Reads the contents of the register" ]
4712 pub fn read(&self) -> R {
4713 R { bits: self.register.read() }
4714 }
4715 # [ doc = r" Writes to the register" ]
4716 pub fn write<F>(&mut self, f: F)
4717 where F: FnOnce(&mut W) -> &mut W
4718 {
4719 let mut w = W::reset_value();
4720 f(&mut w);
4721 self.register.write(w.bits);
4722 }
4723 }
4724 # [ doc = "Value of the field CCR4_H" ]
4725 pub struct Ccr4HR {
4726 bits: u16,
4727 }
4728 impl Ccr4HR {
4729 # [ doc = r" Value of the field as raw bits" ]
4730 pub fn bits(&self) -> u16 {
4731 self.bits
4732 }
4733 }
4734 # [ doc = "Value of the field CCR4_L" ]
4735 pub struct Ccr4LR {
4736 bits: u16,
4737 }
4738 impl Ccr4LR {
4739 # [ doc = r" Value of the field as raw bits" ]
4740 pub fn bits(&self) -> u16 {
4741 self.bits
4742 }
4743 }
4744 # [ doc = r" Proxy" ]
4745 pub struct _Ccr4HW<'a> {
4746 register: &'a mut W,
4747 }
4748 impl<'a> _Ccr4HW<'a> {
4749 # [ doc = r" Writes raw `bits` to the field" ]
4750 pub unsafe fn bits(self, bits: u16) -> &'a mut W {
4751 const MASK: u16 = 65535;
4752 const OFFSET: u8 = 16;
4753 self.register.bits &= !((MASK as u32) << OFFSET);
4754 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4755 self.register
4756 }
4757 }
4758 # [ doc = r" Proxy" ]
4759 pub struct _Ccr4LW<'a> {
4760 register: &'a mut W,
4761 }
4762 impl<'a> _Ccr4LW<'a> {
4763 # [ doc = r" Writes raw `bits` to the field" ]
4764 pub unsafe fn bits(self, bits: u16) -> &'a mut W {
4765 const MASK: u16 = 65535;
4766 const OFFSET: u8 = 0;
4767 self.register.bits &= !((MASK as u32) << OFFSET);
4768 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4769 self.register
4770 }
4771 }
4772 impl R {
4773 # [ doc = r" Value of the register as raw bits" ]
4774 pub fn bits(&self) -> u32 {
4775 self.bits
4776 }
4777 fn _ccr4_h(&self) -> u16 {
4778 const MASK: u16 = 65535;
4779 const OFFSET: u8 = 16;
4780 ((self.bits >> OFFSET) & MASK as u32) as u16
4781 }
4782 # [ doc = "Bits 16:31 - High Capture/Compare value (TIM2 only)" ]
4783 pub fn ccr4_h(&self) -> Ccr4HR {
4784 Ccr4HR { bits: self._ccr4_h() }
4785 }
4786 fn _ccr4_l(&self) -> u16 {
4787 const MASK: u16 = 65535;
4788 const OFFSET: u8 = 0;
4789 ((self.bits >> OFFSET) & MASK as u32) as u16
4790 }
4791 # [ doc = "Bits 0:15 - Low Capture/Compare value" ]
4792 pub fn ccr4_l(&self) -> Ccr4LR {
4793 Ccr4LR { bits: self._ccr4_l() }
4794 }
4795 }
4796 impl W {
4797 # [ doc = r" Reset value of the register" ]
4798 pub fn reset_value() -> W {
4799 W { bits: 0 }
4800 }
4801 # [ doc = r" Writes raw `bits` to the register" ]
4802 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
4803 self.bits = bits;
4804 self
4805 }
4806 # [ doc = "Bits 16:31 - High Capture/Compare value (TIM2 only)" ]
4807 pub fn ccr4_h(&mut self) -> _Ccr4HW {
4808 _Ccr4HW { register: self }
4809 }
4810 # [ doc = "Bits 0:15 - Low Capture/Compare value" ]
4811 pub fn ccr4_l(&mut self) -> _Ccr4LW {
4812 _Ccr4LW { register: self }
4813 }
4814 }
4815}
4816
4817# [ doc = "DMA control register" ]
4818# [ repr ( C ) ]
4819pub struct Dcr {
4820 register: ::volatile_register::RW<u32>,
4821}
4822
4823# [ doc = "DMA control register" ]
4824pub mod dcr {
4825 # [ doc = r" Value read from the register" ]
4826 pub struct R {
4827 bits: u32,
4828 }
4829 # [ doc = r" Value to write to the register" ]
4830 pub struct W {
4831 bits: u32,
4832 }
4833 impl super::Dcr {
4834 # [ doc = r" Modifies the contents of the register" ]
4835 pub fn modify<F>(&mut self, f: F)
4836 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
4837 {
4838 let bits = self.register.read();
4839 let r = R { bits: bits };
4840 let mut w = W { bits: bits };
4841 f(&r, &mut w);
4842 self.register.write(w.bits);
4843 }
4844 # [ doc = r" Reads the contents of the register" ]
4845 pub fn read(&self) -> R {
4846 R { bits: self.register.read() }
4847 }
4848 # [ doc = r" Writes to the register" ]
4849 pub fn write<F>(&mut self, f: F)
4850 where F: FnOnce(&mut W) -> &mut W
4851 {
4852 let mut w = W::reset_value();
4853 f(&mut w);
4854 self.register.write(w.bits);
4855 }
4856 }
4857 # [ doc = "Value of the field DBL" ]
4858 pub struct DblR {
4859 bits: u8,
4860 }
4861 impl DblR {
4862 # [ doc = r" Value of the field as raw bits" ]
4863 pub fn bits(&self) -> u8 {
4864 self.bits
4865 }
4866 }
4867 # [ doc = "Value of the field DBA" ]
4868 pub struct DbaR {
4869 bits: u8,
4870 }
4871 impl DbaR {
4872 # [ doc = r" Value of the field as raw bits" ]
4873 pub fn bits(&self) -> u8 {
4874 self.bits
4875 }
4876 }
4877 # [ doc = r" Proxy" ]
4878 pub struct _DblW<'a> {
4879 register: &'a mut W,
4880 }
4881 impl<'a> _DblW<'a> {
4882 # [ doc = r" Writes raw `bits` to the field" ]
4883 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
4884 const MASK: u8 = 31;
4885 const OFFSET: u8 = 8;
4886 self.register.bits &= !((MASK as u32) << OFFSET);
4887 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4888 self.register
4889 }
4890 }
4891 # [ doc = r" Proxy" ]
4892 pub struct _DbaW<'a> {
4893 register: &'a mut W,
4894 }
4895 impl<'a> _DbaW<'a> {
4896 # [ doc = r" Writes raw `bits` to the field" ]
4897 pub unsafe fn bits(self, bits: u8) -> &'a mut W {
4898 const MASK: u8 = 31;
4899 const OFFSET: u8 = 0;
4900 self.register.bits &= !((MASK as u32) << OFFSET);
4901 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
4902 self.register
4903 }
4904 }
4905 impl R {
4906 # [ doc = r" Value of the register as raw bits" ]
4907 pub fn bits(&self) -> u32 {
4908 self.bits
4909 }
4910 fn _dbl(&self) -> u8 {
4911 const MASK: u8 = 31;
4912 const OFFSET: u8 = 8;
4913 ((self.bits >> OFFSET) & MASK as u32) as u8
4914 }
4915 # [ doc = "Bits 8:12 - DMA burst length" ]
4916 pub fn dbl(&self) -> DblR {
4917 DblR { bits: self._dbl() }
4918 }
4919 fn _dba(&self) -> u8 {
4920 const MASK: u8 = 31;
4921 const OFFSET: u8 = 0;
4922 ((self.bits >> OFFSET) & MASK as u32) as u8
4923 }
4924 # [ doc = "Bits 0:4 - DMA base address" ]
4925 pub fn dba(&self) -> DbaR {
4926 DbaR { bits: self._dba() }
4927 }
4928 }
4929 impl W {
4930 # [ doc = r" Reset value of the register" ]
4931 pub fn reset_value() -> W {
4932 W { bits: 0 }
4933 }
4934 # [ doc = r" Writes raw `bits` to the register" ]
4935 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
4936 self.bits = bits;
4937 self
4938 }
4939 # [ doc = "Bits 8:12 - DMA burst length" ]
4940 pub fn dbl(&mut self) -> _DblW {
4941 _DblW { register: self }
4942 }
4943 # [ doc = "Bits 0:4 - DMA base address" ]
4944 pub fn dba(&mut self) -> _DbaW {
4945 _DbaW { register: self }
4946 }
4947 }
4948}
4949
4950# [ doc = "DMA address for full transfer" ]
4951# [ repr ( C ) ]
4952pub struct Dmar {
4953 register: ::volatile_register::RW<u32>,
4954}
4955
4956# [ doc = "DMA address for full transfer" ]
4957pub mod dmar {
4958 # [ doc = r" Value read from the register" ]
4959 pub struct R {
4960 bits: u32,
4961 }
4962 # [ doc = r" Value to write to the register" ]
4963 pub struct W {
4964 bits: u32,
4965 }
4966 impl super::Dmar {
4967 # [ doc = r" Modifies the contents of the register" ]
4968 pub fn modify<F>(&mut self, f: F)
4969 where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W
4970 {
4971 let bits = self.register.read();
4972 let r = R { bits: bits };
4973 let mut w = W { bits: bits };
4974 f(&r, &mut w);
4975 self.register.write(w.bits);
4976 }
4977 # [ doc = r" Reads the contents of the register" ]
4978 pub fn read(&self) -> R {
4979 R { bits: self.register.read() }
4980 }
4981 # [ doc = r" Writes to the register" ]
4982 pub fn write<F>(&mut self, f: F)
4983 where F: FnOnce(&mut W) -> &mut W
4984 {
4985 let mut w = W::reset_value();
4986 f(&mut w);
4987 self.register.write(w.bits);
4988 }
4989 }
4990 # [ doc = "Value of the field DMAR" ]
4991 pub struct DmarR {
4992 bits: u16,
4993 }
4994 impl DmarR {
4995 # [ doc = r" Value of the field as raw bits" ]
4996 pub fn bits(&self) -> u16 {
4997 self.bits
4998 }
4999 }
5000 # [ doc = r" Proxy" ]
5001 pub struct _DmarW<'a> {
5002 register: &'a mut W,
5003 }
5004 impl<'a> _DmarW<'a> {
5005 # [ doc = r" Writes raw `bits` to the field" ]
5006 pub unsafe fn bits(self, bits: u16) -> &'a mut W {
5007 const MASK: u16 = 65535;
5008 const OFFSET: u8 = 0;
5009 self.register.bits &= !((MASK as u32) << OFFSET);
5010 self.register.bits |= ((bits & MASK) as u32) << OFFSET;
5011 self.register
5012 }
5013 }
5014 impl R {
5015 # [ doc = r" Value of the register as raw bits" ]
5016 pub fn bits(&self) -> u32 {
5017 self.bits
5018 }
5019 fn _dmar(&self) -> u16 {
5020 const MASK: u16 = 65535;
5021 const OFFSET: u8 = 0;
5022 ((self.bits >> OFFSET) & MASK as u32) as u16
5023 }
5024 # [ doc = "Bits 0:15 - DMA register for burst accesses" ]
5025 pub fn dmar(&self) -> DmarR {
5026 DmarR { bits: self._dmar() }
5027 }
5028 }
5029 impl W {
5030 # [ doc = r" Reset value of the register" ]
5031 pub fn reset_value() -> W {
5032 W { bits: 0 }
5033 }
5034 # [ doc = r" Writes raw `bits` to the register" ]
5035 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
5036 self.bits = bits;
5037 self
5038 }
5039 # [ doc = "Bits 0:15 - DMA register for burst accesses" ]
5040 pub fn dmar(&mut self) -> _DmarW {
5041 _DmarW { register: self }
5042 }
5043 }
5044}