Struct stm32f0::stm32f0x8::rcc::cfgr::R

pub struct R(_);

Register CFGR reader

Implementations

impl R

pub fn sw(&self) -> SW_R

Bits 0:1 - System clock Switch

pub fn sws(&self) -> SWS_R

Bits 2:3 - System Clock Switch Status

pub fn hpre(&self) -> HPRE_R

Bits 4:7 - AHB prescaler

pub fn ppre(&self) -> PPRE_R

Bits 8:10 - APB Low speed prescaler (APB1)

pub fn adcpre(&self) -> ADCPRE_R

Bit 14 - ADCPRE is deprecated. See ADC field in CFGR2 register.

pub fn pllsrc(&self) -> PLLSRC_R

Bits 15:16 - PLL input clock source

pub fn pllxtpre(&self) -> PLLXTPRE_R

Bit 17 - HSE divider for PLL entry. Same bit as PREDIC[0] from CFGR2 register. Refer to it for its meaning

pub fn pllmul(&self) -> PLLMUL_R

Bits 18:21 - PLL Multiplication Factor

pub fn mco(&self) -> MCO_R

Bits 24:27 - Microcontroller clock output

pub fn mcopre(&self) -> MCOPRE_R

Bits 28:30 - Microcontroller Clock Output Prescaler

pub fn pllnodiv(&self) -> PLLNODIV_R

Bit 31 - PLL clock not divided for MCO

Methods from Deref<Target = R<CFGR_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CFGR_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<CFGR_SPEC>> for R

fn from(reader: R<CFGR_SPEC>) -> Self

Converts to this type from the input type.