stm32f0/stm32f0x8/pwr/
cr.rs

1///Register `CR` reader
2pub type R = crate::R<CRrs>;
3///Register `CR` writer
4pub type W = crate::W<CRrs>;
5///Field `LPDS` reader - Low-power deep sleep
6pub type LPDS_R = crate::BitReader;
7///Field `LPDS` writer - Low-power deep sleep
8pub type LPDS_W<'a, REG> = crate::BitWriter<'a, REG>;
9/**Power down deepsleep
10
11Value on reset: 0*/
12#[cfg_attr(feature = "defmt", derive(defmt::Format))]
13#[derive(Clone, Copy, Debug, PartialEq, Eq)]
14pub enum PDDS {
15    ///0: Enter Stop mode when the CPU enters deepsleep
16    StopMode = 0,
17    ///1: Enter Standby mode when the CPU enters deepsleep
18    StandbyMode = 1,
19}
20impl From<PDDS> for bool {
21    #[inline(always)]
22    fn from(variant: PDDS) -> Self {
23        variant as u8 != 0
24    }
25}
26///Field `PDDS` reader - Power down deepsleep
27pub type PDDS_R = crate::BitReader<PDDS>;
28impl PDDS_R {
29    ///Get enumerated values variant
30    #[inline(always)]
31    pub const fn variant(&self) -> PDDS {
32        match self.bits {
33            false => PDDS::StopMode,
34            true => PDDS::StandbyMode,
35        }
36    }
37    ///Enter Stop mode when the CPU enters deepsleep
38    #[inline(always)]
39    pub fn is_stop_mode(&self) -> bool {
40        *self == PDDS::StopMode
41    }
42    ///Enter Standby mode when the CPU enters deepsleep
43    #[inline(always)]
44    pub fn is_standby_mode(&self) -> bool {
45        *self == PDDS::StandbyMode
46    }
47}
48///Field `PDDS` writer - Power down deepsleep
49pub type PDDS_W<'a, REG> = crate::BitWriter<'a, REG, PDDS>;
50impl<'a, REG> PDDS_W<'a, REG>
51where
52    REG: crate::Writable + crate::RegisterSpec,
53{
54    ///Enter Stop mode when the CPU enters deepsleep
55    #[inline(always)]
56    pub fn stop_mode(self) -> &'a mut crate::W<REG> {
57        self.variant(PDDS::StopMode)
58    }
59    ///Enter Standby mode when the CPU enters deepsleep
60    #[inline(always)]
61    pub fn standby_mode(self) -> &'a mut crate::W<REG> {
62        self.variant(PDDS::StandbyMode)
63    }
64}
65///Field `CWUF` reader - Clear wakeup flag
66pub type CWUF_R = crate::BitReader;
67///Field `CWUF` writer - Clear wakeup flag
68pub type CWUF_W<'a, REG> = crate::BitWriter<'a, REG>;
69///Field `CSBF` reader - Clear standby flag
70pub type CSBF_R = crate::BitReader;
71///Field `CSBF` writer - Clear standby flag
72pub type CSBF_W<'a, REG> = crate::BitWriter<'a, REG>;
73///Field `PVDE` reader - Power voltage detector enable
74pub type PVDE_R = crate::BitReader;
75///Field `PVDE` writer - Power voltage detector enable
76pub type PVDE_W<'a, REG> = crate::BitWriter<'a, REG>;
77///Field `PLS` reader - PVD level selection
78pub type PLS_R = crate::FieldReader;
79///Field `PLS` writer - PVD level selection
80pub type PLS_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
81///Field `DBP` reader - Disable backup domain write protection
82pub type DBP_R = crate::BitReader;
83///Field `DBP` writer - Disable backup domain write protection
84pub type DBP_W<'a, REG> = crate::BitWriter<'a, REG>;
85impl R {
86    ///Bit 0 - Low-power deep sleep
87    #[inline(always)]
88    pub fn lpds(&self) -> LPDS_R {
89        LPDS_R::new((self.bits & 1) != 0)
90    }
91    ///Bit 1 - Power down deepsleep
92    #[inline(always)]
93    pub fn pdds(&self) -> PDDS_R {
94        PDDS_R::new(((self.bits >> 1) & 1) != 0)
95    }
96    ///Bit 2 - Clear wakeup flag
97    #[inline(always)]
98    pub fn cwuf(&self) -> CWUF_R {
99        CWUF_R::new(((self.bits >> 2) & 1) != 0)
100    }
101    ///Bit 3 - Clear standby flag
102    #[inline(always)]
103    pub fn csbf(&self) -> CSBF_R {
104        CSBF_R::new(((self.bits >> 3) & 1) != 0)
105    }
106    ///Bit 4 - Power voltage detector enable
107    #[inline(always)]
108    pub fn pvde(&self) -> PVDE_R {
109        PVDE_R::new(((self.bits >> 4) & 1) != 0)
110    }
111    ///Bits 5:7 - PVD level selection
112    #[inline(always)]
113    pub fn pls(&self) -> PLS_R {
114        PLS_R::new(((self.bits >> 5) & 7) as u8)
115    }
116    ///Bit 8 - Disable backup domain write protection
117    #[inline(always)]
118    pub fn dbp(&self) -> DBP_R {
119        DBP_R::new(((self.bits >> 8) & 1) != 0)
120    }
121}
122impl core::fmt::Debug for R {
123    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
124        f.debug_struct("CR")
125            .field("dbp", &self.dbp())
126            .field("pls", &self.pls())
127            .field("pvde", &self.pvde())
128            .field("csbf", &self.csbf())
129            .field("cwuf", &self.cwuf())
130            .field("pdds", &self.pdds())
131            .field("lpds", &self.lpds())
132            .finish()
133    }
134}
135impl W {
136    ///Bit 0 - Low-power deep sleep
137    #[inline(always)]
138    pub fn lpds(&mut self) -> LPDS_W<CRrs> {
139        LPDS_W::new(self, 0)
140    }
141    ///Bit 1 - Power down deepsleep
142    #[inline(always)]
143    pub fn pdds(&mut self) -> PDDS_W<CRrs> {
144        PDDS_W::new(self, 1)
145    }
146    ///Bit 2 - Clear wakeup flag
147    #[inline(always)]
148    pub fn cwuf(&mut self) -> CWUF_W<CRrs> {
149        CWUF_W::new(self, 2)
150    }
151    ///Bit 3 - Clear standby flag
152    #[inline(always)]
153    pub fn csbf(&mut self) -> CSBF_W<CRrs> {
154        CSBF_W::new(self, 3)
155    }
156    ///Bit 4 - Power voltage detector enable
157    #[inline(always)]
158    pub fn pvde(&mut self) -> PVDE_W<CRrs> {
159        PVDE_W::new(self, 4)
160    }
161    ///Bits 5:7 - PVD level selection
162    #[inline(always)]
163    pub fn pls(&mut self) -> PLS_W<CRrs> {
164        PLS_W::new(self, 5)
165    }
166    ///Bit 8 - Disable backup domain write protection
167    #[inline(always)]
168    pub fn dbp(&mut self) -> DBP_W<CRrs> {
169        DBP_W::new(self, 8)
170    }
171}
172/**power control register
173
174You can [`read`](crate::Reg::read) this register and get [`cr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
175
176See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F0x8.html#PWR:CR)*/
177pub struct CRrs;
178impl crate::RegisterSpec for CRrs {
179    type Ux = u32;
180}
181///`read()` method returns [`cr::R`](R) reader structure
182impl crate::Readable for CRrs {}
183///`write(|w| ..)` method takes [`cr::W`](W) writer structure
184impl crate::Writable for CRrs {
185    type Safety = crate::Unsafe;
186}
187///`reset()` method sets CR to value 0
188impl crate::Resettable for CRrs {}
stm32f0/stm32f0x8/pwr/cr.rs

stm32f0/stm32f0x8/pwr/
cr.rs
