stm32f0/stm32f0x2/
tim15.rs

1#[repr(C)]
2#[derive(Debug)]
3///Register block
4pub struct RegisterBlock {
5    cr1: CR1,
6    cr2: CR2,
7    smcr: SMCR,
8    dier: DIER,
9    sr: SR,
10    egr: EGR,
11    _reserved_6_ccmr1: [u8; 0x04],
12    _reserved7: [u8; 0x04],
13    ccer: CCER,
14    cnt: CNT,
15    psc: PSC,
16    arr: ARR,
17    rcr: RCR,
18    ccr: [CCR; 2],
19    _reserved13: [u8; 0x08],
20    bdtr: BDTR,
21    dcr: DCR,
22    dmar: DMAR,
23}
24impl RegisterBlock {
25    ///0x00 - control register 1
26    #[inline(always)]
27    pub const fn cr1(&self) -> &CR1 {
28        &self.cr1
29    }
30    ///0x04 - control register 2
31    #[inline(always)]
32    pub const fn cr2(&self) -> &CR2 {
33        &self.cr2
34    }
35    ///0x08 - slave mode control register
36    #[inline(always)]
37    pub const fn smcr(&self) -> &SMCR {
38        &self.smcr
39    }
40    ///0x0c - DMA/Interrupt enable register
41    #[inline(always)]
42    pub const fn dier(&self) -> &DIER {
43        &self.dier
44    }
45    ///0x10 - status register
46    #[inline(always)]
47    pub const fn sr(&self) -> &SR {
48        &self.sr
49    }
50    ///0x14 - event generation register
51    #[inline(always)]
52    pub const fn egr(&self) -> &EGR {
53        &self.egr
54    }
55    ///0x18 - capture/compare mode register 1 (input mode)
56    #[inline(always)]
57    pub const fn ccmr1_input(&self) -> &CCMR1_INPUT {
58        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
59    }
60    ///0x18 - capture/compare mode register (output mode)
61    #[inline(always)]
62    pub const fn ccmr1_output(&self) -> &CCMR1_OUTPUT {
63        unsafe { &*core::ptr::from_ref(self).cast::<u8>().add(24).cast() }
64    }
65    ///0x20 - capture/compare enable register
66    #[inline(always)]
67    pub const fn ccer(&self) -> &CCER {
68        &self.ccer
69    }
70    ///0x24 - counter
71    #[inline(always)]
72    pub const fn cnt(&self) -> &CNT {
73        &self.cnt
74    }
75    ///0x28 - prescaler
76    #[inline(always)]
77    pub const fn psc(&self) -> &PSC {
78        &self.psc
79    }
80    ///0x2c - auto-reload register
81    #[inline(always)]
82    pub const fn arr(&self) -> &ARR {
83        &self.arr
84    }
85    ///0x30 - repetition counter register
86    #[inline(always)]
87    pub const fn rcr(&self) -> &RCR {
88        &self.rcr
89    }
90    ///0x34..0x3c - capture/compare register
91    ///
92    ///<div class="warning">`n` is the index of register in the array. `n == 0` corresponds to `CCR1` register.</div>
93    #[inline(always)]
94    pub const fn ccr(&self, n: usize) -> &CCR {
95        &self.ccr[n]
96    }
97    ///Iterator for array of:
98    ///0x34..0x3c - capture/compare register
99    #[inline(always)]
100    pub fn ccr_iter(&self) -> impl Iterator<Item = &CCR> {
101        self.ccr.iter()
102    }
103    ///0x34 - capture/compare register
104    #[inline(always)]
105    pub const fn ccr1(&self) -> &CCR {
106        self.ccr(0)
107    }
108    ///0x38 - capture/compare register
109    #[inline(always)]
110    pub const fn ccr2(&self) -> &CCR {
111        self.ccr(1)
112    }
113    ///0x44 - break and dead-time register
114    #[inline(always)]
115    pub const fn bdtr(&self) -> &BDTR {
116        &self.bdtr
117    }
118    ///0x48 - DMA control register
119    #[inline(always)]
120    pub const fn dcr(&self) -> &DCR {
121        &self.dcr
122    }
123    ///0x4c - DMA address for full transfer
124    #[inline(always)]
125    pub const fn dmar(&self) -> &DMAR {
126        &self.dmar
127    }
128}
129/**CR1 (rw) register accessor: control register 1
130
131You can [`read`](crate::Reg::read) this register and get [`cr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
132
133See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F0x2.html#TIM15:CR1)
134
135For information about available fields see [`mod@cr1`] module*/
136pub type CR1 = crate::Reg<cr1::CR1rs>;
137///control register 1
138pub mod cr1;
139/**CR2 (rw) register accessor: control register 2
140
141You can [`read`](crate::Reg::read) this register and get [`cr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
142
143See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F0x2.html#TIM15:CR2)
144
145For information about available fields see [`mod@cr2`] module*/
146pub type CR2 = crate::Reg<cr2::CR2rs>;
147///control register 2
148pub mod cr2;
149/**SMCR (rw) register accessor: slave mode control register
150
151You can [`read`](crate::Reg::read) this register and get [`smcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
152
153See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F0x2.html#TIM15:SMCR)
154
155For information about available fields see [`mod@smcr`] module*/
156pub type SMCR = crate::Reg<smcr::SMCRrs>;
157///slave mode control register
158pub mod smcr;
159/**DIER (rw) register accessor: DMA/Interrupt enable register
160
161You can [`read`](crate::Reg::read) this register and get [`dier::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dier::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
162
163See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F0x2.html#TIM15:DIER)
164
165For information about available fields see [`mod@dier`] module*/
166pub type DIER = crate::Reg<dier::DIERrs>;
167///DMA/Interrupt enable register
168pub mod dier;
169/**SR (rw) register accessor: status register
170
171You can [`read`](crate::Reg::read) this register and get [`sr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
172
173See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F0x2.html#TIM15:SR)
174
175For information about available fields see [`mod@sr`] module*/
176pub type SR = crate::Reg<sr::SRrs>;
177///status register
178pub mod sr;
179/**EGR (w) register accessor: event generation register
180
181You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`egr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
182
183See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F0x2.html#TIM15:EGR)
184
185For information about available fields see [`mod@egr`] module*/
186pub type EGR = crate::Reg<egr::EGRrs>;
187///event generation register
188pub mod egr;
189/**CCMR1_Output (rw) register accessor: capture/compare mode register (output mode)
190
191You can [`read`](crate::Reg::read) this register and get [`ccmr1_output::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_output::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
192
193See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F0x2.html#TIM15:CCMR1_Output)
194
195For information about available fields see [`mod@ccmr1_output`] module*/
196#[doc(alias = "CCMR1_Output")]
197pub type CCMR1_OUTPUT = crate::Reg<ccmr1_output::CCMR1_OUTPUTrs>;
198///capture/compare mode register (output mode)
199pub mod ccmr1_output;
200/**CCMR1_Input (rw) register accessor: capture/compare mode register 1 (input mode)
201
202You can [`read`](crate::Reg::read) this register and get [`ccmr1_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccmr1_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
203
204See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F0x2.html#TIM15:CCMR1_Input)
205
206For information about available fields see [`mod@ccmr1_input`] module*/
207#[doc(alias = "CCMR1_Input")]
208pub type CCMR1_INPUT = crate::Reg<ccmr1_input::CCMR1_INPUTrs>;
209///capture/compare mode register 1 (input mode)
210pub mod ccmr1_input;
211/**CCER (rw) register accessor: capture/compare enable register
212
213You can [`read`](crate::Reg::read) this register and get [`ccer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
214
215See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F0x2.html#TIM15:CCER)
216
217For information about available fields see [`mod@ccer`] module*/
218pub type CCER = crate::Reg<ccer::CCERrs>;
219///capture/compare enable register
220pub mod ccer;
221/**CNT (rw) register accessor: counter
222
223You can [`read`](crate::Reg::read) this register and get [`cnt::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cnt::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
224
225See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F0x2.html#TIM15:CNT)
226
227For information about available fields see [`mod@cnt`] module*/
228pub type CNT = crate::Reg<cnt::CNTrs>;
229///counter
230pub mod cnt;
231/**PSC (rw) register accessor: prescaler
232
233You can [`read`](crate::Reg::read) this register and get [`psc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`psc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
234
235See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F0x2.html#TIM15:PSC)
236
237For information about available fields see [`mod@psc`] module*/
238pub type PSC = crate::Reg<psc::PSCrs>;
239///prescaler
240pub mod psc;
241/**ARR (rw) register accessor: auto-reload register
242
243You can [`read`](crate::Reg::read) this register and get [`arr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`arr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
244
245See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F0x2.html#TIM15:ARR)
246
247For information about available fields see [`mod@arr`] module*/
248pub type ARR = crate::Reg<arr::ARRrs>;
249///auto-reload register
250pub mod arr;
251/**RCR (rw) register accessor: repetition counter register
252
253You can [`read`](crate::Reg::read) this register and get [`rcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
254
255See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F0x2.html#TIM15:RCR)
256
257For information about available fields see [`mod@rcr`] module*/
258pub type RCR = crate::Reg<rcr::RCRrs>;
259///repetition counter register
260pub mod rcr;
261/**CCR (rw) register accessor: capture/compare register
262
263You can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
264
265See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F0x2.html#TIM15:CCR[1])
266
267For information about available fields see [`mod@ccr`] module*/
268pub type CCR = crate::Reg<ccr::CCRrs>;
269///capture/compare register
270pub mod ccr;
271/**BDTR (rw) register accessor: break and dead-time register
272
273You can [`read`](crate::Reg::read) this register and get [`bdtr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`bdtr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
274
275See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F0x2.html#TIM15:BDTR)
276
277For information about available fields see [`mod@bdtr`] module*/
278pub type BDTR = crate::Reg<bdtr::BDTRrs>;
279///break and dead-time register
280pub mod bdtr;
281/**DCR (rw) register accessor: DMA control register
282
283You can [`read`](crate::Reg::read) this register and get [`dcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
284
285See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F0x2.html#TIM15:DCR)
286
287For information about available fields see [`mod@dcr`] module*/
288pub type DCR = crate::Reg<dcr::DCRrs>;
289///DMA control register
290pub mod dcr;
291/**DMAR (rw) register accessor: DMA address for full transfer
292
293You can [`read`](crate::Reg::read) this register and get [`dmar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dmar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
294
295See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F0x2.html#TIM15:DMAR)
296
297For information about available fields see [`mod@dmar`] module*/
298pub type DMAR = crate::Reg<dmar::DMARrs>;
299///DMA address for full transfer
300pub mod dmar;
stm32f0/stm32f0x2/tim15.rs

stm32f0/stm32f0x2/
tim15.rs
