stm32f0/stm32f0x1/exti/
imr.rs

1///Register `IMR` reader
2pub type R = crate::R<IMRrs>;
3///Register `IMR` writer
4pub type W = crate::W<IMRrs>;
5/**Interrupt Mask on line 0
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum INTERRUPT_MASK {
11    ///0: Interrupt request line is masked
12    Masked = 0,
13    ///1: Interrupt request line is unmasked
14    Unmasked = 1,
15}
16impl From<INTERRUPT_MASK> for bool {
17    #[inline(always)]
18    fn from(variant: INTERRUPT_MASK) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `MR0` reader - Interrupt Mask on line 0
23pub type MR0_R = crate::BitReader<INTERRUPT_MASK>;
24impl MR0_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> INTERRUPT_MASK {
28        match self.bits {
29            false => INTERRUPT_MASK::Masked,
30            true => INTERRUPT_MASK::Unmasked,
31        }
32    }
33    ///Interrupt request line is masked
34    #[inline(always)]
35    pub fn is_masked(&self) -> bool {
36        *self == INTERRUPT_MASK::Masked
37    }
38    ///Interrupt request line is unmasked
39    #[inline(always)]
40    pub fn is_unmasked(&self) -> bool {
41        *self == INTERRUPT_MASK::Unmasked
42    }
43}
44///Field `MR0` writer - Interrupt Mask on line 0
45pub type MR0_W<'a, REG> = crate::BitWriter<'a, REG, INTERRUPT_MASK>;
46impl<'a, REG> MR0_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///Interrupt request line is masked
51    #[inline(always)]
52    pub fn masked(self) -> &'a mut crate::W<REG> {
53        self.variant(INTERRUPT_MASK::Masked)
54    }
55    ///Interrupt request line is unmasked
56    #[inline(always)]
57    pub fn unmasked(self) -> &'a mut crate::W<REG> {
58        self.variant(INTERRUPT_MASK::Unmasked)
59    }
60}
61///Field `MR1` reader - Interrupt Mask on line 1
62pub use MR0_R as MR1_R;
63///Field `MR2` reader - Interrupt Mask on line 2
64pub use MR0_R as MR2_R;
65///Field `MR3` reader - Interrupt Mask on line 3
66pub use MR0_R as MR3_R;
67///Field `MR4` reader - Interrupt Mask on line 4
68pub use MR0_R as MR4_R;
69///Field `MR5` reader - Interrupt Mask on line 5
70pub use MR0_R as MR5_R;
71///Field `MR6` reader - Interrupt Mask on line 6
72pub use MR0_R as MR6_R;
73///Field `MR7` reader - Interrupt Mask on line 7
74pub use MR0_R as MR7_R;
75///Field `MR8` reader - Interrupt Mask on line 8
76pub use MR0_R as MR8_R;
77///Field `MR9` reader - Interrupt Mask on line 9
78pub use MR0_R as MR9_R;
79///Field `MR10` reader - Interrupt Mask on line 10
80pub use MR0_R as MR10_R;
81///Field `MR11` reader - Interrupt Mask on line 11
82pub use MR0_R as MR11_R;
83///Field `MR12` reader - Interrupt Mask on line 12
84pub use MR0_R as MR12_R;
85///Field `MR13` reader - Interrupt Mask on line 13
86pub use MR0_R as MR13_R;
87///Field `MR14` reader - Interrupt Mask on line 14
88pub use MR0_R as MR14_R;
89///Field `MR15` reader - Interrupt Mask on line 15
90pub use MR0_R as MR15_R;
91///Field `MR16` reader - Interrupt Mask on line 16
92pub use MR0_R as MR16_R;
93///Field `MR17` reader - Interrupt Mask on line 17
94pub use MR0_R as MR17_R;
95///Field `MR18` reader - Interrupt Mask on line 18
96pub use MR0_R as MR18_R;
97///Field `MR19` reader - Interrupt Mask on line 19
98pub use MR0_R as MR19_R;
99///Field `MR20` reader - Interrupt Mask on line 20
100pub use MR0_R as MR20_R;
101///Field `MR21` reader - Interrupt Mask on line 21
102pub use MR0_R as MR21_R;
103///Field `MR22` reader - Interrupt Mask on line 22
104pub use MR0_R as MR22_R;
105///Field `MR23` reader - Interrupt Mask on line 23
106pub use MR0_R as MR23_R;
107///Field `MR24` reader - Interrupt Mask on line 24
108pub use MR0_R as MR24_R;
109///Field `MR25` reader - Interrupt Mask on line 25
110pub use MR0_R as MR25_R;
111///Field `MR26` reader - Interrupt Mask on line 26
112pub use MR0_R as MR26_R;
113///Field `MR27` reader - Interrupt Mask on line 27
114pub use MR0_R as MR27_R;
115///Field `MR1` writer - Interrupt Mask on line 1
116pub use MR0_W as MR1_W;
117///Field `MR2` writer - Interrupt Mask on line 2
118pub use MR0_W as MR2_W;
119///Field `MR3` writer - Interrupt Mask on line 3
120pub use MR0_W as MR3_W;
121///Field `MR4` writer - Interrupt Mask on line 4
122pub use MR0_W as MR4_W;
123///Field `MR5` writer - Interrupt Mask on line 5
124pub use MR0_W as MR5_W;
125///Field `MR6` writer - Interrupt Mask on line 6
126pub use MR0_W as MR6_W;
127///Field `MR7` writer - Interrupt Mask on line 7
128pub use MR0_W as MR7_W;
129///Field `MR8` writer - Interrupt Mask on line 8
130pub use MR0_W as MR8_W;
131///Field `MR9` writer - Interrupt Mask on line 9
132pub use MR0_W as MR9_W;
133///Field `MR10` writer - Interrupt Mask on line 10
134pub use MR0_W as MR10_W;
135///Field `MR11` writer - Interrupt Mask on line 11
136pub use MR0_W as MR11_W;
137///Field `MR12` writer - Interrupt Mask on line 12
138pub use MR0_W as MR12_W;
139///Field `MR13` writer - Interrupt Mask on line 13
140pub use MR0_W as MR13_W;
141///Field `MR14` writer - Interrupt Mask on line 14
142pub use MR0_W as MR14_W;
143///Field `MR15` writer - Interrupt Mask on line 15
144pub use MR0_W as MR15_W;
145///Field `MR16` writer - Interrupt Mask on line 16
146pub use MR0_W as MR16_W;
147///Field `MR17` writer - Interrupt Mask on line 17
148pub use MR0_W as MR17_W;
149///Field `MR18` writer - Interrupt Mask on line 18
150pub use MR0_W as MR18_W;
151///Field `MR19` writer - Interrupt Mask on line 19
152pub use MR0_W as MR19_W;
153///Field `MR20` writer - Interrupt Mask on line 20
154pub use MR0_W as MR20_W;
155///Field `MR21` writer - Interrupt Mask on line 21
156pub use MR0_W as MR21_W;
157///Field `MR22` writer - Interrupt Mask on line 22
158pub use MR0_W as MR22_W;
159///Field `MR23` writer - Interrupt Mask on line 23
160pub use MR0_W as MR23_W;
161///Field `MR24` writer - Interrupt Mask on line 24
162pub use MR0_W as MR24_W;
163///Field `MR25` writer - Interrupt Mask on line 25
164pub use MR0_W as MR25_W;
165///Field `MR26` writer - Interrupt Mask on line 26
166pub use MR0_W as MR26_W;
167///Field `MR27` writer - Interrupt Mask on line 27
168pub use MR0_W as MR27_W;
169impl R {
170    ///Bit 0 - Interrupt Mask on line 0
171    #[inline(always)]
172    pub fn mr0(&self) -> MR0_R {
173        MR0_R::new((self.bits & 1) != 0)
174    }
175    ///Bit 1 - Interrupt Mask on line 1
176    #[inline(always)]
177    pub fn mr1(&self) -> MR1_R {
178        MR1_R::new(((self.bits >> 1) & 1) != 0)
179    }
180    ///Bit 2 - Interrupt Mask on line 2
181    #[inline(always)]
182    pub fn mr2(&self) -> MR2_R {
183        MR2_R::new(((self.bits >> 2) & 1) != 0)
184    }
185    ///Bit 3 - Interrupt Mask on line 3
186    #[inline(always)]
187    pub fn mr3(&self) -> MR3_R {
188        MR3_R::new(((self.bits >> 3) & 1) != 0)
189    }
190    ///Bit 4 - Interrupt Mask on line 4
191    #[inline(always)]
192    pub fn mr4(&self) -> MR4_R {
193        MR4_R::new(((self.bits >> 4) & 1) != 0)
194    }
195    ///Bit 5 - Interrupt Mask on line 5
196    #[inline(always)]
197    pub fn mr5(&self) -> MR5_R {
198        MR5_R::new(((self.bits >> 5) & 1) != 0)
199    }
200    ///Bit 6 - Interrupt Mask on line 6
201    #[inline(always)]
202    pub fn mr6(&self) -> MR6_R {
203        MR6_R::new(((self.bits >> 6) & 1) != 0)
204    }
205    ///Bit 7 - Interrupt Mask on line 7
206    #[inline(always)]
207    pub fn mr7(&self) -> MR7_R {
208        MR7_R::new(((self.bits >> 7) & 1) != 0)
209    }
210    ///Bit 8 - Interrupt Mask on line 8
211    #[inline(always)]
212    pub fn mr8(&self) -> MR8_R {
213        MR8_R::new(((self.bits >> 8) & 1) != 0)
214    }
215    ///Bit 9 - Interrupt Mask on line 9
216    #[inline(always)]
217    pub fn mr9(&self) -> MR9_R {
218        MR9_R::new(((self.bits >> 9) & 1) != 0)
219    }
220    ///Bit 10 - Interrupt Mask on line 10
221    #[inline(always)]
222    pub fn mr10(&self) -> MR10_R {
223        MR10_R::new(((self.bits >> 10) & 1) != 0)
224    }
225    ///Bit 11 - Interrupt Mask on line 11
226    #[inline(always)]
227    pub fn mr11(&self) -> MR11_R {
228        MR11_R::new(((self.bits >> 11) & 1) != 0)
229    }
230    ///Bit 12 - Interrupt Mask on line 12
231    #[inline(always)]
232    pub fn mr12(&self) -> MR12_R {
233        MR12_R::new(((self.bits >> 12) & 1) != 0)
234    }
235    ///Bit 13 - Interrupt Mask on line 13
236    #[inline(always)]
237    pub fn mr13(&self) -> MR13_R {
238        MR13_R::new(((self.bits >> 13) & 1) != 0)
239    }
240    ///Bit 14 - Interrupt Mask on line 14
241    #[inline(always)]
242    pub fn mr14(&self) -> MR14_R {
243        MR14_R::new(((self.bits >> 14) & 1) != 0)
244    }
245    ///Bit 15 - Interrupt Mask on line 15
246    #[inline(always)]
247    pub fn mr15(&self) -> MR15_R {
248        MR15_R::new(((self.bits >> 15) & 1) != 0)
249    }
250    ///Bit 16 - Interrupt Mask on line 16
251    #[inline(always)]
252    pub fn mr16(&self) -> MR16_R {
253        MR16_R::new(((self.bits >> 16) & 1) != 0)
254    }
255    ///Bit 17 - Interrupt Mask on line 17
256    #[inline(always)]
257    pub fn mr17(&self) -> MR17_R {
258        MR17_R::new(((self.bits >> 17) & 1) != 0)
259    }
260    ///Bit 18 - Interrupt Mask on line 18
261    #[inline(always)]
262    pub fn mr18(&self) -> MR18_R {
263        MR18_R::new(((self.bits >> 18) & 1) != 0)
264    }
265    ///Bit 19 - Interrupt Mask on line 19
266    #[inline(always)]
267    pub fn mr19(&self) -> MR19_R {
268        MR19_R::new(((self.bits >> 19) & 1) != 0)
269    }
270    ///Bit 20 - Interrupt Mask on line 20
271    #[inline(always)]
272    pub fn mr20(&self) -> MR20_R {
273        MR20_R::new(((self.bits >> 20) & 1) != 0)
274    }
275    ///Bit 21 - Interrupt Mask on line 21
276    #[inline(always)]
277    pub fn mr21(&self) -> MR21_R {
278        MR21_R::new(((self.bits >> 21) & 1) != 0)
279    }
280    ///Bit 22 - Interrupt Mask on line 22
281    #[inline(always)]
282    pub fn mr22(&self) -> MR22_R {
283        MR22_R::new(((self.bits >> 22) & 1) != 0)
284    }
285    ///Bit 23 - Interrupt Mask on line 23
286    #[inline(always)]
287    pub fn mr23(&self) -> MR23_R {
288        MR23_R::new(((self.bits >> 23) & 1) != 0)
289    }
290    ///Bit 24 - Interrupt Mask on line 24
291    #[inline(always)]
292    pub fn mr24(&self) -> MR24_R {
293        MR24_R::new(((self.bits >> 24) & 1) != 0)
294    }
295    ///Bit 25 - Interrupt Mask on line 25
296    #[inline(always)]
297    pub fn mr25(&self) -> MR25_R {
298        MR25_R::new(((self.bits >> 25) & 1) != 0)
299    }
300    ///Bit 26 - Interrupt Mask on line 26
301    #[inline(always)]
302    pub fn mr26(&self) -> MR26_R {
303        MR26_R::new(((self.bits >> 26) & 1) != 0)
304    }
305    ///Bit 27 - Interrupt Mask on line 27
306    #[inline(always)]
307    pub fn mr27(&self) -> MR27_R {
308        MR27_R::new(((self.bits >> 27) & 1) != 0)
309    }
310}
311impl core::fmt::Debug for R {
312    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
313        f.debug_struct("IMR")
314            .field("mr0", &self.mr0())
315            .field("mr1", &self.mr1())
316            .field("mr2", &self.mr2())
317            .field("mr3", &self.mr3())
318            .field("mr4", &self.mr4())
319            .field("mr5", &self.mr5())
320            .field("mr6", &self.mr6())
321            .field("mr7", &self.mr7())
322            .field("mr8", &self.mr8())
323            .field("mr9", &self.mr9())
324            .field("mr10", &self.mr10())
325            .field("mr11", &self.mr11())
326            .field("mr12", &self.mr12())
327            .field("mr13", &self.mr13())
328            .field("mr14", &self.mr14())
329            .field("mr15", &self.mr15())
330            .field("mr16", &self.mr16())
331            .field("mr17", &self.mr17())
332            .field("mr18", &self.mr18())
333            .field("mr19", &self.mr19())
334            .field("mr20", &self.mr20())
335            .field("mr21", &self.mr21())
336            .field("mr22", &self.mr22())
337            .field("mr23", &self.mr23())
338            .field("mr24", &self.mr24())
339            .field("mr25", &self.mr25())
340            .field("mr26", &self.mr26())
341            .field("mr27", &self.mr27())
342            .finish()
343    }
344}
345impl W {
346    ///Bit 0 - Interrupt Mask on line 0
347    #[inline(always)]
348    pub fn mr0(&mut self) -> MR0_W<IMRrs> {
349        MR0_W::new(self, 0)
350    }
351    ///Bit 1 - Interrupt Mask on line 1
352    #[inline(always)]
353    pub fn mr1(&mut self) -> MR1_W<IMRrs> {
354        MR1_W::new(self, 1)
355    }
356    ///Bit 2 - Interrupt Mask on line 2
357    #[inline(always)]
358    pub fn mr2(&mut self) -> MR2_W<IMRrs> {
359        MR2_W::new(self, 2)
360    }
361    ///Bit 3 - Interrupt Mask on line 3
362    #[inline(always)]
363    pub fn mr3(&mut self) -> MR3_W<IMRrs> {
364        MR3_W::new(self, 3)
365    }
366    ///Bit 4 - Interrupt Mask on line 4
367    #[inline(always)]
368    pub fn mr4(&mut self) -> MR4_W<IMRrs> {
369        MR4_W::new(self, 4)
370    }
371    ///Bit 5 - Interrupt Mask on line 5
372    #[inline(always)]
373    pub fn mr5(&mut self) -> MR5_W<IMRrs> {
374        MR5_W::new(self, 5)
375    }
376    ///Bit 6 - Interrupt Mask on line 6
377    #[inline(always)]
378    pub fn mr6(&mut self) -> MR6_W<IMRrs> {
379        MR6_W::new(self, 6)
380    }
381    ///Bit 7 - Interrupt Mask on line 7
382    #[inline(always)]
383    pub fn mr7(&mut self) -> MR7_W<IMRrs> {
384        MR7_W::new(self, 7)
385    }
386    ///Bit 8 - Interrupt Mask on line 8
387    #[inline(always)]
388    pub fn mr8(&mut self) -> MR8_W<IMRrs> {
389        MR8_W::new(self, 8)
390    }
391    ///Bit 9 - Interrupt Mask on line 9
392    #[inline(always)]
393    pub fn mr9(&mut self) -> MR9_W<IMRrs> {
394        MR9_W::new(self, 9)
395    }
396    ///Bit 10 - Interrupt Mask on line 10
397    #[inline(always)]
398    pub fn mr10(&mut self) -> MR10_W<IMRrs> {
399        MR10_W::new(self, 10)
400    }
401    ///Bit 11 - Interrupt Mask on line 11
402    #[inline(always)]
403    pub fn mr11(&mut self) -> MR11_W<IMRrs> {
404        MR11_W::new(self, 11)
405    }
406    ///Bit 12 - Interrupt Mask on line 12
407    #[inline(always)]
408    pub fn mr12(&mut self) -> MR12_W<IMRrs> {
409        MR12_W::new(self, 12)
410    }
411    ///Bit 13 - Interrupt Mask on line 13
412    #[inline(always)]
413    pub fn mr13(&mut self) -> MR13_W<IMRrs> {
414        MR13_W::new(self, 13)
415    }
416    ///Bit 14 - Interrupt Mask on line 14
417    #[inline(always)]
418    pub fn mr14(&mut self) -> MR14_W<IMRrs> {
419        MR14_W::new(self, 14)
420    }
421    ///Bit 15 - Interrupt Mask on line 15
422    #[inline(always)]
423    pub fn mr15(&mut self) -> MR15_W<IMRrs> {
424        MR15_W::new(self, 15)
425    }
426    ///Bit 16 - Interrupt Mask on line 16
427    #[inline(always)]
428    pub fn mr16(&mut self) -> MR16_W<IMRrs> {
429        MR16_W::new(self, 16)
430    }
431    ///Bit 17 - Interrupt Mask on line 17
432    #[inline(always)]
433    pub fn mr17(&mut self) -> MR17_W<IMRrs> {
434        MR17_W::new(self, 17)
435    }
436    ///Bit 18 - Interrupt Mask on line 18
437    #[inline(always)]
438    pub fn mr18(&mut self) -> MR18_W<IMRrs> {
439        MR18_W::new(self, 18)
440    }
441    ///Bit 19 - Interrupt Mask on line 19
442    #[inline(always)]
443    pub fn mr19(&mut self) -> MR19_W<IMRrs> {
444        MR19_W::new(self, 19)
445    }
446    ///Bit 20 - Interrupt Mask on line 20
447    #[inline(always)]
448    pub fn mr20(&mut self) -> MR20_W<IMRrs> {
449        MR20_W::new(self, 20)
450    }
451    ///Bit 21 - Interrupt Mask on line 21
452    #[inline(always)]
453    pub fn mr21(&mut self) -> MR21_W<IMRrs> {
454        MR21_W::new(self, 21)
455    }
456    ///Bit 22 - Interrupt Mask on line 22
457    #[inline(always)]
458    pub fn mr22(&mut self) -> MR22_W<IMRrs> {
459        MR22_W::new(self, 22)
460    }
461    ///Bit 23 - Interrupt Mask on line 23
462    #[inline(always)]
463    pub fn mr23(&mut self) -> MR23_W<IMRrs> {
464        MR23_W::new(self, 23)
465    }
466    ///Bit 24 - Interrupt Mask on line 24
467    #[inline(always)]
468    pub fn mr24(&mut self) -> MR24_W<IMRrs> {
469        MR24_W::new(self, 24)
470    }
471    ///Bit 25 - Interrupt Mask on line 25
472    #[inline(always)]
473    pub fn mr25(&mut self) -> MR25_W<IMRrs> {
474        MR25_W::new(self, 25)
475    }
476    ///Bit 26 - Interrupt Mask on line 26
477    #[inline(always)]
478    pub fn mr26(&mut self) -> MR26_W<IMRrs> {
479        MR26_W::new(self, 26)
480    }
481    ///Bit 27 - Interrupt Mask on line 27
482    #[inline(always)]
483    pub fn mr27(&mut self) -> MR27_W<IMRrs> {
484        MR27_W::new(self, 27)
485    }
486}
487/**Interrupt mask register (EXTI_IMR)
488
489You can [`read`](crate::Reg::read) this register and get [`imr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`imr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
490
491See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F0x1.html#EXTI:IMR)*/
492pub struct IMRrs;
493impl crate::RegisterSpec for IMRrs {
494    type Ux = u32;
495}
496///`read()` method returns [`imr::R`](R) reader structure
497impl crate::Readable for IMRrs {}
498///`write(|w| ..)` method takes [`imr::W`](W) writer structure
499impl crate::Writable for IMRrs {
500    type Safety = crate::Unsafe;
501}
502///`reset()` method sets IMR to value 0x0f94_0000
503impl crate::Resettable for IMRrs {
504    const RESET_VALUE: u32 = 0x0f94_0000;
505}
stm32f0/stm32f0x1/exti/imr.rs

stm32f0/stm32f0x1/exti/
imr.rs
