stm32f0/stm32f0x0/rcc/
apb1enr.rs

1///Register `APB1ENR` reader
2pub type R = crate::R<APB1ENRrs>;
3///Register `APB1ENR` writer
4pub type W = crate::W<APB1ENRrs>;
5/**Timer 3 clock enable
6
7Value on reset: 0*/
8#[cfg_attr(feature = "defmt", derive(defmt::Format))]
9#[derive(Clone, Copy, Debug, PartialEq, Eq)]
10pub enum TIM3EN {
11    ///0: The selected clock is disabled
12    Disabled = 0,
13    ///1: The selected clock is enabled
14    Enabled = 1,
15}
16impl From<TIM3EN> for bool {
17    #[inline(always)]
18    fn from(variant: TIM3EN) -> Self {
19        variant as u8 != 0
20    }
21}
22///Field `TIM3EN` reader - Timer 3 clock enable
23pub type TIM3EN_R = crate::BitReader<TIM3EN>;
24impl TIM3EN_R {
25    ///Get enumerated values variant
26    #[inline(always)]
27    pub const fn variant(&self) -> TIM3EN {
28        match self.bits {
29            false => TIM3EN::Disabled,
30            true => TIM3EN::Enabled,
31        }
32    }
33    ///The selected clock is disabled
34    #[inline(always)]
35    pub fn is_disabled(&self) -> bool {
36        *self == TIM3EN::Disabled
37    }
38    ///The selected clock is enabled
39    #[inline(always)]
40    pub fn is_enabled(&self) -> bool {
41        *self == TIM3EN::Enabled
42    }
43}
44///Field `TIM3EN` writer - Timer 3 clock enable
45pub type TIM3EN_W<'a, REG> = crate::BitWriter<'a, REG, TIM3EN>;
46impl<'a, REG> TIM3EN_W<'a, REG>
47where
48    REG: crate::Writable + crate::RegisterSpec,
49{
50    ///The selected clock is disabled
51    #[inline(always)]
52    pub fn disabled(self) -> &'a mut crate::W<REG> {
53        self.variant(TIM3EN::Disabled)
54    }
55    ///The selected clock is enabled
56    #[inline(always)]
57    pub fn enabled(self) -> &'a mut crate::W<REG> {
58        self.variant(TIM3EN::Enabled)
59    }
60}
61///Field `TIM6EN` reader - Timer 6 clock enable
62pub use TIM3EN_R as TIM6EN_R;
63///Field `TIM7EN` reader - TIM7 timer clock enable
64pub use TIM3EN_R as TIM7EN_R;
65///Field `TIM14EN` reader - Timer 14 clock enable
66pub use TIM3EN_R as TIM14EN_R;
67///Field `WWDGEN` reader - Window watchdog clock enable
68pub use TIM3EN_R as WWDGEN_R;
69///Field `SPI2EN` reader - SPI 2 clock enable
70pub use TIM3EN_R as SPI2EN_R;
71///Field `USART2EN` reader - USART 2 clock enable
72pub use TIM3EN_R as USART2EN_R;
73///Field `USART3EN` reader - USART3 clock enable
74pub use TIM3EN_R as USART3EN_R;
75///Field `USART4EN` reader - USART4 clock enable
76pub use TIM3EN_R as USART4EN_R;
77///Field `USART5EN` reader - USART5 clock enable
78pub use TIM3EN_R as USART5EN_R;
79///Field `I2C1EN` reader - I2C 1 clock enable
80pub use TIM3EN_R as I2C1EN_R;
81///Field `I2C2EN` reader - I2C 2 clock enable
82pub use TIM3EN_R as I2C2EN_R;
83///Field `USBEN` reader - USB interface clock enable
84pub use TIM3EN_R as USBEN_R;
85///Field `PWREN` reader - Power interface clock enable
86pub use TIM3EN_R as PWREN_R;
87///Field `TIM6EN` writer - Timer 6 clock enable
88pub use TIM3EN_W as TIM6EN_W;
89///Field `TIM7EN` writer - TIM7 timer clock enable
90pub use TIM3EN_W as TIM7EN_W;
91///Field `TIM14EN` writer - Timer 14 clock enable
92pub use TIM3EN_W as TIM14EN_W;
93///Field `WWDGEN` writer - Window watchdog clock enable
94pub use TIM3EN_W as WWDGEN_W;
95///Field `SPI2EN` writer - SPI 2 clock enable
96pub use TIM3EN_W as SPI2EN_W;
97///Field `USART2EN` writer - USART 2 clock enable
98pub use TIM3EN_W as USART2EN_W;
99///Field `USART3EN` writer - USART3 clock enable
100pub use TIM3EN_W as USART3EN_W;
101///Field `USART4EN` writer - USART4 clock enable
102pub use TIM3EN_W as USART4EN_W;
103///Field `USART5EN` writer - USART5 clock enable
104pub use TIM3EN_W as USART5EN_W;
105///Field `I2C1EN` writer - I2C 1 clock enable
106pub use TIM3EN_W as I2C1EN_W;
107///Field `I2C2EN` writer - I2C 2 clock enable
108pub use TIM3EN_W as I2C2EN_W;
109///Field `USBEN` writer - USB interface clock enable
110pub use TIM3EN_W as USBEN_W;
111///Field `PWREN` writer - Power interface clock enable
112pub use TIM3EN_W as PWREN_W;
113impl R {
114    ///Bit 1 - Timer 3 clock enable
115    #[inline(always)]
116    pub fn tim3en(&self) -> TIM3EN_R {
117        TIM3EN_R::new(((self.bits >> 1) & 1) != 0)
118    }
119    ///Bit 4 - Timer 6 clock enable
120    #[inline(always)]
121    pub fn tim6en(&self) -> TIM6EN_R {
122        TIM6EN_R::new(((self.bits >> 4) & 1) != 0)
123    }
124    ///Bit 5 - TIM7 timer clock enable
125    #[inline(always)]
126    pub fn tim7en(&self) -> TIM7EN_R {
127        TIM7EN_R::new(((self.bits >> 5) & 1) != 0)
128    }
129    ///Bit 8 - Timer 14 clock enable
130    #[inline(always)]
131    pub fn tim14en(&self) -> TIM14EN_R {
132        TIM14EN_R::new(((self.bits >> 8) & 1) != 0)
133    }
134    ///Bit 11 - Window watchdog clock enable
135    #[inline(always)]
136    pub fn wwdgen(&self) -> WWDGEN_R {
137        WWDGEN_R::new(((self.bits >> 11) & 1) != 0)
138    }
139    ///Bit 14 - SPI 2 clock enable
140    #[inline(always)]
141    pub fn spi2en(&self) -> SPI2EN_R {
142        SPI2EN_R::new(((self.bits >> 14) & 1) != 0)
143    }
144    ///Bit 17 - USART 2 clock enable
145    #[inline(always)]
146    pub fn usart2en(&self) -> USART2EN_R {
147        USART2EN_R::new(((self.bits >> 17) & 1) != 0)
148    }
149    ///Bit 18 - USART3 clock enable
150    #[inline(always)]
151    pub fn usart3en(&self) -> USART3EN_R {
152        USART3EN_R::new(((self.bits >> 18) & 1) != 0)
153    }
154    ///Bit 19 - USART4 clock enable
155    #[inline(always)]
156    pub fn usart4en(&self) -> USART4EN_R {
157        USART4EN_R::new(((self.bits >> 19) & 1) != 0)
158    }
159    ///Bit 20 - USART5 clock enable
160    #[inline(always)]
161    pub fn usart5en(&self) -> USART5EN_R {
162        USART5EN_R::new(((self.bits >> 20) & 1) != 0)
163    }
164    ///Bit 21 - I2C 1 clock enable
165    #[inline(always)]
166    pub fn i2c1en(&self) -> I2C1EN_R {
167        I2C1EN_R::new(((self.bits >> 21) & 1) != 0)
168    }
169    ///Bit 22 - I2C 2 clock enable
170    #[inline(always)]
171    pub fn i2c2en(&self) -> I2C2EN_R {
172        I2C2EN_R::new(((self.bits >> 22) & 1) != 0)
173    }
174    ///Bit 23 - USB interface clock enable
175    #[inline(always)]
176    pub fn usben(&self) -> USBEN_R {
177        USBEN_R::new(((self.bits >> 23) & 1) != 0)
178    }
179    ///Bit 28 - Power interface clock enable
180    #[inline(always)]
181    pub fn pwren(&self) -> PWREN_R {
182        PWREN_R::new(((self.bits >> 28) & 1) != 0)
183    }
184}
185impl core::fmt::Debug for R {
186    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
187        f.debug_struct("APB1ENR")
188            .field("tim3en", &self.tim3en())
189            .field("tim6en", &self.tim6en())
190            .field("tim7en", &self.tim7en())
191            .field("tim14en", &self.tim14en())
192            .field("wwdgen", &self.wwdgen())
193            .field("spi2en", &self.spi2en())
194            .field("usart2en", &self.usart2en())
195            .field("usart3en", &self.usart3en())
196            .field("usart4en", &self.usart4en())
197            .field("usart5en", &self.usart5en())
198            .field("i2c1en", &self.i2c1en())
199            .field("i2c2en", &self.i2c2en())
200            .field("usben", &self.usben())
201            .field("pwren", &self.pwren())
202            .finish()
203    }
204}
205impl W {
206    ///Bit 1 - Timer 3 clock enable
207    #[inline(always)]
208    pub fn tim3en(&mut self) -> TIM3EN_W<APB1ENRrs> {
209        TIM3EN_W::new(self, 1)
210    }
211    ///Bit 4 - Timer 6 clock enable
212    #[inline(always)]
213    pub fn tim6en(&mut self) -> TIM6EN_W<APB1ENRrs> {
214        TIM6EN_W::new(self, 4)
215    }
216    ///Bit 5 - TIM7 timer clock enable
217    #[inline(always)]
218    pub fn tim7en(&mut self) -> TIM7EN_W<APB1ENRrs> {
219        TIM7EN_W::new(self, 5)
220    }
221    ///Bit 8 - Timer 14 clock enable
222    #[inline(always)]
223    pub fn tim14en(&mut self) -> TIM14EN_W<APB1ENRrs> {
224        TIM14EN_W::new(self, 8)
225    }
226    ///Bit 11 - Window watchdog clock enable
227    #[inline(always)]
228    pub fn wwdgen(&mut self) -> WWDGEN_W<APB1ENRrs> {
229        WWDGEN_W::new(self, 11)
230    }
231    ///Bit 14 - SPI 2 clock enable
232    #[inline(always)]
233    pub fn spi2en(&mut self) -> SPI2EN_W<APB1ENRrs> {
234        SPI2EN_W::new(self, 14)
235    }
236    ///Bit 17 - USART 2 clock enable
237    #[inline(always)]
238    pub fn usart2en(&mut self) -> USART2EN_W<APB1ENRrs> {
239        USART2EN_W::new(self, 17)
240    }
241    ///Bit 18 - USART3 clock enable
242    #[inline(always)]
243    pub fn usart3en(&mut self) -> USART3EN_W<APB1ENRrs> {
244        USART3EN_W::new(self, 18)
245    }
246    ///Bit 19 - USART4 clock enable
247    #[inline(always)]
248    pub fn usart4en(&mut self) -> USART4EN_W<APB1ENRrs> {
249        USART4EN_W::new(self, 19)
250    }
251    ///Bit 20 - USART5 clock enable
252    #[inline(always)]
253    pub fn usart5en(&mut self) -> USART5EN_W<APB1ENRrs> {
254        USART5EN_W::new(self, 20)
255    }
256    ///Bit 21 - I2C 1 clock enable
257    #[inline(always)]
258    pub fn i2c1en(&mut self) -> I2C1EN_W<APB1ENRrs> {
259        I2C1EN_W::new(self, 21)
260    }
261    ///Bit 22 - I2C 2 clock enable
262    #[inline(always)]
263    pub fn i2c2en(&mut self) -> I2C2EN_W<APB1ENRrs> {
264        I2C2EN_W::new(self, 22)
265    }
266    ///Bit 23 - USB interface clock enable
267    #[inline(always)]
268    pub fn usben(&mut self) -> USBEN_W<APB1ENRrs> {
269        USBEN_W::new(self, 23)
270    }
271    ///Bit 28 - Power interface clock enable
272    #[inline(always)]
273    pub fn pwren(&mut self) -> PWREN_W<APB1ENRrs> {
274        PWREN_W::new(self, 28)
275    }
276}
277/**APB1 peripheral clock enable register (RCC_APB1ENR)
278
279You can [`read`](crate::Reg::read) this register and get [`apb1enr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`apb1enr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).
280
281See register [structure](https://stm32-rs.github.io/stm32-rs/STM32F0x0.html#RCC:APB1ENR)*/
282pub struct APB1ENRrs;
283impl crate::RegisterSpec for APB1ENRrs {
284    type Ux = u32;
285}
286///`read()` method returns [`apb1enr::R`](R) reader structure
287impl crate::Readable for APB1ENRrs {}
288///`write(|w| ..)` method takes [`apb1enr::W`](W) writer structure
289impl crate::Writable for APB1ENRrs {
290    type Safety = crate::Unsafe;
291}
292///`reset()` method sets APB1ENR to value 0
293impl crate::Resettable for APB1ENRrs {}
stm32f0/stm32f0x0/rcc/apb1enr.rs

stm32f0/stm32f0x0/rcc/
apb1enr.rs
