1#[doc = "Register `CCMR1_Output` reader"]
2pub struct R(crate::R<CCMR1_OUTPUT_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CCMR1_OUTPUT_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CCMR1_OUTPUT_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CCMR1_OUTPUT_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `CCMR1_Output` writer"]
17pub struct W(crate::W<CCMR1_OUTPUT_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CCMR1_OUTPUT_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CCMR1_OUTPUT_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CCMR1_OUTPUT_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `OC2CE` reader - Output compare 2 clear enable"]
38pub type OC2CE_R = crate::BitReader<bool>;
39#[doc = "Field `OC2CE` writer - Output compare 2 clear enable"]
40pub type OC2CE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
41#[doc = "Output compare 2 mode"]
42pub use OC1M_A as OC2M_A;
43#[doc = "Field `OC2M` reader - Output compare 2 mode"]
44pub use OC1M_R as OC2M_R;
45#[doc = "Field `OC2M` writer - Output compare 2 mode"]
46pub use OC1M_W as OC2M_W;
47#[doc = "Output compare 2 preload enable\n\nValue on reset: 0"]
48#[derive(Clone, Copy, Debug, PartialEq)]
49pub enum OC2PE_A {
50 #[doc = "0: Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately"]
51 Disabled = 0,
52 #[doc = "1: Preload register on CCR2 enabled. Preload value is loaded into active register on each update event"]
53 Enabled = 1,
54}
55impl From<OC2PE_A> for bool {
56 #[inline(always)]
57 fn from(variant: OC2PE_A) -> Self {
58 variant as u8 != 0
59 }
60}
61#[doc = "Field `OC2PE` reader - Output compare 2 preload enable"]
62pub type OC2PE_R = crate::BitReader<OC2PE_A>;
63impl OC2PE_R {
64 #[doc = "Get enumerated values variant"]
65 #[inline(always)]
66 pub fn variant(&self) -> OC2PE_A {
67 match self.bits {
68 false => OC2PE_A::Disabled,
69 true => OC2PE_A::Enabled,
70 }
71 }
72 #[doc = "Checks if the value of the field is `Disabled`"]
73 #[inline(always)]
74 pub fn is_disabled(&self) -> bool {
75 *self == OC2PE_A::Disabled
76 }
77 #[doc = "Checks if the value of the field is `Enabled`"]
78 #[inline(always)]
79 pub fn is_enabled(&self) -> bool {
80 *self == OC2PE_A::Enabled
81 }
82}
83#[doc = "Field `OC2PE` writer - Output compare 2 preload enable"]
84pub type OC2PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, OC2PE_A, O>;
85impl<'a, const O: u8> OC2PE_W<'a, O> {
86 #[doc = "Preload register on CCR2 disabled. New values written to CCR2 are taken into account immediately"]
87 #[inline(always)]
88 pub fn disabled(self) -> &'a mut W {
89 self.variant(OC2PE_A::Disabled)
90 }
91 #[doc = "Preload register on CCR2 enabled. Preload value is loaded into active register on each update event"]
92 #[inline(always)]
93 pub fn enabled(self) -> &'a mut W {
94 self.variant(OC2PE_A::Enabled)
95 }
96}
97#[doc = "Field `OC2FE` reader - Output compare 2 fast enable"]
98pub type OC2FE_R = crate::BitReader<bool>;
99#[doc = "Field `OC2FE` writer - Output compare 2 fast enable"]
100pub type OC2FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
101#[doc = "Capture/Compare 2 selection\n\nValue on reset: 0"]
102#[derive(Clone, Copy, Debug, PartialEq)]
103#[repr(u8)]
104pub enum CC2S_A {
105 #[doc = "0: CC2 channel is configured as output"]
106 Output = 0,
107}
108impl From<CC2S_A> for u8 {
109 #[inline(always)]
110 fn from(variant: CC2S_A) -> Self {
111 variant as _
112 }
113}
114#[doc = "Field `CC2S` reader - Capture/Compare 2 selection"]
115pub type CC2S_R = crate::FieldReader<u8, CC2S_A>;
116impl CC2S_R {
117 #[doc = "Get enumerated values variant"]
118 #[inline(always)]
119 pub fn variant(&self) -> Option<CC2S_A> {
120 match self.bits {
121 0 => Some(CC2S_A::Output),
122 _ => None,
123 }
124 }
125 #[doc = "Checks if the value of the field is `Output`"]
126 #[inline(always)]
127 pub fn is_output(&self) -> bool {
128 *self == CC2S_A::Output
129 }
130}
131#[doc = "Field `CC2S` writer - Capture/Compare 2 selection"]
132pub type CC2S_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCMR1_OUTPUT_SPEC, u8, CC2S_A, 2, O>;
133impl<'a, const O: u8> CC2S_W<'a, O> {
134 #[doc = "CC2 channel is configured as output"]
135 #[inline(always)]
136 pub fn output(self) -> &'a mut W {
137 self.variant(CC2S_A::Output)
138 }
139}
140#[doc = "Field `OC1CE` reader - Output compare 1 clear enable"]
141pub type OC1CE_R = crate::BitReader<bool>;
142#[doc = "Field `OC1CE` writer - Output compare 1 clear enable"]
143pub type OC1CE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
144#[doc = "Output compare 1 mode\n\nValue on reset: 0"]
145#[derive(Clone, Copy, Debug, PartialEq)]
146#[repr(u8)]
147pub enum OC1M_A {
148 #[doc = "0: The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"]
149 Frozen = 0,
150 #[doc = "1: Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"]
151 ActiveOnMatch = 1,
152 #[doc = "2: Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"]
153 InactiveOnMatch = 2,
154 #[doc = "3: OCyREF toggles when TIMx_CNT=TIMx_CCRy"]
155 Toggle = 3,
156 #[doc = "4: OCyREF is forced low"]
157 ForceInactive = 4,
158 #[doc = "5: OCyREF is forced high"]
159 ForceActive = 5,
160 #[doc = "6: In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active"]
161 PwmMode1 = 6,
162 #[doc = "7: Inversely to PwmMode1"]
163 PwmMode2 = 7,
164}
165impl From<OC1M_A> for u8 {
166 #[inline(always)]
167 fn from(variant: OC1M_A) -> Self {
168 variant as _
169 }
170}
171#[doc = "Field `OC1M` reader - Output compare 1 mode"]
172pub type OC1M_R = crate::FieldReader<u8, OC1M_A>;
173impl OC1M_R {
174 #[doc = "Get enumerated values variant"]
175 #[inline(always)]
176 pub fn variant(&self) -> OC1M_A {
177 match self.bits {
178 0 => OC1M_A::Frozen,
179 1 => OC1M_A::ActiveOnMatch,
180 2 => OC1M_A::InactiveOnMatch,
181 3 => OC1M_A::Toggle,
182 4 => OC1M_A::ForceInactive,
183 5 => OC1M_A::ForceActive,
184 6 => OC1M_A::PwmMode1,
185 7 => OC1M_A::PwmMode2,
186 _ => unreachable!(),
187 }
188 }
189 #[doc = "Checks if the value of the field is `Frozen`"]
190 #[inline(always)]
191 pub fn is_frozen(&self) -> bool {
192 *self == OC1M_A::Frozen
193 }
194 #[doc = "Checks if the value of the field is `ActiveOnMatch`"]
195 #[inline(always)]
196 pub fn is_active_on_match(&self) -> bool {
197 *self == OC1M_A::ActiveOnMatch
198 }
199 #[doc = "Checks if the value of the field is `InactiveOnMatch`"]
200 #[inline(always)]
201 pub fn is_inactive_on_match(&self) -> bool {
202 *self == OC1M_A::InactiveOnMatch
203 }
204 #[doc = "Checks if the value of the field is `Toggle`"]
205 #[inline(always)]
206 pub fn is_toggle(&self) -> bool {
207 *self == OC1M_A::Toggle
208 }
209 #[doc = "Checks if the value of the field is `ForceInactive`"]
210 #[inline(always)]
211 pub fn is_force_inactive(&self) -> bool {
212 *self == OC1M_A::ForceInactive
213 }
214 #[doc = "Checks if the value of the field is `ForceActive`"]
215 #[inline(always)]
216 pub fn is_force_active(&self) -> bool {
217 *self == OC1M_A::ForceActive
218 }
219 #[doc = "Checks if the value of the field is `PwmMode1`"]
220 #[inline(always)]
221 pub fn is_pwm_mode1(&self) -> bool {
222 *self == OC1M_A::PwmMode1
223 }
224 #[doc = "Checks if the value of the field is `PwmMode2`"]
225 #[inline(always)]
226 pub fn is_pwm_mode2(&self) -> bool {
227 *self == OC1M_A::PwmMode2
228 }
229}
230#[doc = "Field `OC1M` writer - Output compare 1 mode"]
231pub type OC1M_W<'a, const O: u8> =
232 crate::FieldWriterSafe<'a, u32, CCMR1_OUTPUT_SPEC, u8, OC1M_A, 3, O>;
233impl<'a, const O: u8> OC1M_W<'a, O> {
234 #[doc = "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs"]
235 #[inline(always)]
236 pub fn frozen(self) -> &'a mut W {
237 self.variant(OC1M_A::Frozen)
238 }
239 #[doc = "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register"]
240 #[inline(always)]
241 pub fn active_on_match(self) -> &'a mut W {
242 self.variant(OC1M_A::ActiveOnMatch)
243 }
244 #[doc = "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register"]
245 #[inline(always)]
246 pub fn inactive_on_match(self) -> &'a mut W {
247 self.variant(OC1M_A::InactiveOnMatch)
248 }
249 #[doc = "OCyREF toggles when TIMx_CNT=TIMx_CCRy"]
250 #[inline(always)]
251 pub fn toggle(self) -> &'a mut W {
252 self.variant(OC1M_A::Toggle)
253 }
254 #[doc = "OCyREF is forced low"]
255 #[inline(always)]
256 pub fn force_inactive(self) -> &'a mut W {
257 self.variant(OC1M_A::ForceInactive)
258 }
259 #[doc = "OCyREF is forced high"]
260 #[inline(always)]
261 pub fn force_active(self) -> &'a mut W {
262 self.variant(OC1M_A::ForceActive)
263 }
264 #[doc = "In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active"]
265 #[inline(always)]
266 pub fn pwm_mode1(self) -> &'a mut W {
267 self.variant(OC1M_A::PwmMode1)
268 }
269 #[doc = "Inversely to PwmMode1"]
270 #[inline(always)]
271 pub fn pwm_mode2(self) -> &'a mut W {
272 self.variant(OC1M_A::PwmMode2)
273 }
274}
275#[doc = "Output compare 1 preload enable\n\nValue on reset: 0"]
276#[derive(Clone, Copy, Debug, PartialEq)]
277pub enum OC1PE_A {
278 #[doc = "0: Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately"]
279 Disabled = 0,
280 #[doc = "1: Preload register on CCR1 enabled. Preload value is loaded into active register on each update event"]
281 Enabled = 1,
282}
283impl From<OC1PE_A> for bool {
284 #[inline(always)]
285 fn from(variant: OC1PE_A) -> Self {
286 variant as u8 != 0
287 }
288}
289#[doc = "Field `OC1PE` reader - Output compare 1 preload enable"]
290pub type OC1PE_R = crate::BitReader<OC1PE_A>;
291impl OC1PE_R {
292 #[doc = "Get enumerated values variant"]
293 #[inline(always)]
294 pub fn variant(&self) -> OC1PE_A {
295 match self.bits {
296 false => OC1PE_A::Disabled,
297 true => OC1PE_A::Enabled,
298 }
299 }
300 #[doc = "Checks if the value of the field is `Disabled`"]
301 #[inline(always)]
302 pub fn is_disabled(&self) -> bool {
303 *self == OC1PE_A::Disabled
304 }
305 #[doc = "Checks if the value of the field is `Enabled`"]
306 #[inline(always)]
307 pub fn is_enabled(&self) -> bool {
308 *self == OC1PE_A::Enabled
309 }
310}
311#[doc = "Field `OC1PE` writer - Output compare 1 preload enable"]
312pub type OC1PE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, OC1PE_A, O>;
313impl<'a, const O: u8> OC1PE_W<'a, O> {
314 #[doc = "Preload register on CCR1 disabled. New values written to CCR1 are taken into account immediately"]
315 #[inline(always)]
316 pub fn disabled(self) -> &'a mut W {
317 self.variant(OC1PE_A::Disabled)
318 }
319 #[doc = "Preload register on CCR1 enabled. Preload value is loaded into active register on each update event"]
320 #[inline(always)]
321 pub fn enabled(self) -> &'a mut W {
322 self.variant(OC1PE_A::Enabled)
323 }
324}
325#[doc = "Field `OC1FE` reader - Output compare 1 fast enable"]
326pub type OC1FE_R = crate::BitReader<bool>;
327#[doc = "Field `OC1FE` writer - Output compare 1 fast enable"]
328pub type OC1FE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCMR1_OUTPUT_SPEC, bool, O>;
329#[doc = "Capture/Compare 1 selection\n\nValue on reset: 0"]
330#[derive(Clone, Copy, Debug, PartialEq)]
331#[repr(u8)]
332pub enum CC1S_A {
333 #[doc = "0: CC1 channel is configured as output"]
334 Output = 0,
335}
336impl From<CC1S_A> for u8 {
337 #[inline(always)]
338 fn from(variant: CC1S_A) -> Self {
339 variant as _
340 }
341}
342#[doc = "Field `CC1S` reader - Capture/Compare 1 selection"]
343pub type CC1S_R = crate::FieldReader<u8, CC1S_A>;
344impl CC1S_R {
345 #[doc = "Get enumerated values variant"]
346 #[inline(always)]
347 pub fn variant(&self) -> Option<CC1S_A> {
348 match self.bits {
349 0 => Some(CC1S_A::Output),
350 _ => None,
351 }
352 }
353 #[doc = "Checks if the value of the field is `Output`"]
354 #[inline(always)]
355 pub fn is_output(&self) -> bool {
356 *self == CC1S_A::Output
357 }
358}
359#[doc = "Field `CC1S` writer - Capture/Compare 1 selection"]
360pub type CC1S_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCMR1_OUTPUT_SPEC, u8, CC1S_A, 2, O>;
361impl<'a, const O: u8> CC1S_W<'a, O> {
362 #[doc = "CC1 channel is configured as output"]
363 #[inline(always)]
364 pub fn output(self) -> &'a mut W {
365 self.variant(CC1S_A::Output)
366 }
367}
368impl R {
369 #[doc = "Bit 15 - Output compare 2 clear enable"]
370 #[inline(always)]
371 pub fn oc2ce(&self) -> OC2CE_R {
372 OC2CE_R::new(((self.bits >> 15) & 1) != 0)
373 }
374 #[doc = "Bits 12:14 - Output compare 2 mode"]
375 #[inline(always)]
376 pub fn oc2m(&self) -> OC2M_R {
377 OC2M_R::new(((self.bits >> 12) & 7) as u8)
378 }
379 #[doc = "Bit 11 - Output compare 2 preload enable"]
380 #[inline(always)]
381 pub fn oc2pe(&self) -> OC2PE_R {
382 OC2PE_R::new(((self.bits >> 11) & 1) != 0)
383 }
384 #[doc = "Bit 10 - Output compare 2 fast enable"]
385 #[inline(always)]
386 pub fn oc2fe(&self) -> OC2FE_R {
387 OC2FE_R::new(((self.bits >> 10) & 1) != 0)
388 }
389 #[doc = "Bits 8:9 - Capture/Compare 2 selection"]
390 #[inline(always)]
391 pub fn cc2s(&self) -> CC2S_R {
392 CC2S_R::new(((self.bits >> 8) & 3) as u8)
393 }
394 #[doc = "Bit 7 - Output compare 1 clear enable"]
395 #[inline(always)]
396 pub fn oc1ce(&self) -> OC1CE_R {
397 OC1CE_R::new(((self.bits >> 7) & 1) != 0)
398 }
399 #[doc = "Bits 4:6 - Output compare 1 mode"]
400 #[inline(always)]
401 pub fn oc1m(&self) -> OC1M_R {
402 OC1M_R::new(((self.bits >> 4) & 7) as u8)
403 }
404 #[doc = "Bit 3 - Output compare 1 preload enable"]
405 #[inline(always)]
406 pub fn oc1pe(&self) -> OC1PE_R {
407 OC1PE_R::new(((self.bits >> 3) & 1) != 0)
408 }
409 #[doc = "Bit 2 - Output compare 1 fast enable"]
410 #[inline(always)]
411 pub fn oc1fe(&self) -> OC1FE_R {
412 OC1FE_R::new(((self.bits >> 2) & 1) != 0)
413 }
414 #[doc = "Bits 0:1 - Capture/Compare 1 selection"]
415 #[inline(always)]
416 pub fn cc1s(&self) -> CC1S_R {
417 CC1S_R::new((self.bits & 3) as u8)
418 }
419}
420impl W {
421 #[doc = "Bit 15 - Output compare 2 clear enable"]
422 #[inline(always)]
423 pub fn oc2ce(&mut self) -> OC2CE_W<15> {
424 OC2CE_W::new(self)
425 }
426 #[doc = "Bits 12:14 - Output compare 2 mode"]
427 #[inline(always)]
428 pub fn oc2m(&mut self) -> OC2M_W<12> {
429 OC2M_W::new(self)
430 }
431 #[doc = "Bit 11 - Output compare 2 preload enable"]
432 #[inline(always)]
433 pub fn oc2pe(&mut self) -> OC2PE_W<11> {
434 OC2PE_W::new(self)
435 }
436 #[doc = "Bit 10 - Output compare 2 fast enable"]
437 #[inline(always)]
438 pub fn oc2fe(&mut self) -> OC2FE_W<10> {
439 OC2FE_W::new(self)
440 }
441 #[doc = "Bits 8:9 - Capture/Compare 2 selection"]
442 #[inline(always)]
443 pub fn cc2s(&mut self) -> CC2S_W<8> {
444 CC2S_W::new(self)
445 }
446 #[doc = "Bit 7 - Output compare 1 clear enable"]
447 #[inline(always)]
448 pub fn oc1ce(&mut self) -> OC1CE_W<7> {
449 OC1CE_W::new(self)
450 }
451 #[doc = "Bits 4:6 - Output compare 1 mode"]
452 #[inline(always)]
453 pub fn oc1m(&mut self) -> OC1M_W<4> {
454 OC1M_W::new(self)
455 }
456 #[doc = "Bit 3 - Output compare 1 preload enable"]
457 #[inline(always)]
458 pub fn oc1pe(&mut self) -> OC1PE_W<3> {
459 OC1PE_W::new(self)
460 }
461 #[doc = "Bit 2 - Output compare 1 fast enable"]
462 #[inline(always)]
463 pub fn oc1fe(&mut self) -> OC1FE_W<2> {
464 OC1FE_W::new(self)
465 }
466 #[doc = "Bits 0:1 - Capture/Compare 1 selection"]
467 #[inline(always)]
468 pub fn cc1s(&mut self) -> CC1S_W<0> {
469 CC1S_W::new(self)
470 }
471 #[doc = "Writes raw bits to the register."]
472 #[inline(always)]
473 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
474 self.0.bits(bits);
475 self
476 }
477}
478#[doc = "capture/compare mode register 1 (output mode)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccmr1_output](index.html) module"]
479pub struct CCMR1_OUTPUT_SPEC;
480impl crate::RegisterSpec for CCMR1_OUTPUT_SPEC {
481 type Ux = u32;
482}
483#[doc = "`read()` method returns [ccmr1_output::R](R) reader structure"]
484impl crate::Readable for CCMR1_OUTPUT_SPEC {
485 type Reader = R;
486}
487#[doc = "`write(|w| ..)` method takes [ccmr1_output::W](W) writer structure"]
488impl crate::Writable for CCMR1_OUTPUT_SPEC {
489 type Writer = W;
490}
491#[doc = "`reset()` method sets CCMR1_Output to value 0"]
492impl crate::Resettable for CCMR1_OUTPUT_SPEC {
493 #[inline(always)]
494 fn reset_value() -> Self::Ux {
495 0
496 }
497}