stm32f0/stm32f0x2/adc/
cfgr2.rs

1#[doc = "Register `CFGR2` reader"]
2pub struct R(crate::R<CFGR2_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CFGR2_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CFGR2_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CFGR2_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CFGR2` writer"]
17pub struct W(crate::W<CFGR2_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CFGR2_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CFGR2_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CFGR2_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "ADC clock mode\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum CKMODE_A {
41    #[doc = "0: Asynchronous clock mode"]
42    Adcclk = 0,
43    #[doc = "1: Synchronous clock mode (PCLK/2)"]
44    PclkDiv2 = 1,
45    #[doc = "2: Sychronous clock mode (PCLK/4)"]
46    PclkDiv4 = 2,
47}
48impl From<CKMODE_A> for u8 {
49    #[inline(always)]
50    fn from(variant: CKMODE_A) -> Self {
51        variant as _
52    }
53}
54#[doc = "Field `CKMODE` reader - ADC clock mode"]
55pub type CKMODE_R = crate::FieldReader<u8, CKMODE_A>;
56impl CKMODE_R {
57    #[doc = "Get enumerated values variant"]
58    #[inline(always)]
59    pub fn variant(&self) -> Option<CKMODE_A> {
60        match self.bits {
61            0 => Some(CKMODE_A::Adcclk),
62            1 => Some(CKMODE_A::PclkDiv2),
63            2 => Some(CKMODE_A::PclkDiv4),
64            _ => None,
65        }
66    }
67    #[doc = "Checks if the value of the field is `Adcclk`"]
68    #[inline(always)]
69    pub fn is_adcclk(&self) -> bool {
70        *self == CKMODE_A::Adcclk
71    }
72    #[doc = "Checks if the value of the field is `PclkDiv2`"]
73    #[inline(always)]
74    pub fn is_pclk_div2(&self) -> bool {
75        *self == CKMODE_A::PclkDiv2
76    }
77    #[doc = "Checks if the value of the field is `PclkDiv4`"]
78    #[inline(always)]
79    pub fn is_pclk_div4(&self) -> bool {
80        *self == CKMODE_A::PclkDiv4
81    }
82}
83#[doc = "Field `CKMODE` writer - ADC clock mode"]
84pub type CKMODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CFGR2_SPEC, u8, CKMODE_A, 2, O>;
85impl<'a, const O: u8> CKMODE_W<'a, O> {
86    #[doc = "Asynchronous clock mode"]
87    #[inline(always)]
88    pub fn adcclk(self) -> &'a mut W {
89        self.variant(CKMODE_A::Adcclk)
90    }
91    #[doc = "Synchronous clock mode (PCLK/2)"]
92    #[inline(always)]
93    pub fn pclk_div2(self) -> &'a mut W {
94        self.variant(CKMODE_A::PclkDiv2)
95    }
96    #[doc = "Sychronous clock mode (PCLK/4)"]
97    #[inline(always)]
98    pub fn pclk_div4(self) -> &'a mut W {
99        self.variant(CKMODE_A::PclkDiv4)
100    }
101}
102impl R {
103    #[doc = "Bits 30:31 - ADC clock mode"]
104    #[inline(always)]
105    pub fn ckmode(&self) -> CKMODE_R {
106        CKMODE_R::new(((self.bits >> 30) & 3) as u8)
107    }
108}
109impl W {
110    #[doc = "Bits 30:31 - ADC clock mode"]
111    #[inline(always)]
112    pub fn ckmode(&mut self) -> CKMODE_W<30> {
113        CKMODE_W::new(self)
114    }
115    #[doc = "Writes raw bits to the register."]
116    #[inline(always)]
117    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
118        self.0.bits(bits);
119        self
120    }
121}
122#[doc = "configuration register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfgr2](index.html) module"]
123pub struct CFGR2_SPEC;
124impl crate::RegisterSpec for CFGR2_SPEC {
125    type Ux = u32;
126}
127#[doc = "`read()` method returns [cfgr2::R](R) reader structure"]
128impl crate::Readable for CFGR2_SPEC {
129    type Reader = R;
130}
131#[doc = "`write(|w| ..)` method takes [cfgr2::W](W) writer structure"]
132impl crate::Writable for CFGR2_SPEC {
133    type Writer = W;
134}
135#[doc = "`reset()` method sets CFGR2 to value 0x8000"]
136impl crate::Resettable for CFGR2_SPEC {
137    #[inline(always)]
138    fn reset_value() -> Self::Ux {
139        0x8000
140    }
141}
stm32f0/stm32f0x2/adc/cfgr2.rs

stm32f0/stm32f0x2/adc/
cfgr2.rs
